xloader: Panda - bugfix mux redefinition different values
[x-loader:x-loader.git] / include / asm / arch-omap4 / mux.h
1 /* Copyright 2009
2  * Texas Instruments, <www.ti.com>
3  * Syed Rafiuddin <rafiuddin.syed@ti.com>
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License as
7  * published by the Free Software Foundation; either version 2 of
8  * the License, or (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18  * MA 02111-1307 USA
19  */
20 #ifndef _OMAP4430_MUX_H_
21 #define _OMAP4430_MUX_H_
22
23 /*
24  * OFF_PD       - Off mode pull type down
25  * OFF_PU       - Off mode pull type up
26  * OFF_OUT_PTD  - Off Mode Mux low for OUT
27  * OFF_OUT_PTU  - Off Mode Mux high for OUT
28  * OFF_IN       - Off Mode Mux set to IN
29  * OFF_OUT      - Off Mode Mux set to OUT
30  * OFF_EN       - Off Mode Mux Enable
31  * IEN          - Input Enable
32  * IDIS         - Input Disable
33  * PTD          - Pull type Down
34  * PTU          - Pull type Up
35  * DIS          - Pull type selection is inactive
36  * EN           - Pull type selection is active
37  * M0           - Mode 0
38  */
39 #ifdef CONFIG_OFF_PADCONF
40 #define OFF_PD          (1 << 12)
41 #define OFF_PU          (3 << 12)
42 #define OFF_OUT_PTD     (0 << 10)
43 #define OFF_OUT_PTU     (2 << 10)
44 #define OFF_IN          (1 << 10)
45 #define OFF_OUT         (0 << 10)
46 #define OFF_EN          (1 << 9)
47 #else
48 #define OFF_PD          (0 << 12)
49 #define OFF_PU          (0 << 12)
50 #define OFF_OUT_PTD     (0 << 10)
51 #define OFF_OUT_PTU     (0 << 10)
52 #define OFF_IN          (0 << 10)
53 #define OFF_OUT         (0 << 10)
54 #define OFF_EN          (0 << 9)
55 #endif
56
57 #define IEN             (1 << 8)
58 #define IDIS            (0 << 8)
59 #define PTU             (3 << 3)
60 #define PTD             (1 << 3)
61 #define EN              (1 << 3)
62 #define DIS             (0 << 3)
63
64 #define M0              0
65 #define M1              1
66 #define M2              2
67 #define M3              3
68 #define M4              4
69 #define M5              5
70 #define M6              6
71 #define M7              7
72
73 #ifdef CONFIG_OFF_PADCONF
74 #define OFF_IN_PD       (OFF_PD | OFF_IN | OFF_EN)
75 #define OFF_IN_PU       (OFF_PU | OFF_IN | OFF_EN)
76 #define OFF_OUT_PD      (OFF_OUT_PTD | OFF_OUT | OFF_EN)
77 #define OFF_OUT_PU      (OFF_OUT_PTU | OFF_OUT | OFF_EN)
78 #else
79 #define OFF_IN_PD       0
80 #define OFF_IN_PU       0
81 #define OFF_OUT_PD      0
82 #define OFF_OUT_PU      0
83 #endif /* #ifdef CONFIG_OFF_PADCONF */
84
85 /*
86  * To get the actual address the offset has to added
87  * with OMAP44XX_CTRL_BASE to get the actual address
88  */
89
90 /* OMAP4 SPECIFIC PADCONF REGISTERS */
91
92 #define CONTROL_PADCONF_CORE_REVISION           0x0000
93 #define CONTROL_PADCONF_CORE_HWINFO             0x0004
94 #define CONTROL_PADCONF_CORE_SYSCONFIG          0x0010
95 #define CONTROL_PADCONF_GPMC_AD0                0x0040
96 #define CONTROL_PADCONF_GPMC_AD1                0x0042
97 #define CONTROL_PADCONF_GPMC_AD2                0x0044
98 #define CONTROL_PADCONF_GPMC_AD3                0x0046
99 #define CONTROL_PADCONF_GPMC_AD4                0x0048
100 #define CONTROL_PADCONF_GPMC_AD5                0x004A
101 #define CONTROL_PADCONF_GPMC_AD6                0x004C
102 #define CONTROL_PADCONF_GPMC_AD7                0x004E
103 #define CONTROL_PADCONF_GPMC_AD8                0x0050
104 #define CONTROL_PADCONF_GPMC_AD9                0x0052
105 #define CONTROL_PADCONF_GPMC_AD10               0x0054
106 #define CONTROL_PADCONF_GPMC_AD11               0x0056
107 #define CONTROL_PADCONF_GPMC_AD12               0x0058
108 #define CONTROL_PADCONF_GPMC_AD13               0x005A
109 #define CONTROL_PADCONF_GPMC_AD14               0x005C
110 #define CONTROL_PADCONF_GPMC_AD15               0x005E
111 #define CONTROL_PADCONF_GPMC_A16                0x0060
112 #define CONTROL_PADCONF_GPMC_A17                0x0062
113 #define CONTROL_PADCONF_GPMC_A18                0x0064
114 #define CONTROL_PADCONF_GPMC_A19                0x0066
115 #define CONTROL_PADCONF_GPMC_A20                0x0068
116 #define CONTROL_PADCONF_GPMC_A21                0x006A
117 #define CONTROL_PADCONF_GPMC_A22                0x006C
118 #define CONTROL_PADCONF_GPMC_A23                0x006E
119 #define CONTROL_PADCONF_GPMC_A24                0x0070
120 #define CONTROL_PADCONF_GPMC_A25                0x0072
121 #define CONTROL_PADCONF_GPMC_NCS0               0x0074
122 #define CONTROL_PADCONF_GPMC_NCS1               0x0076
123 #define CONTROL_PADCONF_GPMC_NCS2               0x0078
124 #define CONTROL_PADCONF_GPMC_NCS3               0x007A
125 #define CONTROL_PADCONF_GPMC_NWP                0x007C
126 #define CONTROL_PADCONF_GPMC_CLK                0x007E
127 #define CONTROL_PADCONF_GPMC_NADV_ALE           0x0080
128 #define CONTROL_PADCONF_GPMC_NOE                0x0082
129 #define CONTROL_PADCONF_GPMC_NWE                0x0084
130 #define CONTROL_PADCONF_GPMC_NBE0_CLE           0x0086
131 #define CONTROL_PADCONF_GPMC_NBE1               0x0088
132 #define CONTROL_PADCONF_GPMC_WAIT0              0x008A
133 #define CONTROL_PADCONF_GPMC_WAIT1              0x008C
134 #define CONTROL_PADCONF_C2C_DATA11              0x008E
135 #define CONTROL_PADCONF_C2C_DATA12              0x0090
136 #define CONTROL_PADCONF_C2C_DATA13              0x0092
137 #define CONTROL_PADCONF_C2C_DATA14              0x0094
138 #define CONTROL_PADCONF_C2C_DATA15              0x0096
139 #define CONTROL_PADCONF_HDMI_HPD                0x0098
140 #define CONTROL_PADCONF_HDMI_CEC                0x009A
141 #define CONTROL_PADCONF_HDMI_DDC_SCL            0x009C
142 #define CONTROL_PADCONF_HDMI_DDC_SDA            0x009E
143 #define CONTROL_PADCONF_CSI21_DX0               0x00A0
144 #define CONTROL_PADCONF_CSI21_DY0               0x00A2
145 #define CONTROL_PADCONF_CSI21_DX1               0x00A4
146 #define CONTROL_PADCONF_CSI21_DY1               0x00A6
147 #define CONTROL_PADCONF_CSI21_DX2               0x00A8
148 #define CONTROL_PADCONF_CSI21_DY2               0x00AA
149 #define CONTROL_PADCONF_CSI21_DX3               0x00AC
150 #define CONTROL_PADCONF_CSI21_DY3               0x00AE
151 #define CONTROL_PADCONF_CSI21_DX4               0x00B0
152 #define CONTROL_PADCONF_CSI21_DY4               0x00B2
153 #define CONTROL_PADCONF_CSI22_DX0               0x00B4
154 #define CONTROL_PADCONF_CSI22_DY0               0x00B6
155 #define CONTROL_PADCONF_CSI22_DX1               0x00B8
156 #define CONTROL_PADCONF_CSI22_DY1               0x00BA
157 #define CONTROL_PADCONF_CAM_SHUTTER             0x00BC
158 #define CONTROL_PADCONF_CAM_STROBE              0x00BE
159 #define CONTROL_PADCONF_CAM_GLOBALRESET         0x00C0
160 #define CONTROL_PADCONF_USBB1_ULPITLL_CLK       0x00C2
161 #define CONTROL_PADCONF_USBB1_ULPITLL_STP       0x00C4
162 #define CONTROL_PADCONF_USBB1_ULPITLL_DIR       0x00C6
163 #define CONTROL_PADCONF_USBB1_ULPITLL_NXT       0x00C8
164 #define CONTROL_PADCONF_USBB1_ULPITLL_DAT0      0x00CA
165 #define CONTROL_PADCONF_USBB1_ULPITLL_DAT1      0x00CC
166 #define CONTROL_PADCONF_USBB1_ULPITLL_DAT2      0x00CE
167 #define CONTROL_PADCONF_USBB1_ULPITLL_DAT3      0x00D0
168 #define CONTROL_PADCONF_USBB1_ULPITLL_DAT4      0x00D2
169 #define CONTROL_PADCONF_USBB1_ULPITLL_DAT5      0x00D4
170 #define CONTROL_PADCONF_USBB1_ULPITLL_DAT6      0x00D6
171 #define CONTROL_PADCONF_USBB1_ULPITLL_DAT7      0x00D8
172 #define CONTROL_PADCONF_USBB1_HSIC_DATA         0x00DA
173 #define CONTROL_PADCONF_USBB1_HSIC_STROBE       0x00DC
174 #define CONTROL_PADCONF_USBC1_ICUSB_DP          0x00DE
175 #define CONTROL_PADCONF_USBC1_ICUSB_DM          0x00E0
176 #define CONTROL_PADCONF_SDMMC1_CLK              0x00E2
177 #define CONTROL_PADCONF_SDMMC1_CMD              0x00E4
178 #define CONTROL_PADCONF_SDMMC1_DAT0             0x00E6
179 #define CONTROL_PADCONF_SDMMC1_DAT1             0x00E8
180 #define CONTROL_PADCONF_SDMMC1_DAT2             0x00EA
181 #define CONTROL_PADCONF_SDMMC1_DAT3             0x00EC
182 #define CONTROL_PADCONF_SDMMC1_DAT4             0x00EE
183 #define CONTROL_PADCONF_SDMMC1_DAT5             0x00F0
184 #define CONTROL_PADCONF_SDMMC1_DAT6             0x00F2
185 #define CONTROL_PADCONF_SDMMC1_DAT7             0x00F4
186 #define CONTROL_PADCONF_ABE_MCBSP2_CLKX         0x00F6
187 #define CONTROL_PADCONF_ABE_MCBSP2_DR           0x00F8
188 #define CONTROL_PADCONF_ABE_MCBSP2_DX           0x00FA
189 #define CONTROL_PADCONF_ABE_MCBSP2_FSX          0x00FC
190 #define CONTROL_PADCONF_ABE_MCBSP1_CLKX         0x00FE
191 #define CONTROL_PADCONF_ABE_MCBSP1_DR           0x0100
192 #define CONTROL_PADCONF_ABE_MCBSP1_DX           0x0102
193 #define CONTROL_PADCONF_ABE_MCBSP1_FSX          0x0104
194 #define CONTROL_PADCONF_ABE_PDM_UL_DATA         0x0106
195 #define CONTROL_PADCONF_ABE_PDM_DL_DATA         0x0108
196 #define CONTROL_PADCONF_ABE_PDM_FRAME           0x010A
197 #define CONTROL_PADCONF_ABE_PDM_LB_CLK          0x010C
198 #define CONTROL_PADCONF_ABE_CLKS                0x010E
199 #define CONTROL_PADCONF_ABE_DMIC_CLK1           0x0110
200 #define CONTROL_PADCONF_ABE_DMIC_DIN1           0x0112
201 #define CONTROL_PADCONF_ABE_DMIC_DIN2           0x0114
202 #define CONTROL_PADCONF_ABE_DMIC_DIN3           0x0116
203 #define CONTROL_PADCONF_UART2_CTS               0x0118
204 #define CONTROL_PADCONF_UART2_RTS               0x011A
205 #define CONTROL_PADCONF_UART2_RX                0x011C
206 #define CONTROL_PADCONF_UART2_TX                0x011E
207 #define CONTROL_PADCONF_HDQ_SIO                 0x0120
208 #define CONTROL_PADCONF_I2C1_SCL                0x0122
209 #define CONTROL_PADCONF_I2C1_SDA                0x0124
210 #define CONTROL_PADCONF_I2C2_SCL                0x0126
211 #define CONTROL_PADCONF_I2C2_SDA                0x0128
212 #define CONTROL_PADCONF_I2C3_SCL                0x012A
213 #define CONTROL_PADCONF_I2C3_SDA                0x012C
214 #define CONTROL_PADCONF_I2C4_SCL                0x012E
215 #define CONTROL_PADCONF_I2C4_SDA                0x0130
216 #define CONTROL_PADCONF_MCSPI1_CLK              0x0132
217 #define CONTROL_PADCONF_MCSPI1_SOMI             0x0134
218 #define CONTROL_PADCONF_MCSPI1_SIMO             0x0136
219 #define CONTROL_PADCONF_MCSPI1_CS0              0x0138
220 #define CONTROL_PADCONF_MCSPI1_CS1              0x013A
221 #define CONTROL_PADCONF_MCSPI1_CS2              0x013C
222 #define CONTROL_PADCONF_MCSPI1_CS3              0x013E
223 #define CONTROL_PADCONF_UART3_CTS_RCTX          0x0140
224 #define CONTROL_PADCONF_UART3_RTS_SD            0x0142
225 #define CONTROL_PADCONF_UART3_RX_IRRX           0x0144
226 #define CONTROL_PADCONF_UART3_TX_IRTX           0x0146
227 #define CONTROL_PADCONF_SDMMC5_CLK              0x0148
228 #define CONTROL_PADCONF_SDMMC5_CMD              0x014A
229 #define CONTROL_PADCONF_SDMMC5_DAT0             0x014C
230 #define CONTROL_PADCONF_SDMMC5_DAT1             0x014E
231 #define CONTROL_PADCONF_SDMMC5_DAT2             0x0150
232 #define CONTROL_PADCONF_SDMMC5_DAT3             0x0152
233 #define CONTROL_PADCONF_MCSPI4_CLK              0x0154
234 #define CONTROL_PADCONF_MCSPI4_SIMO             0x0156
235 #define CONTROL_PADCONF_MCSPI4_SOMI             0x0158
236 #define CONTROL_PADCONF_MCSPI4_CS0              0x015A
237 #define CONTROL_PADCONF_UART4_RX                0x015C
238 #define CONTROL_PADCONF_UART4_TX                0x015E
239 #define CONTROL_PADCONF_USBB2_ULPITLL_CLK       0x0160
240 #define CONTROL_PADCONF_USBB2_ULPITLL_STP       0x0162
241 #define CONTROL_PADCONF_USBB2_ULPITLL_DIR       0x0164
242 #define CONTROL_PADCONF_USBB2_ULPITLL_NXT       0x0166
243 #define CONTROL_PADCONF_USBB2_ULPITLL_DAT0      0x0168
244 #define CONTROL_PADCONF_USBB2_ULPITLL_DAT1      0x016A
245 #define CONTROL_PADCONF_USBB2_ULPITLL_DAT2      0x016C
246 #define CONTROL_PADCONF_USBB2_ULPITLL_DAT3      0x016E
247 #define CONTROL_PADCONF_USBB2_ULPITLL_DAT4      0x0170
248 #define CONTROL_PADCONF_USBB2_ULPITLL_DAT5      0x0172
249 #define CONTROL_PADCONF_USBB2_ULPITLL_DAT6      0x0174
250 #define CONTROL_PADCONF_USBB2_ULPITLL_DAT7      0x0176
251 #define CONTROL_PADCONF_USBB2_HSIC_DATA         0x0178
252 #define CONTROL_PADCONF_USBB2_HSIC_STROBE       0x017A
253 #define CONTROL_PADCONF_UNIPRO_TX0              0x017C
254 #define CONTROL_PADCONF_UNIPRO_TY0              0x017E
255 #define CONTROL_PADCONF_UNIPRO_TX1              0x0180
256 #define CONTROL_PADCONF_UNIPRO_TY1              0x0182
257 #define CONTROL_PADCONF_UNIPRO_TX2              0x0184
258 #define CONTROL_PADCONF_UNIPRO_TY2              0x0186
259 #define CONTROL_PADCONF_UNIPRO_RX0              0x0188
260 #define CONTROL_PADCONF_UNIPRO_RY0              0x018A
261 #define CONTROL_PADCONF_UNIPRO_RX1              0x018C
262 #define CONTROL_PADCONF_UNIPRO_RY1              0x018E
263 #define CONTROL_PADCONF_UNIPRO_RX2              0x0190
264 #define CONTROL_PADCONF_UNIPRO_RY2              0x0192
265 #define CONTROL_PADCONF_USBA0_OTG_CE            0x0194
266 #define CONTROL_PADCONF_USBA0_OTG_DP            0x0196
267 #define CONTROL_PADCONF_USBA0_OTG_DM            0x0198
268 #define CONTROL_PADCONF_FREF_CLK1_OUT           0x019A
269 #define CONTROL_PADCONF_FREF_CLK2_OUT           0x019C
270 #define CONTROL_PADCONF_SYS_NIRQ1               0x019E
271 #define CONTROL_PADCONF_SYS_NIRQ2               0x01A0
272 #define CONTROL_PADCONF_SYS_BOOT0               0x01A2
273 #define CONTROL_PADCONF_SYS_BOOT1               0x01A4
274 #define CONTROL_PADCONF_SYS_BOOT2               0x01A6
275 #define CONTROL_PADCONF_SYS_BOOT3               0x01A8
276 #define CONTROL_PADCONF_SYS_BOOT4               0x01AA
277 #define CONTROL_PADCONF_SYS_BOOT5               0x01AC
278 #define CONTROL_PADCONF_DPM_EMU0                0x01AE
279 #define CONTROL_PADCONF_DPM_EMU1                0x01B0
280 #define CONTROL_PADCONF_DPM_EMU2                0x01B2
281 #define CONTROL_PADCONF_DPM_EMU3                0x01B4
282 #define CONTROL_PADCONF_DPM_EMU4                0x01B6
283 #define CONTROL_PADCONF_DPM_EMU5                0x01B8
284 #define CONTROL_PADCONF_DPM_EMU6                0x01BA
285 #define CONTROL_PADCONF_DPM_EMU7                0x01BC
286 #define CONTROL_PADCONF_DPM_EMU8                0x01BE
287 #define CONTROL_PADCONF_DPM_EMU9                0x01C0
288 #define CONTROL_PADCONF_DPM_EMU10               0x01C2
289 #define CONTROL_PADCONF_DPM_EMU11               0x01C4
290 #define CONTROL_PADCONF_DPM_EMU12               0x01C6
291 #define CONTROL_PADCONF_DPM_EMU13               0x01C8
292 #define CONTROL_PADCONF_DPM_EMU14               0x01CA
293 #define CONTROL_PADCONF_DPM_EMU15               0x01CC
294 #define CONTROL_PADCONF_DPM_EMU16               0x01CE
295 #define CONTROL_PADCONF_DPM_EMU17               0x01D0
296 #define CONTROL_PADCONF_DPM_EMU18               0x01D2
297 #define CONTROL_PADCONF_DPM_EMU19               0x01D4
298 #define CONTROL_PADCONF_WAKEUPEVENT_0           0x01D8
299 #define CONTROL_PADCONF_WAKEUPEVENT_1           0x01DC
300 #define CONTROL_PADCONF_WAKEUPEVENT_2           0x01E0
301 #define CONTROL_PADCONF_WAKEUPEVENT_3           0x01E4
302 #define CONTROL_PADCONF_WAKEUPEVENT_4           0x01E8
303 #define CONTROL_PADCONF_WAKEUPEVENT_5           0x01EC
304 #define CONTROL_PADCONF_WAKEUPEVENT_6           0x01F0
305
306 #define CONTROL_PADCONF_GLOBAL                  0x05A2
307 #define CONTROL_PADCONF_MODE                    0x05A4
308 #define CONTROL_SMART1IO_PADCONF_0              0x05A8
309 #define CONTROL_SMART1IO_PADCONF_1              0x05AC
310 #define CONTROL_SMART2IO_PADCONF_0              0x05B0
311 #define CONTROL_SMART2IO_PADCONF_1              0x05B4
312 #define CONTROL_SMART3IO_PADCONF_0              0x05B8
313 #define CONTROL_SMART3IO_PADCONF_1              0x05BC
314 #define CONTROL_SMART3IO_PADCONF_2              0x05C0
315 #define CONTROL_USBB_HSIC                       0x05C4
316 #define CONTROL_SLIMBUS                         0x05C8
317 #define CONTROL_PBIASLITE                       0x0600
318 #define CONTROL_I2C_0                           0x0604
319 #define CONTROL_CAMERA_RX                       0x0608
320 #define CONTROL_AVDAC                           0x060C
321 #define CONTROL_HDMI_TX_PHY                     0x0610
322 #define CONTROL_MMC2                            0x0614
323 #define CONTROL_DSIPHY                          0x0618
324 #define CONTROL_MCBSPLP                         0x061C
325 #define CONTROL_USB2PHYCORE                     0x0620
326 #define CONTROL_I2C_1                           0x0624
327 #define CONTROL_MMC1                            0x0628
328 #define CONTROL_HSI                             0x062C
329 #define CONTROL_USB                             0x0630
330 #define CONTROL_HDQ                             0x0634
331 #define CONTROL_LPDDR2IO1_0                     0x0638
332 #define CONTROL_LPDDR2IO1_1                     0x063C
333 #define CONTROL_LPDDR2IO1_2                     0x0640
334 #define CONTROL_LPDDR2IO1_3                     0x0644
335 #define CONTROL_LPDDR2IO2_0                     0x0648
336 #define CONTROL_LPDDR2IO2_1                     0x064C
337 #define CONTROL_LPDDR2IO2_2                     0x0650
338 #define CONTROL_LPDDR2IO2_3                     0x0654
339 #define CONTROL_BUS_HOLD                        0x0658
340 #define CONTROL_C2C                             0x065C
341 #define CONTROL_CORE_CONTROL_SPARE_RW           0x0660
342 #define CONTROL_CORE_CONTROL_SPARE_R            0x0664
343 #define CONTROL_CORE_CONTROL_SPARE_R_C0         0x0668
344 #define CONTROL_EFUSE_1                         0x0700
345 #define CONTROL_EFUSE_2                         0x0704
346 #define CONTROL_EFUSE_3                         0x0708
347 #define CONTROL_EFUSE_4                         0x070C
348
349 #define CONTROL_PADCONF_WKUP_REVISION           0x0000
350 #define CONTROL_PADCONF_WKUP_HWINFO             0x0004
351 #define CONTROL_PADCONF_WKUP_SYSCONFIG          0x0010
352 #define CONTROL_WKUP_PAD0_SIM_IO                0x0040
353 #define CONTROL_WKUP_PAD1_SIM_CLK               0x0042
354 #define CONTROL_WKUP_PAD0_SIM_RESET             0x0044
355 #define CONTROL_WKUP_PAD1_SIM_CD                0x0046
356 #define CONTROL_WKUP_PAD0_SIM_PWRCTRL           0x0048
357 #define CONTROL_WKUP_PAD1_SR_SCL                0x004A
358 #define CONTROL_WKUP_PAD0_SR_SDA                0x004C
359 #define CONTROL_WKUP_PAD1_FREF_XTAL_IN          0x004E
360 #define CONTROL_WKUP_PAD0_FREF_SLICER_IN        0x0050
361 #define CONTROL_WKUP_PAD1_FREF_CLK_IOREQ        0x0052
362 #define CONTROL_WKUP_PAD0_FREF_CLK0_OUT         0x0054
363 #define CONTROL_WKUP_PAD1_FREF_CLK3_REQ         0x0056
364 #define CONTROL_WKUP_PAD0_FREF_CLK3_OUT         0x0058
365 #define CONTROL_WKUP_PAD1_FREF_CLK4_REQ         0x005A
366 #define CONTROL_WKUP_PAD0_FREF_CLK4_OUT         0x005C
367 #define CONTROL_WKUP_PAD1_SYS_32K               0x005E
368 #define CONTROL_WKUP_PAD0_SYS_NRESPWRON         0x0060
369 #define CONTROL_WKUP_PAD1_SYS_NRESWARM          0x0062
370 #define CONTROL_WKUP_PAD0_SYS_PWR_REQ           0x0064
371 #define CONTROL_WKUP_PAD1_SYS_PWRON_RESET       0x0066
372 #define CONTROL_WKUP_PAD0_SYS_BOOT6             0x0068
373 #define CONTROL_WKUP_PAD1_SYS_BOOT7             0x006A
374 #define CONTROL_WKUP_PAD0_JTAG_NTRST            0x006C
375 #define CONTROL_WKUP_PAD1_JTAG_TCK              0x006D
376 #define CONTROL_WKUP_PAD0_JTAG_RTCK             0x0070
377 #define CONTROL_WKUP_PAD1_JTAG_TMS_TMSC         0x0072
378 #define CONTROL_WKUP_PAD0_JTAG_TDI              0x0074
379 #define CONTROL_WKUP_PAD1_JTAG_TDO              0x0076
380 /*
381  * this is an accidental redefinition I think
382  * see earlier in this file
383  * it is not used anywhere yet
384  * #define CONTROL_PADCONF_WAKEUPEVENT_0                0x007C
385 */
386 #define CONTROL_SMART1NOPMIO_PADCONF_0          0x05A0
387 #define CONTROL_SMART1NOPMIO_PADCONF_1          0x05A4
388 /*
389  * this is an accidental redefinition I think
390  * see earlier in this file
391  * it is not used anywhere yet
392  * #define CONTROL_PADCONF_MODE                 0x05A8
393  */
394 #define CONTROL_XTAL_OSCILLATOR                 0x05AC
395 #define CONTROL_CONTROL_I2C_2                   0x0604
396 #define CONTROL_CONTROL_JTAG                    0x0608
397 #define CONTROL_CONTROL_SYS                     0x060C
398 #define CONTROL_WKUP_CONTROL_SPARE_RW           0x0614
399 #define CONTROL_WKUP_CONTROL_SPARE_R            0x0618
400 #define CONTROL_WKUP_CONTROL_SPARE_R_C0         0x061C
401
402 #endif