xloader: Panda - add led flashing debug code
[x-loader:vanni-pandaboard-x-loader.git] / board / omap4430panda / omap4430panda.c
1 /*
2  * (C) Copyright 2004-2009
3  * Texas Instruments, <www.ti.com>
4  * Richard Woodruff <r-woodruff2@ti.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License
11  * version 2 as published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23 #include <common.h>
24 #include <asm/arch/cpu.h>
25 #include <asm/io.h>
26 #include <asm/arch/bits.h>
27 #include <asm/arch/mux.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/arch/sys_info.h>
30 #include <asm/arch/clocks.h>
31 #include <asm/arch/mem.h>
32 #include <i2c.h>
33 #if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
34 #include <linux/mtd/nand_legacy.h>
35 #endif
36
37 /* EMIF and DMM registers */
38 #define EMIF1_BASE                      0x4c000000
39 #define EMIF2_BASE                      0x4d000000
40 #define DMM_BASE                        0x4e000000
41 /* EMIF */
42 #define EMIF_MOD_ID_REV                 0x0000
43 #define EMIF_STATUS                     0x0004
44 #define EMIF_SDRAM_CONFIG               0x0008
45 #define EMIF_LPDDR2_NVM_CONFIG          0x000C
46 #define EMIF_SDRAM_REF_CTRL             0x0010
47 #define EMIF_SDRAM_REF_CTRL_SHDW        0x0014
48 #define EMIF_SDRAM_TIM_1                0x0018
49 #define EMIF_SDRAM_TIM_1_SHDW           0x001C
50 #define EMIF_SDRAM_TIM_2                0x0020
51 #define EMIF_SDRAM_TIM_2_SHDW           0x0024
52 #define EMIF_SDRAM_TIM_3                0x0028
53 #define EMIF_SDRAM_TIM_3_SHDW           0x002C
54 #define EMIF_LPDDR2_NVM_TIM             0x0030
55 #define EMIF_LPDDR2_NVM_TIM_SHDW        0x0034
56 #define EMIF_PWR_MGMT_CTRL              0x0038
57 #define EMIF_PWR_MGMT_CTRL_SHDW         0x003C
58 #define EMIF_LPDDR2_MODE_REG_DATA       0x0040
59 #define EMIF_LPDDR2_MODE_REG_CFG        0x0050
60 #define EMIF_L3_CONFIG                  0x0054
61 #define EMIF_L3_CFG_VAL_1               0x0058
62 #define EMIF_L3_CFG_VAL_2               0x005C
63 #define IODFT_TLGC                      0x0060
64 #define EMIF_PERF_CNT_1                 0x0080
65 #define EMIF_PERF_CNT_2                 0x0084
66 #define EMIF_PERF_CNT_CFG               0x0088
67 #define EMIF_PERF_CNT_SEL               0x008C
68 #define EMIF_PERF_CNT_TIM               0x0090
69 #define EMIF_READ_IDLE_CTRL             0x0098
70 #define EMIF_READ_IDLE_CTRL_SHDW        0x009c
71 #define EMIF_ZQ_CONFIG                  0x00C8
72 #define EMIF_DDR_PHY_CTRL_1             0x00E4
73 #define EMIF_DDR_PHY_CTRL_1_SHDW        0x00E8
74 #define EMIF_DDR_PHY_CTRL_2             0x00EC
75
76 #define DMM_LISA_MAP_0                  0x0040
77 #define DMM_LISA_MAP_1                  0x0044
78 #define DMM_LISA_MAP_2                  0x0048
79 #define DMM_LISA_MAP_3                  0x004C
80
81 #define MR0_ADDR                        0
82 #define MR1_ADDR                        1
83 #define MR2_ADDR                        2
84 #define MR4_ADDR                        4
85 #define MR10_ADDR                       10
86 #define MR16_ADDR                       16
87 #define REF_EN                          0x40000000
88 /* defines for MR1 */
89 #define MR1_BL4                         2
90 #define MR1_BL8                         3
91 #define MR1_BL16                        4
92
93 #define MR1_BT_SEQ                      0
94 #define BT_INT                          1
95
96 #define MR1_WC                          0
97 #define MR1_NWC                         1
98
99 #define MR1_NWR3                        1
100 #define MR1_NWR4                        2
101 #define MR1_NWR5                        3
102 #define MR1_NWR6                        4
103 #define MR1_NWR7                        5
104 #define MR1_NWR8                        6
105
106 #define MR1_VALUE       ((MR1_NWR3 << 5) | (MR1_WC << 4) | (MR1_BT_SEQ << 3)  \
107                                                         | (MR1_BL8 << 0))
108
109 /* defines for MR2 */
110 #define MR2_RL3_WL1                     1
111 #define MR2_RL4_WL2                     2
112 #define MR2_RL5_WL2                     3
113 #define MR2_RL6_WL3                     4
114
115 /* defines for MR10 */
116 #define MR10_ZQINIT                     0xFF
117 #define MR10_ZQRESET                    0xC3
118 #define MR10_ZQCL                       0xAB
119 #define MR10_ZQCS                       0x56
120
121
122 /* TODO: FREQ update method is not working so shadow registers programming
123  * is just for same of completeness. This would be safer if auto
124  * trasnitions are working
125  */
126 #define FREQ_UPDATE_EMIF
127 /* EMIF Needs to be configured@19.2 MHz and shadow registers
128  * should be programmed for new OPP.
129  */
130 /* Elpida 2x2Gbit */
131 #define SDRAM_CONFIG_INIT               0x80800EB1
132 #define DDR_PHY_CTRL_1_INIT             0x849FFFF5
133 #define READ_IDLE_CTRL                  0x000501FF
134 #define PWR_MGMT_CTRL                   0x4000000f
135 #define PWR_MGMT_CTRL_OPP100            0x4000000f
136 #define ZQ_CONFIG                       0x500b3215
137
138 #define CS1_MR(mr)      ((mr) | 0x80000000)
139 struct ddr_regs{
140         u32 tim1;
141         u32 tim2;
142         u32 tim3;
143         u32 phy_ctrl_1;
144         u32 ref_ctrl;
145         u32 config_init;
146         u32 config_final;
147         u32 zq_config;
148         u8 mr1;
149         u8 mr2;
150 };
151 const struct ddr_regs ddr_regs_380_mhz = {
152         .tim1           = 0x10cb061a,
153         .tim2           = 0x20350d52,
154         .tim3           = 0x00b1431f,
155         .phy_ctrl_1     = 0x849FF408,
156         .ref_ctrl       = 0x000005ca,
157         .config_init    = 0x80000eb1,
158         .config_final   = 0x80001ab1,
159         .zq_config      = 0x500b3215,
160         .mr1            = 0x83,
161         .mr2            = 0x4
162 };
163
164 /*
165  * Unused timings - but we may need them later
166  * Keep them commented
167  */
168 #if 0
169 const struct ddr_regs ddr_regs_400_mhz = {
170         .tim1           = 0x10eb065a,
171         .tim2           = 0x20370dd2,
172         .tim3           = 0x00b1c33f,
173         .phy_ctrl_1     = 0x849FF408,
174         .ref_ctrl       = 0x00000618,
175         .config_init    = 0x80000eb1,
176         .config_final   = 0x80001ab1,
177         .zq_config      = 0x500b3215,
178         .mr1            = 0x83,
179         .mr2            = 0x4
180 };
181
182 const struct ddr_regs ddr_regs_200_mhz = {
183         .tim1           = 0x08648309,
184         .tim2           = 0x101b06ca,
185         .tim3           = 0x0048a19f,
186         .phy_ctrl_1     = 0x849FF405,
187         .ref_ctrl       = 0x0000030c,
188         .config_init    = 0x80000eb1,
189         .config_final   = 0x80000eb1,
190         .zq_config      = 0x500b3215,
191         .mr1            = 0x23,
192         .mr2            = 0x1
193 };
194 #endif
195
196 const struct ddr_regs ddr_regs_200_mhz_2cs = {
197         .tim1           = 0x08648309,
198         .tim2           = 0x101b06ca,
199         .tim3           = 0x0048a19f,
200         .phy_ctrl_1     = 0x849FF405,
201         .ref_ctrl       = 0x0000030c,
202         .config_init    = 0x80000eb9,
203         .config_final   = 0x80000eb9,
204         .zq_config      = 0xD00b3215,
205         .mr1            = 0x23,
206         .mr2            = 0x1
207 };
208
209 const struct ddr_regs ddr_regs_400_mhz_2cs = {
210         /* tRRD changed from 10ns to 12.5ns because of the tFAW requirement*/
211         .tim1           = 0x10eb0662,
212         .tim2           = 0x20370dd2,
213         .tim3           = 0x00b1c33f,
214         .phy_ctrl_1     = 0x849FF408,
215         .ref_ctrl       = 0x00000618,
216         .config_init    = 0x80000eb9,
217         .config_final   = 0x80001ab9,
218         .zq_config      = 0xD00b3215,
219         .mr1            = 0x83,
220         .mr2            = 0x4
221 };
222
223 /*******************************************************
224  * Routine: delay
225  * Description: spinning delay to use before udelay works
226  ******************************************************/
227 static inline void delay(unsigned long loops)
228 {
229         __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
230                           "bne 1b" : "=r" (loops) : "0"(loops));
231 }
232
233
234 void big_delay(unsigned int count)
235 {
236         int i;
237         for (i = 0; i < count; i++)
238                 delay(1);
239 }
240
241 void reset_phy(unsigned int base)
242 {
243         __raw_writel(__raw_readl(base + IODFT_TLGC) | (1 << 10),
244                                                              base + IODFT_TLGC);
245 }
246
247 /* this flashes the Panda LEDs forever, if called after muxconf */
248
249 void spam_leds(void)
250 {
251         unsigned int v = __raw_readl(OMAP44XX_GPIO_BASE1 + 0x134);
252
253         /* set both LED gpio to output */
254         __raw_writel((v & ~(0x03 << 7)), OMAP44XX_GPIO_BASE1 + 0x134);
255
256         v = __raw_readl(OMAP44XX_GPIO_BASE1 + 0x13c);
257         while (1) {
258                 __raw_writel((v & ~(0x03 << 7)), OMAP44XX_GPIO_BASE1 + 0x13c);
259                 big_delay(3000000);
260                 __raw_writel((v | (0x03 << 7)), OMAP44XX_GPIO_BASE1 + 0x13c);
261                 big_delay(3000000);
262         }
263 }
264
265 /* TODO: FREQ update method is not working so shadow registers programming
266  * is just for same of completeness. This would be safer if auto
267  * trasnitions are working
268  */
269 static int emif_config(unsigned int base)
270 {
271         unsigned int reg_value, rev;
272         const struct ddr_regs *ddr_regs = NULL;
273         rev = omap_revision();
274
275         if (rev == OMAP4430_ES1_0)
276                 ddr_regs = &ddr_regs_380_mhz;
277         else if (rev == OMAP4430_ES2_0)
278                 ddr_regs = &ddr_regs_200_mhz_2cs;
279         else if (rev >= OMAP4430_ES2_1)
280                 ddr_regs = &ddr_regs_400_mhz_2cs;
281
282         /*
283          * set SDRAM CONFIG register
284          * EMIF_SDRAM_CONFIG[31:29] REG_SDRAM_TYPE = 4 for LPDDR2-S4
285          * EMIF_SDRAM_CONFIG[28:27] REG_IBANK_POS = 0
286          * EMIF_SDRAM_CONFIG[13:10] REG_CL = 3
287          * EMIF_SDRAM_CONFIG[6:4] REG_IBANK = 3 - 8 banks
288          * EMIF_SDRAM_CONFIG[3] REG_EBANK = 0 - CS0
289          * EMIF_SDRAM_CONFIG[2:0] REG_PAGESIZE = 2  - 512- 9 column
290          * JDEC specs - S4-2Gb --8 banks -- R0-R13, C0-c8
291          */
292         __raw_writel(__raw_readl(base + EMIF_LPDDR2_NVM_CONFIG) & 0xbfffffff,
293                                                  base + EMIF_LPDDR2_NVM_CONFIG);
294         __raw_writel(ddr_regs->config_init, base + EMIF_SDRAM_CONFIG);
295
296         /* PHY control values */
297         __raw_writel(DDR_PHY_CTRL_1_INIT, base + EMIF_DDR_PHY_CTRL_1);
298         __raw_writel(ddr_regs->phy_ctrl_1, base + EMIF_DDR_PHY_CTRL_1_SHDW);
299
300         /*
301          * EMIF_READ_IDLE_CTRL
302          */
303         __raw_writel(READ_IDLE_CTRL, base + EMIF_READ_IDLE_CTRL);
304         __raw_writel(READ_IDLE_CTRL, base + EMIF_READ_IDLE_CTRL);
305
306         /*
307          * EMIF_SDRAM_TIM_1
308          */
309         __raw_writel(ddr_regs->tim1, base + EMIF_SDRAM_TIM_1);
310         __raw_writel(ddr_regs->tim1, base + EMIF_SDRAM_TIM_1_SHDW);
311
312         /*
313          * EMIF_SDRAM_TIM_2
314          */
315         __raw_writel(ddr_regs->tim2, base + EMIF_SDRAM_TIM_2);
316         __raw_writel(ddr_regs->tim2, base + EMIF_SDRAM_TIM_2_SHDW);
317
318         /*
319          * EMIF_SDRAM_TIM_3
320          */
321         __raw_writel(ddr_regs->tim3, base + EMIF_SDRAM_TIM_3);
322         __raw_writel(ddr_regs->tim3, base + EMIF_SDRAM_TIM_3_SHDW);
323
324         __raw_writel(ddr_regs->zq_config, base + EMIF_ZQ_CONFIG);
325
326         /*
327          * poll MR0 register (DAI bit)
328          * REG_CS[31] = 0 -- Mode register command to CS0
329          * REG_REFRESH_EN[30] = 1 -- Refresh enable after MRW
330          * REG_ADDRESS[7:0] = 00 -- Refresh enable after MRW
331          */
332
333         __raw_writel(MR0_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
334
335         do {
336                 reg_value = __raw_readl(base + EMIF_LPDDR2_MODE_REG_DATA);
337         } while (reg_value & 1);
338
339         __raw_writel(CS1_MR(MR0_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
340
341         do {
342                 reg_value = __raw_readl(base + EMIF_LPDDR2_MODE_REG_DATA);
343         } while (reg_value & 1);
344
345
346         /* set MR10 register */
347         __raw_writel(MR10_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
348         __raw_writel(MR10_ZQINIT, base + EMIF_LPDDR2_MODE_REG_DATA);
349         __raw_writel(CS1_MR(MR10_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
350         __raw_writel(MR10_ZQINIT, base + EMIF_LPDDR2_MODE_REG_DATA);
351
352         /* wait for tZQINIT=1us  */
353         delay(10);
354
355         /* set MR1 register */
356         __raw_writel(MR1_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
357         __raw_writel(ddr_regs->mr1, base + EMIF_LPDDR2_MODE_REG_DATA);
358         __raw_writel(CS1_MR(MR1_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
359         __raw_writel(ddr_regs->mr1, base + EMIF_LPDDR2_MODE_REG_DATA);
360
361         /* set MR2 register RL=6 for OPP100 */
362         __raw_writel(MR2_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
363         __raw_writel(ddr_regs->mr2, base + EMIF_LPDDR2_MODE_REG_DATA);
364         __raw_writel(CS1_MR(MR2_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
365         __raw_writel(ddr_regs->mr2, base + EMIF_LPDDR2_MODE_REG_DATA);
366
367         /* Set SDRAM CONFIG register again here with final RL-WL value */
368         __raw_writel(ddr_regs->config_final, base + EMIF_SDRAM_CONFIG);
369         __raw_writel(ddr_regs->phy_ctrl_1, base + EMIF_DDR_PHY_CTRL_1);
370
371         /*
372          * EMIF_SDRAM_REF_CTRL
373          * refresh rate = DDR_CLK / reg_refresh_rate
374          * 3.9 uS = (400MHz)    / reg_refresh_rate
375          */
376         __raw_writel(ddr_regs->ref_ctrl, base + EMIF_SDRAM_REF_CTRL);
377         __raw_writel(ddr_regs->ref_ctrl, base + EMIF_SDRAM_REF_CTRL_SHDW);
378
379         /* set MR16 register */
380         __raw_writel(MR16_ADDR | REF_EN, base + EMIF_LPDDR2_MODE_REG_CFG);
381         __raw_writel(0, base + EMIF_LPDDR2_MODE_REG_DATA);
382         __raw_writel(CS1_MR(MR16_ADDR | REF_EN),
383                                                base + EMIF_LPDDR2_MODE_REG_CFG);
384         __raw_writel(0, base + EMIF_LPDDR2_MODE_REG_DATA);
385
386         /* LPDDR2 init complete */
387
388         return 0;
389 }
390 /*****************************************
391  * Routine: ddr_init
392  * Description: Configure DDR
393  * EMIF1 -- CS0 -- DDR1 (256 MB)
394  * EMIF2 -- CS0 -- DDR2 (256 MB)
395  *****************************************/
396 static void ddr_init(void)
397 {
398         unsigned int base_addr, rev;
399         rev = omap_revision();
400
401         if (rev == OMAP4430_ES1_0) {
402                 /* Configurte the Control Module DDRIO device */
403                 __raw_writel(0x1c1c1c1c, 0x4A100638);
404                 __raw_writel(0x1c1c1c1c, 0x4A10063c);
405                 __raw_writel(0x1c1c1c1c, 0x4A100640);
406                 __raw_writel(0x1c1c1c1c, 0x4A100648);
407                 __raw_writel(0x1c1c1c1c, 0x4A10064c);
408                 __raw_writel(0x1c1c1c1c, 0x4A100650);
409                 /* LPDDR2IO set to NMOS PTV */
410                 __raw_writel(0x00ffc000, 0x4A100704);
411         } else if (rev == OMAP4430_ES2_0) {
412                 __raw_writel(0x9e9e9e9e, 0x4A100638);
413                 __raw_writel(0x9e9e9e9e, 0x4A10063c);
414                 __raw_writel(0x9e9e9e9e, 0x4A100640);
415                 __raw_writel(0x9e9e9e9e, 0x4A100648);
416                 __raw_writel(0x9e9e9e9e, 0x4A10064c);
417                 __raw_writel(0x9e9e9e9e, 0x4A100650);
418                 /* LPDDR2IO set to NMOS PTV */
419                 __raw_writel(0x00ffc000, 0x4A100704);
420         }
421
422         /*
423          * DMM Configuration
424          */
425
426         /* Both EMIFs 128 byte interleaved*/
427         if (rev == OMAP4430_ES1_0)
428                 __raw_writel(0x80540300, DMM_BASE + DMM_LISA_MAP_0);
429         else
430                 __raw_writel(0x80640300, DMM_BASE + DMM_LISA_MAP_0);
431
432         __raw_writel(0x00000000, DMM_BASE + DMM_LISA_MAP_2);
433         __raw_writel(0xFF020100, DMM_BASE + DMM_LISA_MAP_3);
434
435         /* DDR needs to be initialised @ 19.2 MHz
436          * So put core DPLL in bypass mode
437          * Configure the Core DPLL but don't lock it
438          */
439         configure_core_dpll_no_lock();
440
441         __raw_writel(0, EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
442         __raw_writel(0, EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
443
444         base_addr = EMIF1_BASE;
445         emif_config(base_addr);
446
447         /* Configure EMIF24D */
448         base_addr = EMIF2_BASE;
449         emif_config(base_addr);
450         /* Lock Core using shadow CM_SHADOW_FREQ_CONFIG1 */
451         lock_core_dpll_shadow();
452         /* TODO: SDC needs few hacks to get DDR freq update working */
453
454         /* Set DLL_OVERRIDE = 0 */
455         __raw_writel(0, CM_DLL_CTRL);
456
457         delay(200);
458
459         /* Check for DDR PHY ready for EMIF1 & EMIF2 */
460         while (!(__raw_readl(EMIF1_BASE + EMIF_STATUS) & 4) ||
461                                    !(__raw_readl(EMIF2_BASE + EMIF_STATUS) & 4))
462                 ;
463
464         /* Reprogram the DDR PYHY Control register */
465         /* PHY control values */
466
467         sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1);
468         sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1);
469
470         /* Put the Core Subsystem PD to ON State */
471
472         __raw_writel(0x80000000, EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
473         __raw_writel(0x80000000, EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
474
475         /* SYSTEM BUG:
476          * In n a specific situation, the OCP interface between the DMM and
477          * EMIF may hang.
478          * 1. A TILER port is used to perform 2D burst writes of
479          *       width 1 and height 8
480          * 2. ELLAn port is used to perform reads
481          * 3. All accesses are routed to the same EMIF controller
482          *
483          * Work around to avoid this issue REG_SYS_THRESH_MAX value should
484          * be kept higher than default 0x7. As per recommondation 0x0A will
485          * be used for better performance with REG_LL_THRESH_MAX = 0x00
486          */
487         if (rev == OMAP4430_ES1_0) {
488                 __raw_writel(0x0A0000FF, EMIF1_BASE + EMIF_L3_CONFIG);
489                 __raw_writel(0x0A0000FF, EMIF2_BASE + EMIF_L3_CONFIG);
490         }
491
492         /*
493          * DMM : DMM_LISA_MAP_0(Section_0)
494          * [31:24] SYS_ADDR             0x80
495          * [22:20] SYS_SIZE             0x7 - 2Gb
496          * [19:18] SDRC_INTLDMM         0x1 - 128 byte
497          * [17:16] SDRC_ADDRSPC         0x0
498          * [9:8] SDRC_MAP               0x3
499          * [7:0] SDRC_ADDR              0X0
500          */
501         reset_phy(EMIF1_BASE);
502         reset_phy(EMIF2_BASE);
503
504         __raw_writel(0, 0x80000000);
505         __raw_writel(0, 0x80000000);
506 }
507 /*****************************************
508  * Routine: board_init
509  * Description: Early hardware init.
510  *****************************************/
511 int board_init(void)
512 {
513         return 0;
514 }
515
516 /*************************************************************
517  * Routine: get_mem_type(void) - returns the kind of memory connected
518  * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
519  *************************************************************/
520 u32 get_mem_type(void)
521 {
522         /* no nand, so return GPMC_NONE */
523         return GPMC_NONE;
524 }
525
526 /*****************************************
527  * Routine: secure_unlock
528  * Description: Setup security registers for access
529  * (GP Device only)
530  *****************************************/
531 void secure_unlock_mem(void)
532 {
533         /* Permission values for registers -Full fledged permissions to all */
534         #define UNLOCK_1 0xFFFFFFFF
535         #define UNLOCK_2 0x00000000
536         #define UNLOCK_3 0x0000FFFF
537
538         /* Protection Module Register Target APE (PM_RT)*/
539         __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
540         __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
541         __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
542         __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
543
544         __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
545         __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
546         __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
547
548         __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
549         __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
550         __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
551         __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
552
553         /* IVA Changes */
554         __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
555         __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
556         __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
557
558         __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
559 }
560
561 /**********************************************************
562  * Routine: try_unlock_sram()
563  * Description: If chip is GP/EMU(special) type, unlock the SRAM for
564  *  general use.
565  ***********************************************************/
566 void try_unlock_memory(void)
567 {
568         /* if GP device unlock device SRAM for general use */
569         /* secure code breaks for Secure/Emulation device - HS/E/T*/
570 }
571
572
573 #if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000)
574 static int scale_vcores(void)
575 {
576         unsigned int rev = omap_revision();
577         /* For VC bypass only VCOREx_CGF_FORCE  is necessary and
578          * VCOREx_CFG_VOLTAGE  changes can be discarded
579          */
580         /* PRM_VC_CFG_I2C_MODE */
581         __raw_writel(0, 0x4A307BA8);
582
583         /* PRM_VC_CFG_I2C_CLK */
584         __raw_writel(0x6026, 0x4A307BAC);
585
586         /* set VCORE1 force VSEL */
587         /* PRM_VC_VAL_BYPASS) */
588         if (rev == OMAP4430_ES1_0)
589                 __raw_writel(0x3B5512, 0x4A307BA0);
590         else
591                 __raw_writel(0x3A5512, 0x4A307BA0);
592
593         __raw_writel(__raw_readl(0x4A307BA0) | 0x1000000, 0x4A307BA0);
594         while (__raw_readl(0x4A307BA0) & 0x1000000)
595                 ;
596
597         /* PRM_IRQSTATUS_MPU */
598         __raw_writel(__raw_readl(0x4A306010), 0x4A306010);
599
600         /* FIXME: set VCORE2 force VSEL, Check the reset value */
601         /* PRM_VC_VAL_BYPASS) */
602         if (rev == OMAP4430_ES1_0)
603                 __raw_writel(0x315B12, 0x4A307BA0);
604         else
605                 __raw_writel(0x295B12, 0x4A307BA0);
606
607         __raw_writel(__raw_readl(0x4A307BA0) | 0x1000000, 0x4A307BA0);
608         while (__raw_readl(0x4A307BA0) & 0x1000000)
609                 ;
610
611         /* PRM_IRQSTATUS_MPU */
612         __raw_writel(__raw_readl(0x4A306010), 0x4A306010);
613
614         /*/set VCORE3 force VSEL */
615         /* PRM_VC_VAL_BYPASS */
616         switch (rev) {
617         case OMAP4430_ES1_0:
618                 __raw_writel(0x316112, 0x4A307BA0);
619                 break;
620         case OMAP4430_ES2_0:
621                 __raw_writel(0x296112, 0x4A307BA0);
622                 break;
623         case OMAP4430_ES2_1:
624                 __raw_writel(0x2A6112, 0x4A307BA0);
625                 break;
626         }
627         __raw_writel(__raw_readl(0x4A307BA0) | 0x1000000, 0x4A307BA0);
628         while (__raw_readl(0x4A307BA0) & 0x1000000)
629                 ;
630
631         /* PRM_IRQSTATUS_MPU */
632         __raw_writel(__raw_readl(0x4A306010), 0x4A306010);
633
634         return 0;
635 }
636 #endif
637
638 /**********************************************************
639  * Routine: s_init
640  * Description: Does early system init of muxing and clocks.
641  * - Called path is with SRAM stack.
642  **********************************************************/
643
644 void s_init(void)
645 {
646         unsigned int rev = omap_revision();
647
648         set_muxconf_regs();
649         delay(100);
650
651         /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */
652         /* Currently SMI in Kernel on ES2 devices seems to have an isse
653          * Once that is resolved, we can postpone this config to kernel
654          */
655         /* setup_auxcr(get_device_type(), external_boot); */
656
657         ddr_init();
658
659 /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
660 #if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000)
661         scale_vcores();
662 #endif
663         prcm_init();
664
665         if (rev != OMAP4430_ES1_0) {
666                 if (__raw_readl(0x4805D138) & (1<<22)) {
667                         /* enable software ioreq */
668                         sr32(0x4A30a31C, 8, 1, 0x1);
669                         /* set for sys_clk (38.4MHz) */
670                         sr32(0x4A30a31C, 1, 2, 0x0);
671                         /* set divisor to 2 */
672                         sr32(0x4A30a31C, 16, 4, 0x1);
673                         /* set the clock source to active */
674                         sr32(0x4A30a110, 0, 1, 0x1);
675                         /* enable clocks */
676                         sr32(0x4A30a110, 2, 2, 0x3);
677                 } else {
678                         /* enable software ioreq */
679                         sr32(0x4A30a314, 8, 1, 0x1);
680                         /* set for PER_DPLL */
681                         sr32(0x4A30a314, 1, 2, 0x2);
682                         /* set divisor to 16 */
683                         sr32(0x4A30a314, 16, 4, 0xf);
684                         /* set the clock source to active */
685                         sr32(0x4A30a110, 0, 1, 0x1);
686                         /* enable clocks */
687                         sr32(0x4A30a110, 2, 2, 0x3);
688                 }
689         }
690 }
691
692 /*******************************************************
693  * Routine: misc_init_r
694  * Description: Init ethernet (done here so udelay works)
695  ********************************************************/
696 int misc_init_r(void)
697 {
698         return 0;
699 }
700
701 /******************************************************
702  * Routine: wait_for_command_complete
703  * Description: Wait for posting to finish on watchdog
704  ******************************************************/
705 void wait_for_command_complete(unsigned int wd_base)
706 {
707         int pending = 1;
708         do {
709                 pending = __raw_readl(wd_base + WWPS);
710         } while (pending);
711 }
712
713 /*******************************************************************
714  * Routine:ether_init
715  * Description: take the Ethernet controller out of reset and wait
716  *                 for the EEPROM load to complete.
717  ******************************************************************/
718
719 /**********************************************
720  * Routine: dram_init
721  * Description: sets uboots idea of sdram size
722  **********************************************/
723 int dram_init(void)
724 {
725         return 0;
726 }
727
728 #define OMAP44XX_WKUP_CTRL_BASE 0x4A31E000
729
730 #if 1
731 #define M0_SAFE M0
732 #define M1_SAFE M1
733 #define M2_SAFE M2
734 #define M4_SAFE M4
735 #define M7_SAFE M7
736 #define M3_SAFE M3
737 #define M5_SAFE M5
738 #define M6_SAFE M6
739 #else
740 #define M0_SAFE M7
741 #define M1_SAFE M7
742 #define M2_SAFE M7
743 #define M4_SAFE M7
744 #define M7_SAFE M7
745 #define M3_SAFE M7
746 #define M5_SAFE M7
747 #define M6_SAFE M7
748 #endif
749 #define         MV(OFFSET, VALUE) \
750                         __raw_writew((VALUE), OMAP44XX_CTRL_BASE + (OFFSET));
751 #define         MV1(OFFSET, VALUE) \
752                       __raw_writew((VALUE), OMAP44XX_WKUP_CTRL_BASE + (OFFSET));
753
754 #define         CP(x)   (CONTROL_PADCONF_##x)
755 #define         WK(x)   (CONTROL_WKUP_##x)
756 /*
757  * IEN  - Input Enable
758  * IDIS - Input Disable
759  * PTD  - Pull type Down
760  * PTU  - Pull type Up
761  * DIS  - Pull type selection is inactive
762  * EN   - Pull type selection is active
763  * M0   - Mode 0
764  * The commented string gives the final mux configuration for that pin
765  */
766
767 struct omap4panda_mux {
768         unsigned int ads;
769         unsigned int value;
770 };
771
772 static const struct omap4panda_mux omap4panda_mux[] = {
773         { OMAP44XX_CTRL_BASE + CP(GPMC_AD0),
774                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_dat0 */ },
775         { OMAP44XX_CTRL_BASE + CP(GPMC_AD1),
776                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_dat1 */ },
777         { OMAP44XX_CTRL_BASE + CP(GPMC_AD2),
778                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_dat2 */ },
779         { OMAP44XX_CTRL_BASE + CP(GPMC_AD3),
780                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_dat3 */ },
781         { OMAP44XX_CTRL_BASE + CP(GPMC_AD4),
782                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_dat4 */ },
783         { OMAP44XX_CTRL_BASE + CP(GPMC_AD5),
784                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_dat5 */ },
785         { OMAP44XX_CTRL_BASE + CP(GPMC_AD6),
786                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_dat6 */ },
787         { OMAP44XX_CTRL_BASE + CP(GPMC_AD7),
788                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_dat7 */ },
789         { OMAP44XX_CTRL_BASE + CP(GPMC_AD8),
790                      PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3  /* gpio_32 */ },
791         { OMAP44XX_CTRL_BASE + CP(GPMC_AD9),
792                                                 PTU | IEN | M3  /* gpio_33 */ },
793         { OMAP44XX_CTRL_BASE + CP(GPMC_AD10),
794                                                 PTU | IEN | M3  /* gpio_34 */ },
795         { OMAP44XX_CTRL_BASE + CP(GPMC_AD11),
796                                                 PTU | IEN | M3  /* gpio_35 */ },
797         { OMAP44XX_CTRL_BASE + CP(GPMC_AD12),
798                                                 PTU | IEN | M3  /* gpio_36 */ },
799         { OMAP44XX_CTRL_BASE + CP(GPMC_AD13),
800                       PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3  /* gpio_37 */ },
801         { OMAP44XX_CTRL_BASE + CP(GPMC_AD14),
802                       PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3  /* gpio_38 */ },
803         { OMAP44XX_CTRL_BASE + CP(GPMC_AD15),
804                       PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3  /* gpio_39 */ },
805         { OMAP44XX_CTRL_BASE + CP(GPMC_A16), M3  /* gpio_40 */ },
806         { OMAP44XX_CTRL_BASE + CP(GPMC_A17), PTD | M3  /* gpio_41 */ },
807         { OMAP44XX_CTRL_BASE + CP(GPMC_A18),
808                     PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_row6 */ },
809         { OMAP44XX_CTRL_BASE + CP(GPMC_A19),
810                     PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_row7 */ },
811         { OMAP44XX_CTRL_BASE + CP(GPMC_A20),
812                                                       IEN | M3  /* gpio_44 */ },
813         { OMAP44XX_CTRL_BASE + CP(GPMC_A21), M3  /* gpio_45 */ },
814         { OMAP44XX_CTRL_BASE + CP(GPMC_A22), M3  /* gpio_46 */ },
815         { OMAP44XX_CTRL_BASE + CP(GPMC_A23),
816                                 OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_col7 */ },
817         { OMAP44XX_CTRL_BASE + CP(GPMC_A24), PTD | M3  /* gpio_48 */ },
818         { OMAP44XX_CTRL_BASE + CP(GPMC_A25), PTD | M3  /* gpio_49 */ },
819         { OMAP44XX_CTRL_BASE + CP(GPMC_NCS0), M3  /* gpio_50 */ },
820         { OMAP44XX_CTRL_BASE + CP(GPMC_NCS1), IEN | M3  /* gpio_51 */ },
821         { OMAP44XX_CTRL_BASE + CP(GPMC_NCS2), IEN | M3  /* gpio_52 */ },
822         { OMAP44XX_CTRL_BASE + CP(GPMC_NCS3), IEN | M3  /* gpio_53 */ },
823         { OMAP44XX_CTRL_BASE + CP(GPMC_NWP), M3  /* gpio_54 */ },
824         { OMAP44XX_CTRL_BASE + CP(GPMC_CLK), PTD | M3  /* gpio_55 */ },
825         { OMAP44XX_CTRL_BASE + CP(GPMC_NADV_ALE), M3  /* gpio_56 */ },
826         { OMAP44XX_CTRL_BASE + CP(GPMC_NOE),
827                       PTU | IEN | OFF_EN | OFF_OUT_PTD | M1  /* sdmmc2_clk */ },
828         { OMAP44XX_CTRL_BASE + CP(GPMC_NWE),
829                   PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* sdmmc2_cmd */ },
830         { OMAP44XX_CTRL_BASE + CP(GPMC_NBE0_CLE), M3  /* gpio_59 */ },
831         { OMAP44XX_CTRL_BASE + CP(GPMC_NBE1), PTD | M3  /* gpio_60 */ },
832         { OMAP44XX_CTRL_BASE + CP(GPMC_WAIT0), PTU | IEN | M3  /* gpio_61 */ },
833         { OMAP44XX_CTRL_BASE + CP(GPMC_WAIT1),
834                        PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3 /* gpio_62 */ },
835         { OMAP44XX_CTRL_BASE + CP(C2C_DATA11), PTD | M3  /* gpio_100 */ },
836         { OMAP44XX_CTRL_BASE + CP(C2C_DATA12), PTD | IEN | M3  /* gpio_101 */ },
837         { OMAP44XX_CTRL_BASE + CP(C2C_DATA13), PTD | M3  /* gpio_102 */ },
838         { OMAP44XX_CTRL_BASE + CP(C2C_DATA14), M1  /* dsi2_te0 */ },
839         { OMAP44XX_CTRL_BASE + CP(C2C_DATA15), PTD | M3  /* gpio_104 */ },
840         { OMAP44XX_CTRL_BASE + CP(HDMI_HPD), M0  /* hdmi_hpd */ },
841         { OMAP44XX_CTRL_BASE + CP(HDMI_CEC), M0  /* hdmi_cec */ },
842         { OMAP44XX_CTRL_BASE + CP(HDMI_DDC_SCL), PTU | M0  /* hdmi_ddc_scl */ },
843         { OMAP44XX_CTRL_BASE + CP(HDMI_DDC_SDA),
844                                            PTU | IEN | M0  /* hdmi_ddc_sda */ },
845         { OMAP44XX_CTRL_BASE + CP(CSI21_DX0), IEN | M0  /* csi21_dx0 */ },
846         { OMAP44XX_CTRL_BASE + CP(CSI21_DY0), IEN | M0  /* csi21_dy0 */ },
847         { OMAP44XX_CTRL_BASE + CP(CSI21_DX1), IEN | M0  /* csi21_dx1 */ },
848         { OMAP44XX_CTRL_BASE + CP(CSI21_DY1), IEN | M0  /* csi21_dy1 */ },
849         { OMAP44XX_CTRL_BASE + CP(CSI21_DX2), IEN | M0  /* csi21_dx2 */ },
850         { OMAP44XX_CTRL_BASE + CP(CSI21_DY2), IEN | M0  /* csi21_dy2 */ },
851         { OMAP44XX_CTRL_BASE + CP(CSI21_DX3), PTD | M7  /* csi21_dx3 */ },
852         { OMAP44XX_CTRL_BASE + CP(CSI21_DY3), PTD | M7  /* csi21_dy3 */ },
853         { OMAP44XX_CTRL_BASE + CP(CSI21_DX4),
854                          PTD | OFF_EN | OFF_PD | OFF_IN | M7  /* csi21_dx4 */ },
855         { OMAP44XX_CTRL_BASE + CP(CSI21_DY4),
856                          PTD | OFF_EN | OFF_PD | OFF_IN | M7  /* csi21_dy4 */ },
857         { OMAP44XX_CTRL_BASE + CP(CSI22_DX0), IEN | M0  /* csi22_dx0 */ },
858         { OMAP44XX_CTRL_BASE + CP(CSI22_DY0), IEN | M0  /* csi22_dy0 */ },
859         { OMAP44XX_CTRL_BASE + CP(CSI22_DX1), IEN | M0  /* csi22_dx1 */ },
860         { OMAP44XX_CTRL_BASE + CP(CSI22_DY1), IEN | M0  /* csi22_dy1 */ },
861         { OMAP44XX_CTRL_BASE + CP(CAM_SHUTTER),
862                         OFF_EN | OFF_PD | OFF_OUT_PTD | M0  /* cam_shutter */ },
863         { OMAP44XX_CTRL_BASE + CP(CAM_STROBE),
864                          OFF_EN | OFF_PD | OFF_OUT_PTD | M0  /* cam_strobe */ },
865         { OMAP44XX_CTRL_BASE + CP(CAM_GLOBALRESET),
866                       PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3  /* gpio_83 */ },
867         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_CLK),
868            PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_clk */ },
869         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_STP),
870                            OFF_EN | OFF_OUT_PTD | M4  /* usbb1_ulpiphy_stp */ },
871         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DIR),
872                  IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_dir */ },
873         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_NXT),
874                  IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_nxt */ },
875         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT0),
876                 IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_dat0 */ },
877         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT1),
878                 IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_dat1 */ },
879         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT2),
880                 IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_dat2 */ },
881         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT3),
882                 IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_dat3 */ },
883         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT4),
884                 IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_dat4 */ },
885         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT5),
886                 IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_dat5 */ },
887         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT6),
888                 IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_dat6 */ },
889         { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT7),
890                 IEN | OFF_EN | OFF_PD | OFF_IN | M4  /* usbb1_ulpiphy_dat7 */ },
891         { OMAP44XX_CTRL_BASE + CP(USBB1_HSIC_DATA),
892                    IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* usbb1_hsic_data */ },
893         { OMAP44XX_CTRL_BASE + CP(USBB1_HSIC_STROBE),
894                  IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* usbb1_hsic_strobe */ },
895         { OMAP44XX_CTRL_BASE + CP(USBC1_ICUSB_DP),
896                                                IEN | M0  /* usbc1_icusb_dp */ },
897         { OMAP44XX_CTRL_BASE + CP(USBC1_ICUSB_DM),
898                                                IEN | M0  /* usbc1_icusb_dm */ },
899         { OMAP44XX_CTRL_BASE + CP(SDMMC1_CLK),
900                             PTU | OFF_EN | OFF_OUT_PTD | M0  /* sdmmc1_clk */ },
901         { OMAP44XX_CTRL_BASE + CP(SDMMC1_CMD),
902                   PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc1_cmd */ },
903         { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT0),
904                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc1_dat0 */ },
905         { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT1),
906                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc1_dat1 */ },
907         { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT2),
908                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc1_dat2 */ },
909         { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT3),
910                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc1_dat3 */ },
911         { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT4),
912                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc1_dat4 */ },
913         { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT5),
914                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc1_dat5 */ },
915         { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT6),
916                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc1_dat6 */ },
917         { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT7),
918                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc1_dat7 */ },
919         { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP2_CLKX),
920                    IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* abe_mcbsp2_clkx */ },
921         { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP2_DR),
922                          IEN | OFF_EN | OFF_OUT_PTD | M0  /* abe_mcbsp2_dr */ },
923         { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP2_DX),
924                                OFF_EN | OFF_OUT_PTD | M0  /* abe_mcbsp2_dx */ },
925         { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP2_FSX),
926                     IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* abe_mcbsp2_fsx */ },
927         { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP1_CLKX),
928                                            IEN | M1  /* abe_slimbus1_clock */ },
929         { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP1_DR),
930                                             IEN | M1  /* abe_slimbus1_data */ },
931         { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP1_DX),
932                                OFF_EN | OFF_OUT_PTD | M0  /* abe_mcbsp1_dx */ },
933         { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP1_FSX),
934                     IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* abe_mcbsp1_fsx */ },
935         { OMAP44XX_CTRL_BASE + CP(ABE_PDM_UL_DATA),
936              PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* abe_pdm_ul_data */ },
937         { OMAP44XX_CTRL_BASE + CP(ABE_PDM_DL_DATA),
938              PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* abe_pdm_dl_data */ },
939         { OMAP44XX_CTRL_BASE + CP(ABE_PDM_FRAME),
940                PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* abe_pdm_frame */ },
941         { OMAP44XX_CTRL_BASE + CP(ABE_PDM_LB_CLK),
942               PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* abe_pdm_lb_clk */ },
943         { OMAP44XX_CTRL_BASE + CP(ABE_CLKS),
944                     PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* abe_clks */ },
945         { OMAP44XX_CTRL_BASE + CP(ABE_DMIC_CLK1), M0  /* abe_dmic_clk1 */ },
946         { OMAP44XX_CTRL_BASE + CP(ABE_DMIC_DIN1),
947                                                 IEN | M0  /* abe_dmic_din1 */ },
948         { OMAP44XX_CTRL_BASE + CP(ABE_DMIC_DIN2),
949                                                 IEN | M0  /* abe_dmic_din2 */ },
950         { OMAP44XX_CTRL_BASE + CP(ABE_DMIC_DIN3),
951                                                 IEN | M0  /* abe_dmic_din3 */ },
952         { OMAP44XX_CTRL_BASE + CP(UART2_CTS), PTU | IEN | M0  /* uart2_cts */ },
953         { OMAP44XX_CTRL_BASE + CP(UART2_RTS), M0  /* uart2_rts */ },
954         { OMAP44XX_CTRL_BASE + CP(UART2_RX), PTU | IEN | M0  /* uart2_rx */ },
955         { OMAP44XX_CTRL_BASE + CP(UART2_TX), M0  /* uart2_tx */ },
956         { OMAP44XX_CTRL_BASE + CP(HDQ_SIO), M3  /* gpio_127 */ },
957         { OMAP44XX_CTRL_BASE + CP(I2C1_SCL), PTU | IEN | M0  /* i2c1_scl */ },
958         { OMAP44XX_CTRL_BASE + CP(I2C1_SDA), PTU | IEN | M0  /* i2c1_sda */ },
959         { OMAP44XX_CTRL_BASE + CP(I2C2_SCL), PTU | IEN | M0  /* i2c2_scl */ },
960         { OMAP44XX_CTRL_BASE + CP(I2C2_SDA), PTU | IEN | M0  /* i2c2_sda */ },
961         { OMAP44XX_CTRL_BASE + CP(I2C3_SCL), PTU | IEN | M0  /* i2c3_scl */ },
962         { OMAP44XX_CTRL_BASE + CP(I2C3_SDA), PTU | IEN | M0  /* i2c3_sda */ },
963         { OMAP44XX_CTRL_BASE + CP(I2C4_SCL), PTU | IEN | M0  /* i2c4_scl */ },
964         { OMAP44XX_CTRL_BASE + CP(I2C4_SDA), PTU | IEN | M0  /* i2c4_sda */ },
965         { OMAP44XX_CTRL_BASE + CP(MCSPI1_CLK),
966                         IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* mcspi1_clk */ },
967         { OMAP44XX_CTRL_BASE + CP(MCSPI1_SOMI),
968                        IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* mcspi1_somi */ },
969         { OMAP44XX_CTRL_BASE + CP(MCSPI1_SIMO),
970                        IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* mcspi1_simo */ },
971         { OMAP44XX_CTRL_BASE + CP(MCSPI1_CS0),
972                   PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* mcspi1_cs0 */ },
973         { OMAP44XX_CTRL_BASE + CP(MCSPI1_CS1),
974                   PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3  /* mcspi1_cs1 */ },
975         { OMAP44XX_CTRL_BASE + CP(MCSPI1_CS2),
976                               PTU | OFF_EN | OFF_OUT_PTU | M3  /* gpio_139 */ },
977         { OMAP44XX_CTRL_BASE + CP(MCSPI1_CS3), PTU | IEN | M3  /* gpio_140 */ },
978         { OMAP44XX_CTRL_BASE + CP(UART3_CTS_RCTX),
979                                                PTU | IEN | M0  /* uart3_tx */ },
980         { OMAP44XX_CTRL_BASE + CP(UART3_RTS_SD), M0  /* uart3_rts_sd */ },
981         { OMAP44XX_CTRL_BASE + CP(UART3_RX_IRRX), IEN | M0  /* uart3_rx */ },
982         { OMAP44XX_CTRL_BASE + CP(UART3_TX_IRTX), M0  /* uart3_tx */ },
983         { OMAP44XX_CTRL_BASE + CP(SDMMC5_CLK),
984                       PTU | IEN | OFF_EN | OFF_OUT_PTD | M0  /* sdmmc5_clk */ },
985         { OMAP44XX_CTRL_BASE + CP(SDMMC5_CMD),
986                   PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc5_cmd */ },
987         { OMAP44XX_CTRL_BASE + CP(SDMMC5_DAT0),
988                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc5_dat0 */ },
989         { OMAP44XX_CTRL_BASE + CP(SDMMC5_DAT1),
990                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc5_dat1 */ },
991         { OMAP44XX_CTRL_BASE + CP(SDMMC5_DAT2),
992                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc5_dat2 */ },
993         { OMAP44XX_CTRL_BASE + CP(SDMMC5_DAT3),
994                  PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* sdmmc5_dat3 */ },
995         { OMAP44XX_CTRL_BASE + CP(MCSPI4_CLK),
996                         IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* mcspi4_clk */ },
997         { OMAP44XX_CTRL_BASE + CP(MCSPI4_SIMO),
998                        IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* mcspi4_simo */ },
999         { OMAP44XX_CTRL_BASE + CP(MCSPI4_SOMI),
1000                        IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* mcspi4_somi */ },
1001         { OMAP44XX_CTRL_BASE + CP(MCSPI4_CS0),
1002                   PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* mcspi4_cs0 */ },
1003         { OMAP44XX_CTRL_BASE + CP(UART4_RX), IEN | M0  /* uart4_rx */ },
1004         { OMAP44XX_CTRL_BASE + CP(UART4_TX), M0  /* uart4_tx */ },
1005         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_CLK),
1006                                                      IEN | M3  /* gpio_157 */ },
1007         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_STP),
1008                                                 IEN | M5  /* dispc2_data23 */ },
1009         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DIR),
1010                                                 IEN | M5  /* dispc2_data22 */ },
1011         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_NXT),
1012                                                 IEN | M5  /* dispc2_data21 */ },
1013         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT0),
1014                                                 IEN | M5  /* dispc2_data20 */ },
1015         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT1),
1016                                                 IEN | M5  /* dispc2_data19 */ },
1017         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT2),
1018                                                 IEN | M5  /* dispc2_data18 */ },
1019         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT3),
1020                                                 IEN | M5  /* dispc2_data15 */ },
1021         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT4),
1022                                                 IEN | M5  /* dispc2_data14 */ },
1023         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT5),
1024                                                 IEN | M5  /* dispc2_data13 */ },
1025         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT6),
1026                                                 IEN | M5  /* dispc2_data12 */ },
1027         { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT7),
1028                                                 IEN | M5  /* dispc2_data11 */ },
1029         { OMAP44XX_CTRL_BASE + CP(USBB2_HSIC_DATA),
1030                               PTD | OFF_EN | OFF_OUT_PTU | M3  /* gpio_169 */ },
1031         { OMAP44XX_CTRL_BASE + CP(USBB2_HSIC_STROBE),
1032                               PTD | OFF_EN | OFF_OUT_PTU | M3  /* gpio_170 */ },
1033         { OMAP44XX_CTRL_BASE + CP(UNIPRO_TX0), PTD | IEN | M3  /* gpio_171 */ },
1034         { OMAP44XX_CTRL_BASE + CP(UNIPRO_TY0),
1035                                 OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_col1 */ },
1036         { OMAP44XX_CTRL_BASE + CP(UNIPRO_TX1),
1037                                 OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_col2 */ },
1038         { OMAP44XX_CTRL_BASE + CP(UNIPRO_TY1),
1039                                 OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_col3 */ },
1040         { OMAP44XX_CTRL_BASE + CP(UNIPRO_TX2), PTU | IEN | M3  /* gpio_0 */ },
1041         { OMAP44XX_CTRL_BASE + CP(UNIPRO_TY2), PTU | IEN | M3  /* gpio_1 */ },
1042         { OMAP44XX_CTRL_BASE + CP(UNIPRO_RX0),
1043                     PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_row0 */ },
1044         { OMAP44XX_CTRL_BASE + CP(UNIPRO_RY0),
1045                     PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_row1 */ },
1046         { OMAP44XX_CTRL_BASE + CP(UNIPRO_RX1),
1047                     PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_row2 */ },
1048         { OMAP44XX_CTRL_BASE + CP(UNIPRO_RY1),
1049                     PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_row3 */ },
1050         { OMAP44XX_CTRL_BASE + CP(UNIPRO_RX2),
1051                     PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_row4 */ },
1052         { OMAP44XX_CTRL_BASE + CP(UNIPRO_RY2),
1053                     PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1  /* kpd_row5 */ },
1054         { OMAP44XX_CTRL_BASE + CP(USBA0_OTG_CE),
1055                  PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0  /* usba0_otg_ce */ },
1056         { OMAP44XX_CTRL_BASE + CP(USBA0_OTG_DP),
1057                       IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* usba0_otg_dp */ },
1058         { OMAP44XX_CTRL_BASE + CP(USBA0_OTG_DM),
1059                       IEN | OFF_EN | OFF_PD | OFF_IN | M0  /* usba0_otg_dm */ },
1060         { OMAP44XX_CTRL_BASE + CP(FREF_CLK1_OUT), M0  /* fref_clk1_out */ },
1061         { OMAP44XX_CTRL_BASE + CP(FREF_CLK2_OUT),
1062                                                PTD | IEN | M3  /* gpio_182 */ },
1063         { OMAP44XX_CTRL_BASE + CP(SYS_NIRQ1), PTU | IEN | M0  /* sys_nirq1 */ },
1064         { OMAP44XX_CTRL_BASE + CP(SYS_NIRQ2), PTU | IEN | M0  /* sys_nirq2 */ },
1065         { OMAP44XX_CTRL_BASE + CP(SYS_BOOT0), PTU | IEN | M3  /* gpio_184 */ },
1066         { OMAP44XX_CTRL_BASE + CP(SYS_BOOT1), M3  /* gpio_185 */ },
1067         { OMAP44XX_CTRL_BASE + CP(SYS_BOOT2), PTD | IEN | M3  /* gpio_186 */ },
1068         { OMAP44XX_CTRL_BASE + CP(SYS_BOOT3), M3  /* gpio_187 */ },
1069         { OMAP44XX_CTRL_BASE + CP(SYS_BOOT4), M3  /* gpio_188 */ },
1070         { OMAP44XX_CTRL_BASE + CP(SYS_BOOT5), PTD | IEN | M3  /* gpio_189 */ },
1071         { OMAP44XX_CTRL_BASE + CP(DPM_EMU0), IEN | M0  /* dpm_emu0 */ },
1072         { OMAP44XX_CTRL_BASE + CP(DPM_EMU1), IEN | M0  /* dpm_emu1 */ },
1073         { OMAP44XX_CTRL_BASE + CP(DPM_EMU2), IEN | M0  /* dpm_emu2 */ },
1074         { OMAP44XX_CTRL_BASE + CP(DPM_EMU3), IEN | M5  /* dispc2_data10 */ },
1075         { OMAP44XX_CTRL_BASE + CP(DPM_EMU4), IEN | M5  /* dispc2_data9 */ },
1076         { OMAP44XX_CTRL_BASE + CP(DPM_EMU5), IEN | M5  /* dispc2_data16 */ },
1077         { OMAP44XX_CTRL_BASE + CP(DPM_EMU6), IEN | M5  /* dispc2_data17 */ },
1078         { OMAP44XX_CTRL_BASE + CP(DPM_EMU7), IEN | M5  /* dispc2_hsync */ },
1079         { OMAP44XX_CTRL_BASE + CP(DPM_EMU8), IEN | M5  /* dispc2_pclk */ },
1080         { OMAP44XX_CTRL_BASE + CP(DPM_EMU9), IEN | M5  /* dispc2_vsync */ },
1081         { OMAP44XX_CTRL_BASE + CP(DPM_EMU10), IEN | M5  /* dispc2_de */ },
1082         { OMAP44XX_CTRL_BASE + CP(DPM_EMU11), IEN | M5  /* dispc2_data8 */ },
1083         { OMAP44XX_CTRL_BASE + CP(DPM_EMU12), IEN | M5  /* dispc2_data7 */ },
1084         { OMAP44XX_CTRL_BASE + CP(DPM_EMU13), IEN | M5  /* dispc2_data6 */ },
1085         { OMAP44XX_CTRL_BASE + CP(DPM_EMU14), IEN | M5  /* dispc2_data5 */ },
1086         { OMAP44XX_CTRL_BASE + CP(DPM_EMU15), IEN | M5  /* dispc2_data4 */ },
1087         { OMAP44XX_CTRL_BASE + CP(DPM_EMU16), M3  /* gpio_27 */ },
1088         { OMAP44XX_CTRL_BASE + CP(DPM_EMU17), IEN | M5  /* dispc2_data2 */ },
1089         { OMAP44XX_CTRL_BASE + CP(DPM_EMU18), IEN | M5  /* dispc2_data1 */ },
1090         { OMAP44XX_CTRL_BASE + CP(DPM_EMU19), IEN | M5  /* dispc2_data0 */ },
1091         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_SIM_IO), IEN | M0  /* sim_io */ },
1092         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_SIM_CLK), M0  /* sim_clk */ },
1093         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_SIM_RESET), M0  /* sim_reset */ },
1094         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_SIM_CD),
1095                                                  PTU | IEN | M0  /* sim_cd */ },
1096         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_SIM_PWRCTRL),
1097                                                         M0  /* sim_pwrctrl */ },
1098         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_SR_SCL),
1099                                                  PTU | IEN | M0  /* sr_scl */ },
1100         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_SR_SDA),
1101                                                  PTU | IEN | M0  /* sr_sda */ },
1102         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_FREF_XTAL_IN), M0  /* # */ },
1103         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_FREF_SLICER_IN),
1104                                                      M0  /* fref_slicer_in */ },
1105         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_FREF_CLK_IOREQ),
1106                                                      M0  /* fref_clk_ioreq */ },
1107         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_FREF_CLK0_OUT),
1108                                                     M2  /* sys_drm_msecure */ },
1109         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_FREF_CLK3_REQ),
1110                                                       PTU | IEN | M0  /* # */ },
1111         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_FREF_CLK3_OUT),
1112                                                       M0  /* fref_clk3_out */ },
1113         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_FREF_CLK4_REQ),
1114                                                       PTU | IEN | M0  /* # */ },
1115         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_FREF_CLK4_OUT), M0  /* # */ },
1116         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_SYS_32K), IEN | M0  /* sys_32k */ },
1117         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_SYS_NRESPWRON),
1118                                                       M0  /* sys_nrespwron */ },
1119         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_SYS_NRESWARM),
1120                                                        M0  /* sys_nreswarm */ },
1121         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_SYS_PWR_REQ),
1122                                                   PTU | M0  /* sys_pwr_req */ },
1123         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_SYS_PWRON_RESET),
1124                                                           M3  /* gpio_wk29 */ },
1125         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_SYS_BOOT6),
1126                                                      IEN | M3  /* gpio_wk9 */ },
1127         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_SYS_BOOT7),
1128                                                     IEN | M3  /* gpio_wk10 */ },
1129         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_FREF_CLK3_REQ),
1130                                                            M3 /* gpio_wk30 */ },
1131         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_FREF_CLK4_REQ), M3 /* gpio_wk7 */ },
1132         { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_FREF_CLK4_OUT), M3 /* gpio_wk8 */ },
1133 };
1134
1135 /**********************************************************
1136  * Routine: set_muxconf_regs
1137  * Description: Setting up the configuration Mux registers
1138  *              specific to the hardware. Many pins need
1139  *              to be moved from protect to primary mode.
1140  *********************************************************/
1141 void set_muxconf_regs(void)
1142 {
1143         int n;
1144
1145         for (n = 0; n < sizeof omap4panda_mux / sizeof omap4panda_mux[0]; n++)
1146                 __raw_writew(omap4panda_mux[n].value, omap4panda_mux[n].ads);
1147 }
1148
1149 /******************************************************************************
1150  * Routine: update_mux()
1151  * Description:Update balls which are different between boards.  All should be
1152  *             updated to match functionality.  However, I'm only updating ones
1153  *             which I'll be using for now.  When power comes into play they
1154  *             all need updating.
1155  *****************************************************************************/
1156 void update_mux(u32 btype, u32 mtype)
1157 {
1158         /* REVISIT  */
1159 }
1160
1161 /* optionally do something like blinking LED */
1162 void board_hang(void)
1163 {
1164         while (1)
1165                 ;
1166 }
1167
1168 int nand_init(void)
1169 {
1170         return 0;
1171 }