OMAP4: Select DPLL PER Clock as source for SGX FCLK
authorRajeev Kulkarni <rajeevk@ti.com>
Tue, 26 Oct 2010 12:34:43 +0000 (07:34 -0500)
committerRicardo Salveti de Araujo <ricardo.salveti@canonical.com>
Tue, 21 Dec 2010 13:56:35 +0000 (11:56 -0200)
commitfff093ab92c5dadd646130c38097dc167d2d0e1e
treeba59e3c179e9fe813d198ae5e1c15ce75814462c
parent94fee465a6d63b6f0551037fe14cec4410bb9af2
OMAP4: Select DPLL PER Clock as source for SGX FCLK

The correct frequncy for SGX is 307.2 Mhz.. If DPLL_PER
is set 1536 Mhz, There is no need to change dividers, just
parent clock need to change. And DPLL PER is set at 1536.

Signed-off-by: Rajeev Kulkarni <rajeevk@ti.com>
Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
board/omap4430panda/clock.c