lib/printf.c: making serial_printf return vsprintf ret value
[x-loader:lihh89s-x-loader.git] / board / omap2420h4 / omap2420h4.c
1 /*
2  * Copyright (C) 2005 Texas Instruments.
3  * Jian Zhang <jzhang@ti.com>
4  * Richard Woodruff <r-woodruff2@ti.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24 #include <common.h>
25 #include <asm/arch/omap2420.h>
26 #include <asm/arch/bits.h>
27
28 #include <asm/arch/mem.h>
29 #include <asm/arch/sys_info.h>
30 #include <asm/arch/clocks.h>
31
32 static void wait_for_command_complete(unsigned int wd_base);
33 static void watchdog_init(void);
34 static void peripheral_enable(void);
35 static void muxSetupUART1(void);
36 static u32  get_cpu_rev(void);
37
38
39 /*******************************************************
40  * Routine: delay
41  * Description: spinning delay to use before udelay works
42  ******************************************************/
43 static inline void delay (unsigned long loops)
44 {
45         __asm__ volatile ("1:\n"
46                                           "subs %0, %1, #1\n"
47                                           "bne 1b":"=r" (loops):"0" (loops));
48 }
49
50 /*****************************************
51  * Routine: board_init
52  * Description: Early hardware init.
53  *****************************************/
54 int board_init (void)
55 {
56         return 0;
57 }
58
59 #ifdef CFG_SDRAM_DDR
60 void
61 config_sdram_ddr(u32 rev)
62 {
63         /* ball D11, mode 0 */
64         __raw_writeb(0x08, 0x48000032);
65
66         /* SDRC_CS0 Configuration */
67         if (rev == CPU_2420_2422_ES1) {
68                 __raw_writel(H4_2422_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
69                 __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING);
70         } else {
71                 __raw_writel(H4_2420_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
72                 __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
73         }
74
75         __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL);
76         __raw_writel(H4_242x_SDRC_ACTIM_CTRLA_0_ES1, SDRC_ACTIM_CTRLA_0);
77         __raw_writel(H4_242x_SDRC_ACTIM_CTRLB_0_ES1, SDRC_ACTIM_CTRLB_0);
78
79         /* Manual Command sequence */
80         __raw_writel(CMD_NOP, SDRC_MANUAL_0);
81         __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
82         __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
83         __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
84
85
86         /* 
87          * CS0 SDRC Mode Register
88          * Burst length = 4 - DDR memory
89          * Serial mode
90          * CAS latency = 3 
91          */
92         __raw_writel(0x00000032, SDRC_MR_0);
93
94         /* SDRC DLLA control register */
95         /* Delay is 90 degrees */
96         if (rev == CPU_2420_2422_ES1) {
97                 /* Enable DLL, Load counter with 115 (middle of range) */ 
98                 __raw_writel(0x00000002, SDRC_DLLA_CTRL);
99                 /* Enable DLL, Load counter with 128 (middle of range) */ 
100                 __raw_writel(0x00000002, SDRC_DLLB_CTRL);
101         } else {
102                 /* Enable DLL, Load counter with 115 (middle of range) */ 
103                 __raw_writel(0x00000008, SDRC_DLLA_CTRL);       // ES2.x
104                 /* Enable DLL, Load counter with 128 (middle of range) */ 
105                 __raw_writel(0x00000008, SDRC_DLLB_CTRL);       // ES2.x
106         }
107
108 }
109 #endif // CFG_SDRAM_DDR
110
111
112 #ifdef CFG_SDRAM_COMBO 
113 void
114 config_sdram_combo(u32 rev)
115 {
116
117         u32 dllctrl=0;
118
119         /* ball C12, mode 0 */
120         __raw_writeb(0x00, 0x480000a1);
121         /* ball D11, mode 0 */
122         __raw_writeb(0x00, 0x48000032);
123         /* ball B13, mode 0 - for CKE1 (not needed rkw for combo) */
124         __raw_writeb(0x00, 0x480000a3);
125
126         /*configure sdrc 32 bit for COMBO ddr sdram. Issue soft reset */
127         __raw_writel(0x00000012, SDRC_SYSCONFIG);
128         delay(200000);
129         __raw_writel(0x00000010, SDRC_SYSCONFIG);
130
131         /* SDRCTriState: no Tris */
132         /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */
133         __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
134
135
136         /* CS0 SDRC Memory Configuration, */
137         /* DDR-SDRAM, External SDRAM is x32bit, */
138         /* Configure to MUX9: 1x8Mbx32  */
139         __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_0);
140         __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
141         __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
142         __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL);
143
144         /* Manual Command sequence */
145         __raw_writel(CMD_NOP, SDRC_MANUAL_0);
146         __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
147         __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
148         __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
149
150         /* CS0 SDRC Mode Register */
151         /* Burst length = 4 - DDR memory */
152         /* Serial mode */
153         /* CAS latency = 3  */
154         __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_0);
155
156         /* CS1 SDRC Memory Configuration, */
157         /* DDR-SDRAM, External SDRAM is x32bit, */
158         /* Configure to MUX9: 1x8Mbx32 */
159         __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_1);
160         __raw_writel(H4_242X_SDRC_ACTIM_CTRLA_0_100MHz, SDRC_ACTIM_CTRLA_1);
161         __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1);
162         __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, 0x680090d4);
163
164         /* Manual Command sequence */
165         __raw_writel(CMD_NOP, SDRC_MANUAL_1);
166         __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1);
167         __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
168         __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
169
170         /* CS1 SDRC Mode Register */
171         /* Burst length = 4 - DDR memory */
172         /* Serial mode */
173         /* CAS latency = 3 */
174         __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_1);
175
176         /* SDRC DLLA control register */
177         /* Delay is 90 degrees */
178         if (rev == CPU_242X_ES1)
179                 dllctrl = (BIT0|BIT3);
180         else
181                 dllctrl = BIT0;         
182
183         if (rev == CPU_2420_2422_ES1) {
184                 /* Enable DLL, Load counter with 115 (middle of range) */
185                 __raw_writel(0x00007306, SDRC_DLLA_CTRL);
186                 __raw_writel(0x00007302, SDRC_DLLA_CTRL);
187                 /* Enable DLL, Load counter with 128 (middle of range)  */
188                 __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */
189                 __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */
190         }
191         else {
192                 /* Enable DLL, Load counter with 115 (middle of range) */
193                 __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);   // ES2.x
194                 __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x
195                 __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL);   // ES2.x ?
196                 __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x
197         }
198 }
199
200 #endif // CFG_SDRAM_COMBO
201
202 #ifdef CFG_SDRAM_SDR 
203 void
204 config_sdram_sdr(u32 rev)
205 {
206         u32 dllctrl=0;
207
208         /* ball D11, mode 0 */
209         __raw_writeb(0x00, 0x48000032);
210
211         __raw_writel(0x00000012, SDRC_SYSCONFIG);
212         delay(200000);
213         __raw_writel(0x00000010, SDRC_SYSCONFIG);
214
215         /* Chip-level shared interface management */
216         /* SDRCTriState: no Tris */
217         /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */
218         /* CS1MuxCfg: 000 (32-bit SDRAM on D31..0) */
219         if (rev == CPU_2420_2422_ES1)
220                 __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING);
221         else
222                 __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
223
224         /* CS0 SDRC Memory Configuration, */
225         /* DDR-SDRAM, External SDRAM is x32bit, */
226         /* Configure to MUX14: 32Mbx32 */
227         __raw_writel(H4_2420_SDRC_MDCFG_0_SDR, SDRC_MCFG_0); /* diff from combo case */
228         __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
229         __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
230         __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL);
231
232         /* Manual Command sequence */
233         __raw_writel(CMD_NOP, SDRC_MANUAL_0);
234         __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
235         __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
236         __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
237  
238         /* CS0 SDRC Mode Register */
239         /* Burst length = 2 - SDR memory */
240         /* Serial mode */
241         /* CAS latency = 3  */
242         __raw_writel(H4_2420_SDRC_MR_0_SDR, SDRC_MR_0);  /* diff from combo case */
243
244         /* SDRC DLLA control register */
245         /* Enable DLL, Load counter with 115 (middle of range) */ 
246         /* Delay is 90 degrees */
247
248         if (rev == CPU_242X_ES1)
249                 dllctrl = (BIT0|BIT3);
250         else
251                 dllctrl = BIT0;
252
253         if (rev == CPU_2420_2422_ES1) {
254                 __raw_writel(0x00007306, SDRC_DLLA_CTRL);
255                 __raw_writel(0x00007302, SDRC_DLLA_CTRL);
256                 /* Enable DLL, Load counter with 128 (middle of range) */ 
257                 __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */
258                 __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */
259         }
260         else {
261                 __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);  // ES2.x
262                 __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL);     // ES2.x
263                 /* Enable DLL, Load counter with 128 (middle of range) */ 
264                 __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL);  // ES2.x
265                 __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL);     // ES2.x
266         }
267    
268 }
269 #endif // CFG_SDRAM_SDR
270
271 #ifdef CFG_SDRAM_STACKED 
272 void
273 config_sdram_stacked(u32 rev)
274 {
275
276         /* Pin Muxing for SDRC */
277         __raw_writeb(0x00, 0x480000a1); /* mux mode 0 (CS1) */
278         __raw_writeb(0x00, 0x480000a3); /* mux mode 0 (CKE1) */
279         __raw_writeb(0x00, 0x48000032); /* connect sdrc_a12 */
280         __raw_writeb(0x00, 0x48000031); /* connect sdrc_a13 */
281
282         /* configure sdrc 32 bit for COMBO ddr sdram */
283         __raw_writel(0x00000010, SDRC_SYSCONFIG);       /* no idle ack and RESET enable */
284         delay(200000);
285         __raw_writel(0x00000010, SDRC_SYSCONFIG);       /* smart idle mode */
286
287         /* SDRC_SHARING */
288         /* U-boot is writing 0x00000100 though (H4_2420_SDRC_SHARING ) */
289         //__raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
290
291         __raw_writel(0x00004900, SDRC_SHARING);
292
293         /* SDRC_CS0 Configuration */
294         /* None for ES2.1 */
295
296         /*  SDRC_CS1 Configuration */
297         __raw_writel(0x00000000, SDRC_CS_CFG);  /* Remap CS1 to 0x80000000 */
298
299         /* Disable power down of CKE */
300         __raw_writel(0x00000085, SDRC_POWER);
301
302         __raw_writel(0x01A02019, SDRC_MCFG_1);  /* SDRC_MCFG1 */
303         __raw_writel(0x0003DD03, SDRC_RFR_CTRL1);       /* SDRC_RFR_CTRL1 */
304         __raw_writel(0x92DDC485, SDRC_ACTIM_CTRLA_1);   /* SDRC_ACTIM_CTRLA0 */
305         __raw_writel(0x00000014, SDRC_ACTIM_CTRLB_1);   /* SDRC_ACTIM_CTRLB0 */
306
307         /*Manual Command sequence */
308         __raw_writel(CMD_NOP, SDRC_MANUAL_1);
309         __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1);
310         __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
311         __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
312
313         /* CS0 SDRC Mode Register */
314         /* Burst length = 4 - DDR memory */
315         /* Serial mode */
316         /* CAS latency = 3  */
317         __raw_writel(0x00000032, SDRC_MR_1);
318         __raw_writel(0x00000020, SDRC_EMR2_1);  /* weak-strength driver */
319
320         /* SDRC DLLA control register */
321         /* Delay is 90 degrees */
322         if (rev == CPU_2420_2422_ES1) {
323                 /* Enable DLL, Load counter with 115 (middle of range) */ 
324                 __raw_writel(0x00007302, SDRC_DLLA_CTRL);
325                 /* Enable DLL, Load counter with 128 (middle of range) */ 
326                 __raw_writel(0x00007302, SDRC_DLLB_CTRL);
327         }
328         else {
329                 /* Enable DLL, Load counter with 115 (middle of range) */ 
330                 __raw_writel(0x00003108, SDRC_DLLA_CTRL);       // ES2.x
331                 /* Enable DLL, Load counter with 128 (middle of range) */ 
332                 __raw_writel(0x00003108, SDRC_DLLB_CTRL);       // ES2.x
333         }
334 }
335 #endif // CFG_SDRAM_STACKED
336
337 /**********************************************************
338  * Routine: s_init
339  * Description: Does early system init of muxing and clocks.
340  * - Called at time when only stack is available.
341  **********************************************************/
342 int s_init(int skip)
343 {
344         u32   rev;
345
346         rev = get_cpu_rev();
347
348         watchdog_init();
349         muxSetupUART1();
350         delay(100);
351
352         /*DPLL out = 2x DPLL --> core clock */
353         __raw_writel(DPLL_OUT, CM_CLKSEL2_PLL);
354
355         /*DPLL into low power bypass (others off) */
356         __raw_writel(0x00000001, CM_CLKEN_PLL);
357
358         /*MPU core clock = Core /2 = 300 */
359         __raw_writel(MPU_DIV, CM_CLKSEL_MPU);
360
361         /*DSPif=200, DSPif=100, IVA=200 */
362         __raw_writel(DSP_DIV, CM_CLKSEL_DSP);
363
364         /*GFX clock (L3/2) 50MHz */
365         __raw_writel(GFX_DIV, CM_CLKSEL_GFX);
366
367         /*L3=100, L4=100, DisplaySS=50 Vlync=96Mhz,ssi=100, usb=50 */
368         __raw_writel(BUS_DIV, CM_CLKSEL1_CORE);
369
370         /*12MHz apll src, 12/(1+1)*50=300 */
371         __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL);
372
373         /*Valid the configuration */
374         __raw_writel(0x00000001, PRCM_CLKCFG_CTRL);
375         delay(1000);
376
377         /*Enable DPLL=300, 96MHz APLL locked. */
378         __raw_writel(0x0000000F, CM_CLKEN_PLL);
379         delay(200000);
380
381 #ifdef CFG_SDRAM_DDR
382         config_sdram_ddr(rev);
383 #elif defined(CFG_SDRAM_COMBO)
384         config_sdram_combo(rev);
385 #elif defined(CFG_SDRAM_SDR)
386         config_sdram_sdr(rev);
387 #elif defined(CFG_SDRAM_STACKED)
388         config_sdram_stacked(rev);
389 #else
390 #error SDRAM type not supported
391 #endif  
392
393         delay(20000);
394         peripheral_enable();
395         return(0);
396 }
397
398 /*******************************************************
399  * Routine: misc_init_r
400  * Description: Init ethernet (done here so udelay works)
401  ********************************************************/
402 int misc_init_r (void)
403 {
404         return(0);
405 }
406
407 /****************************************
408  * Routine: watchdog_init
409  * Description: Shut down watch dogs
410  *****************************************/
411 static void watchdog_init(void)
412 {
413 #define GP (BIT8|BIT9)
414
415         /* There are 4 watch dogs.  1 secure, and 3 general purpose.
416          * I would expect that the ROM takes care of the secure one,
417          * but we will try also.  Of the 3 GP ones, 1 can reset us
418          * directly, the other 2 only generate MPU interrupts.
419          */
420         __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
421         wait_for_command_complete(WD2_BASE);
422         __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
423
424 #if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/
425         __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR);
426         wait_for_command_complete(WD3_BASE);
427         __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR);
428
429         __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR);
430         wait_for_command_complete(WD4_BASE);
431         __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR);
432 #endif
433
434 }
435
436 /******************************************************
437  * Routine: wait_for_command_complete
438  * Description: Wait for posting to finish on watchdog
439  ******************************************************/
440 static void wait_for_command_complete(unsigned int wd_base)
441 {
442         int pending = 1;
443         do {
444                 pending = __raw_readl(wd_base+WWPS);
445         } while (pending);
446 }
447
448
449 /**********************************************
450  * Routine: dram_init
451  * Description: sets uboots idea of sdram size
452  **********************************************/
453 int dram_init (void)
454 {
455         return 0;
456 }
457  
458 /*****************************************************************
459  * Routine: peripheral_enable
460  * Description: Enable the clks & power for perifs (GPT2, UART1,...)
461  ******************************************************************/
462 static void peripheral_enable(void)
463 {
464         unsigned int v, if_clks=0, func_clks=0;
465
466         /* Enable GP2 timer.*/
467         if_clks |= BIT4;
468         func_clks |= BIT4;
469         v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */
470         __raw_writel(v, CM_CLKSEL2_CORE);
471         __raw_writel(0x1, CM_CLKSEL_WKUP);
472
473 #ifdef CFG_NS16550
474         /* Enable UART1 clock */
475         func_clks |= BIT21;
476         if_clks |= BIT21;
477 #endif
478         v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;     /* Interface clocks on */
479         __raw_writel(v,CM_ICLKEN1_CORE );
480         v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
481         __raw_writel(v, CM_FCLKEN1_CORE);
482         delay(1000);
483
484 #ifndef KERNEL_UPDATED
485         {
486 #define V1 0xffffffff
487 #define V2 0x00000007
488
489                 __raw_writel(V1, CM_FCLKEN1_CORE);
490                 __raw_writel(V2, CM_FCLKEN2_CORE);
491                 __raw_writel(V1, CM_ICLKEN1_CORE);
492                 __raw_writel(V1, CM_ICLKEN2_CORE);
493         }
494 #endif
495
496 }
497
498 /* Pin Muxing registers used for UART1 */
499 #define CONTROL_PADCONF_UART1_CTS       ((volatile unsigned char *)0x480000C5)
500 #define CONTROL_PADCONF_UART1_RTS       ((volatile unsigned char *)0x480000C6)
501 #define CONTROL_PADCONF_UART1_TX        ((volatile unsigned char *)0x480000C7)
502 #define CONTROL_PADCONF_UART1_RX        ((volatile unsigned char *)0x480000C8)
503 /****************************************
504  * Routine: muxSetupUART1  (ostboot)
505  * Description: Set up uart1 muxing
506  *****************************************/
507 static void muxSetupUART1(void)
508 {
509         volatile unsigned char  *MuxConfigReg;
510
511         /* UART1_CTS pin configuration, PIN = D21 */
512         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
513         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
514
515         /* UART1_RTS pin configuration, PIN = H21 */
516         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
517         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
518
519         /* UART1_TX pin configuration, PIN = L20 */
520         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
521         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
522
523         /* UART1_RX pin configuration, PIN = T21 */
524         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
525         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
526 }
527
528 int nand_init(void)
529 {
530         u32     rev;
531
532         rev = get_cpu_rev();
533
534
535         /* GPMC pin muxing */ 
536         (*(volatile int*)0x48000070) &= 0x000000FF;
537         (*(volatile int*)0x48000074) &= 0x00000000;
538         (*(volatile int*)0x48000078) &= 0x00000000;
539         (*(volatile int*)0x4800007C) &= 0x00000000;
540         (*(volatile int*)0x48000080) &= 0xFF000000;
541
542         /* GPMC_IO_DIR */
543         (*(volatile int*)0x4800008C) = 0x19000000;
544
545         /* GPMC Configuration */
546         (*(volatile int*)0x6800A010) = 0x0000000A;
547         while (((*(volatile int *)0x6800A014) & 0x00000001) == 0);
548
549         (*(volatile int*)0x6800A050) = 0x00000001;      
550         (*(volatile int*)0x6800A060) = 0x00001800;      
551         (*(volatile int*)0x6800A064) = 0x00141400;      
552         (*(volatile int*)0x6800A068) = 0x00141400;      
553         (*(volatile int*)0x6800A06C) = 0x0F010F01;      
554         (*(volatile int*)0x6800A070) = 0x010C1414;
555         (*(volatile int*)0x6800A074) = 0x00000A80;
556         (*(volatile int*)0x6800A078) = 0x00000C44;      //base 0x04000000
557
558         (*(volatile int*)0x6800A0A8) = 0x00000000;
559         delay(1000);
560 #ifdef CFG_SDRAM_STACKED
561         (*(volatile int*)0x6800A090) = 0x00011000;
562 #else
563         (*(volatile int*)0x6800A090) = 0x00011200;
564 #endif
565         (*(volatile int*)0x6800A094) = 0x001f1f00;
566         (*(volatile int*)0x6800A098) = 0x00080802;
567         (*(volatile int*)0x6800A09C) = 0x1C091C09;
568         (*(volatile int*)0x6800A0A0) = 0x031A1F1F;
569         (*(volatile int*)0x6800A0A4) = 0x000003C2;
570         (*(volatile int*)0x6800A0A8) = 0x00000F48;
571
572         if (rev != CPU_2420_2422_ES1)
573                 (*(volatile int*)0x6800A040) = 0x1FF0;  // es2.x
574
575         if (nand_chip()){
576                 printf("Unsupported Chip!\n");
577                 return 1;
578         }
579         return 0;
580 }
581
582 /******************************************
583  * get_cpu_rev(void) - extract version info
584  ******************************************/
585 u32 get_cpu_rev(void)
586 {
587         u32 v;
588         v = __raw_readl(TAP_IDCODE_REG);
589         v = v >> 28;
590         return(v+1);  /* currently 2422 and 2420 match up */
591 }
592
593 /* optionally do something like blinking LED */
594 void board_hang (void)
595 {}
596
597
598