omap_hsmmc: enable sdio_irq.
[replicant:kernel_goldelico_gta04.git] / drivers / mmc / host / omap_hsmmc.c
1 /*
2  * drivers/mmc/host/omap_hsmmc.c
3  *
4  * Driver for OMAP2430/3430 MMC controller.
5  *
6  * Copyright (C) 2007 Texas Instruments.
7  *
8  * Authors:
9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
10  *      Madhusudhan             <madhu.cr@ti.com>
11  *      Mohit Jalori            <mjalori@ti.com>
12  *
13  * This file is licensed under the terms of the GNU General Public License
14  * version 2. This program is licensed "as is" without any warranty of any
15  * kind, whether express or implied.
16  */
17
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/dmaengine.h>
23 #include <linux/seq_file.h>
24 #include <linux/sizes.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_device.h>
29 #include <linux/timer.h>
30 #include <linux/clk.h>
31 #include <linux/of.h>
32 #include <linux/of_gpio.h>
33 #include <linux/of_device.h>
34 #include <linux/omap-dma.h>
35 #include <linux/mmc/host.h>
36 #include <linux/mmc/core.h>
37 #include <linux/mmc/mmc.h>
38 #include <linux/io.h>
39 #include <linux/gpio.h>
40 #include <linux/regulator/consumer.h>
41 #include <linux/pinctrl/consumer.h>
42 #include <linux/pm_runtime.h>
43 #include <linux/platform_data/mmc-omap.h>
44
45 /* OMAP HSMMC Host Controller Registers */
46 #define OMAP_HSMMC_SYSSTATUS    0x0014
47 #define OMAP_HSMMC_CON          0x002C
48 #define OMAP_HSMMC_BLK          0x0104
49 #define OMAP_HSMMC_ARG          0x0108
50 #define OMAP_HSMMC_CMD          0x010C
51 #define OMAP_HSMMC_RSP10        0x0110
52 #define OMAP_HSMMC_RSP32        0x0114
53 #define OMAP_HSMMC_RSP54        0x0118
54 #define OMAP_HSMMC_RSP76        0x011C
55 #define OMAP_HSMMC_DATA         0x0120
56 #define OMAP_HSMMC_HCTL         0x0128
57 #define OMAP_HSMMC_SYSCTL       0x012C
58 #define OMAP_HSMMC_STAT         0x0130
59 #define OMAP_HSMMC_IE           0x0134
60 #define OMAP_HSMMC_ISE          0x0138
61 #define OMAP_HSMMC_CAPA         0x0140
62
63 #define VS18                    (1 << 26)
64 #define VS30                    (1 << 25)
65 #define HSS                     (1 << 21)
66 #define SDVS18                  (0x5 << 9)
67 #define SDVS30                  (0x6 << 9)
68 #define SDVS33                  (0x7 << 9)
69 #define SDVS_MASK               0x00000E00
70 #define SDVSCLR                 0xFFFFF1FF
71 #define SDVSDET                 0x00000400
72 #define AUTOIDLE                0x1
73 #define SDBP                    (1 << 8)
74 #define DTO                     0xe
75 #define ICE                     0x1
76 #define ICS                     0x2
77 #define CEN                     (1 << 2)
78 #define CLKD_MASK               0x0000FFC0
79 #define CLKD_SHIFT              6
80 #define DTO_MASK                0x000F0000
81 #define DTO_SHIFT               16
82 #define INIT_STREAM             (1 << 1)
83 #define DP_SELECT               (1 << 21)
84 #define DDIR                    (1 << 4)
85 #define DMAE                    0x1
86 #define MSBS                    (1 << 5)
87 #define BCE                     (1 << 1)
88 #define FOUR_BIT                (1 << 1)
89 #define HSPE                    (1 << 2)
90 #define DDR                     (1 << 19)
91 #define CTPL                    (1 << 11)
92 #define CLKEXTFREE              (1 << 16)
93 #define DW8                     (1 << 5)
94 #define OD                      0x1
95 #define STAT_CLEAR              0xFFFFFFFF
96 #define INIT_STREAM_CMD         0x00000000
97 #define DUAL_VOLT_OCR_BIT       7
98 #define SRC                     (1 << 25)
99 #define SRD                     (1 << 26)
100 #define SOFTRESET               (1 << 1)
101 #define RESETDONE               (1 << 0)
102
103 /* Interrupt masks for IE and ISE register */
104 #define CC_EN                   (1 << 0)
105 #define TC_EN                   (1 << 1)
106 #define BWR_EN                  (1 << 4)
107 #define BRR_EN                  (1 << 5)
108 #define CIRQ_EN                 (1 << 8)
109 #define ERR_EN                  (1 << 15)
110 #define CTO_EN                  (1 << 16)
111 #define CCRC_EN                 (1 << 17)
112 #define CEB_EN                  (1 << 18)
113 #define CIE_EN                  (1 << 19)
114 #define DTO_EN                  (1 << 20)
115 #define DCRC_EN                 (1 << 21)
116 #define DEB_EN                  (1 << 22)
117 #define CERR_EN                 (1 << 28)
118 #define BADA_EN                 (1 << 29)
119
120 #define INT_EN_MASK             (BADA_EN | CERR_EN | DEB_EN | DCRC_EN |\
121                 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
122                 BRR_EN | BWR_EN | TC_EN | CC_EN)
123
124 #define MMC_AUTOSUSPEND_DELAY   100
125 #define MMC_TIMEOUT_MS          20
126 #define OMAP_MMC_MIN_CLOCK      400000
127 #define OMAP_MMC_MAX_CLOCK      52000000
128 #define DRIVER_NAME             "omap_hsmmc"
129
130 /*
131  * One controller can have multiple slots, like on some omap boards using
132  * omap.c controller driver. Luckily this is not currently done on any known
133  * omap_hsmmc.c device.
134  */
135 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
136
137 /*
138  * MMC Host controller read/write API's
139  */
140 #define OMAP_HSMMC_READ(base, reg)      \
141         __raw_readl((base) + OMAP_HSMMC_##reg)
142
143 #define OMAP_HSMMC_WRITE(base, reg, val) \
144         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
145
146 struct omap_hsmmc_next {
147         unsigned int    dma_len;
148         s32             cookie;
149 };
150
151 struct omap_hsmmc_host {
152         struct  device          *dev;
153         struct  mmc_host        *mmc;
154         struct  mmc_request     *mrq;
155         struct  mmc_command     *cmd;
156         struct  mmc_data        *data;
157         struct  clk             *fclk;
158         struct  clk             *dbclk;
159         /*
160          * vcc == configured supply
161          * vcc_aux == optional
162          *   -  MMC1, supply for DAT4..DAT7
163          *   -  MMC2/MMC2, external level shifter voltage supply, for
164          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
165          */
166         struct  regulator       *vcc;
167         struct  regulator       *vcc_aux;
168         int                     pbias_disable;
169         void    __iomem         *base;
170         resource_size_t         mapbase;
171         spinlock_t              irq_lock; /* Prevent races with irq handler */
172         unsigned int            dma_len;
173         unsigned int            dma_sg_idx;
174         unsigned char           bus_mode;
175         unsigned char           power_mode;
176         int                     suspended;
177         int                     irq;
178         int                     use_dma, dma_ch;
179         struct dma_chan         *tx_chan;
180         struct dma_chan         *rx_chan;
181         int                     slot_id;
182         int                     response_busy;
183         int                     context_loss;
184         int                     protect_card;
185         int                     reqs_blocked;
186         int                     use_reg;
187         int                     req_in_progress;
188         int                     sdio_int;
189         int                     irq_requested;/* Keep fclk going if interrupt
190                                                * handler is registered */
191         struct omap_hsmmc_next  next_data;
192
193         struct  omap_mmc_platform_data  *pdata;
194 };
195
196 static int omap_hsmmc_card_detect(struct device *dev, int slot)
197 {
198         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
199         struct omap_mmc_platform_data *mmc = host->pdata;
200
201         /* NOTE: assumes card detect signal is active-low */
202         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
203 }
204
205 static int omap_hsmmc_get_wp(struct device *dev, int slot)
206 {
207         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
208         struct omap_mmc_platform_data *mmc = host->pdata;
209
210         /* NOTE: assumes write protect signal is active-high */
211         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
212 }
213
214 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
215 {
216         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
217         struct omap_mmc_platform_data *mmc = host->pdata;
218
219         /* NOTE: assumes card detect signal is active-low */
220         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
221 }
222
223 #ifdef CONFIG_PM
224
225 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
226 {
227         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
228         struct omap_mmc_platform_data *mmc = host->pdata;
229
230         disable_irq(mmc->slots[0].card_detect_irq);
231         return 0;
232 }
233
234 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
235 {
236         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
237         struct omap_mmc_platform_data *mmc = host->pdata;
238
239         enable_irq(mmc->slots[0].card_detect_irq);
240         return 0;
241 }
242
243 #else
244
245 #define omap_hsmmc_suspend_cdirq        NULL
246 #define omap_hsmmc_resume_cdirq         NULL
247
248 #endif
249
250 #ifdef CONFIG_REGULATOR
251
252 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
253                                    int vdd)
254 {
255         struct omap_hsmmc_host *host =
256                 platform_get_drvdata(to_platform_device(dev));
257         int ret = 0;
258
259         /*
260          * If we don't see a Vcc regulator, assume it's a fixed
261          * voltage always-on regulator.
262          */
263         if (!host->vcc)
264                 return 0;
265         /*
266          * With DT, never turn OFF the regulator for MMC1. This is because
267          * the pbias cell programming support is still missing when
268          * booting with Device tree
269          */
270         if (host->pbias_disable && !vdd)
271                 return 0;
272
273         if (gpio_is_valid(mmc_slot(host).gpio_reset))
274                 gpio_set_value_cansleep(mmc_slot(host).gpio_reset, 0);
275         if (mmc_slot(host).before_set_reg)
276                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
277
278         /*
279          * Assume Vcc regulator is used only to power the card ... OMAP
280          * VDDS is used to power the pins, optionally with a transceiver to
281          * support cards using voltages other than VDDS (1.8V nominal).  When a
282          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
283          *
284          * In some cases this regulator won't support enable/disable;
285          * e.g. it's a fixed rail for a WLAN chip.
286          *
287          * In other cases vcc_aux switches interface power.  Example, for
288          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
289          * chips/cards need an interface voltage rail too.
290          */
291         if (power_on) {
292                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
293                 /* Enable interface voltage rail, if needed */
294                 if (ret == 0 && host->vcc_aux) {
295                         ret = regulator_enable(host->vcc_aux);
296                         if (ret < 0)
297                                 ret = mmc_regulator_set_ocr(host->mmc,
298                                                         host->vcc, 0);
299                 }
300         } else {
301                 /* Shut down the rail */
302                 if (host->vcc_aux)
303                         ret = regulator_disable(host->vcc_aux);
304                 if (!ret) {
305                         /* Then proceed to shut down the local regulator */
306                         ret = mmc_regulator_set_ocr(host->mmc,
307                                                 host->vcc, 0);
308                 }
309         }
310
311         if (mmc_slot(host).after_set_reg)
312                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
313         if (gpio_is_valid(mmc_slot(host).gpio_reset))
314                 gpio_set_value_cansleep(mmc_slot(host).gpio_reset, 1);
315
316         return ret;
317 }
318
319 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
320 {
321         struct regulator *reg;
322         int ocr_value = 0;
323
324         reg = regulator_get(host->dev, "vmmc");
325         if (IS_ERR(reg)) {
326                 dev_err(host->dev, "vmmc regulator missing\n");
327                 return PTR_ERR(reg);
328         } else {
329                 mmc_slot(host).set_power = omap_hsmmc_set_power;
330                 host->vcc = reg;
331                 ocr_value = mmc_regulator_get_ocrmask(reg);
332                 if (!mmc_slot(host).ocr_mask) {
333                         mmc_slot(host).ocr_mask = ocr_value;
334                 } else {
335                         if (!(mmc_slot(host).ocr_mask & ocr_value)) {
336                                 dev_err(host->dev, "ocrmask %x is not supported\n",
337                                         mmc_slot(host).ocr_mask);
338                                 mmc_slot(host).ocr_mask = 0;
339                                 return -EINVAL;
340                         }
341                 }
342
343                 /* Allow an aux regulator */
344                 reg = regulator_get(host->dev, "vmmc_aux");
345                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
346
347                 /* For eMMC do not power off when not in sleep state */
348                 if (mmc_slot(host).no_regulator_off_init)
349                         return 0;
350                 /*
351                 * UGLY HACK:  workaround regulator framework bugs.
352                 * When the bootloader leaves a supply active, it's
353                 * initialized with zero usecount ... and we can't
354                 * disable it without first enabling it.  Until the
355                 * framework is fixed, we need a workaround like this
356                 * (which is safe for MMC, but not in general).
357                 */
358                 if (regulator_is_enabled(host->vcc) > 0 ||
359                     (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
360                         int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
361
362                         mmc_slot(host).set_power(host->dev, host->slot_id,
363                                                  1, vdd);
364                         mmc_slot(host).set_power(host->dev, host->slot_id,
365                                                  0, 0);
366                 }
367         }
368
369         return 0;
370 }
371
372 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
373 {
374         regulator_put(host->vcc);
375         regulator_put(host->vcc_aux);
376         mmc_slot(host).set_power = NULL;
377 }
378
379 static inline int omap_hsmmc_have_reg(void)
380 {
381         return 1;
382 }
383
384 #else
385
386 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
387 {
388         return -EINVAL;
389 }
390
391 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
392 {
393 }
394
395 static inline int omap_hsmmc_have_reg(void)
396 {
397         return 0;
398 }
399
400 #endif
401
402 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
403 {
404         int ret;
405
406         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
407                 if (pdata->slots[0].cover)
408                         pdata->slots[0].get_cover_state =
409                                         omap_hsmmc_get_cover_state;
410                 else
411                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
412                 pdata->slots[0].card_detect_irq =
413                                 gpio_to_irq(pdata->slots[0].switch_pin);
414                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
415                 if (ret)
416                         return ret;
417                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
418                 if (ret)
419                         goto err_free_sp;
420         } else
421                 pdata->slots[0].switch_pin = -EINVAL;
422
423         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
424                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
425                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
426                 if (ret)
427                         goto err_free_cd;
428                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
429                 if (ret)
430                         goto err_free_wp;
431         } else
432                 pdata->slots[0].gpio_wp = -EINVAL;
433
434         if (gpio_is_valid(pdata->slots[0].gpio_reset)) {
435                 ret = gpio_request(pdata->slots[0].gpio_reset, "mmc_reset");
436                 if (ret)
437                         goto err_free_wp;
438                 ret = gpio_direction_output(pdata->slots[0].gpio_reset, 1);
439                 if (ret)
440                         goto err_free_reset;
441         } else
442                 pdata->slots[0].gpio_reset = -EINVAL;
443
444         return 0;
445 err_free_reset:
446         gpio_free(pdata->slots[0].gpio_reset);
447 err_free_wp:
448         if (gpio_is_valid(pdata->slots[0].gpio_wp))
449                 gpio_free(pdata->slots[0].gpio_wp);
450 err_free_cd:
451         if (gpio_is_valid(pdata->slots[0].switch_pin))
452 err_free_sp:
453                 gpio_free(pdata->slots[0].switch_pin);
454         return ret;
455 }
456
457 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
458 {
459         if (gpio_is_valid(pdata->slots[0].gpio_reset))
460                 gpio_free(pdata->slots[0].gpio_reset);
461         if (gpio_is_valid(pdata->slots[0].gpio_wp))
462                 gpio_free(pdata->slots[0].gpio_wp);
463         if (gpio_is_valid(pdata->slots[0].switch_pin))
464                 gpio_free(pdata->slots[0].switch_pin);
465 }
466
467 /*
468  * Start clock to the card
469  */
470 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
471 {
472         OMAP_HSMMC_WRITE(host->base, SYSCTL,
473                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
474 }
475
476 /*
477  * Stop clock to the card
478  */
479 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
480 {
481         OMAP_HSMMC_WRITE(host->base, SYSCTL,
482                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
483         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
484                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
485 }
486
487 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
488                                   struct mmc_command *cmd)
489 {
490         unsigned int irq_mask = INT_EN_MASK;
491         unsigned long flags;
492
493         spin_lock_irqsave(&host->irq_lock, flags);
494         if (host->use_dma)
495                 irq_mask &= ~(BRR_EN | BWR_EN);
496         if (host->sdio_int)
497                 irq_mask |= CIRQ_EN;
498
499         /* Disable timeout for erases */
500         if (cmd && cmd->opcode == MMC_ERASE)
501                 irq_mask &= ~DTO_EN;
502
503         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
504         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
505         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
506         spin_unlock_irqrestore(&host->irq_lock, flags);
507 }
508
509 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
510 {
511         unsigned int irq_mask = 0;
512         unsigned long flags;
513
514         spin_lock_irqsave(&host->irq_lock, flags);
515         if (host->sdio_int)
516                 irq_mask |= CIRQ_EN;
517         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
518         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
519         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
520         spin_unlock_irqrestore(&host->irq_lock, flags);
521 }
522
523 /* Calculate divisor for the given clock frequency */
524 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
525 {
526         u16 dsor = 0;
527
528         if (ios->clock) {
529                 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
530                 if (dsor > 250)
531                         dsor = 250;
532         }
533
534         return dsor;
535 }
536
537 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
538 {
539         struct mmc_ios *ios = &host->mmc->ios;
540         unsigned long regval;
541         unsigned long timeout;
542         unsigned long clkdiv;
543
544         dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
545
546         omap_hsmmc_stop_clock(host);
547
548         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
549         regval = regval & ~(CLKD_MASK | DTO_MASK);
550         clkdiv = calc_divisor(host, ios);
551         regval = regval | (clkdiv << 6) | (DTO << 16);
552         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
553         OMAP_HSMMC_WRITE(host->base, SYSCTL,
554                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
555
556         /* Wait till the ICS bit is set */
557         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
558         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
559                 && time_before(jiffies, timeout))
560                 cpu_relax();
561
562         /*
563          * Enable High-Speed Support
564          * Pre-Requisites
565          *      - Controller should support High-Speed-Enable Bit
566          *      - Controller should not be using DDR Mode
567          *      - Controller should advertise that it supports High Speed
568          *        in capabilities register
569          *      - MMC/SD clock coming out of controller > 25MHz
570          */
571         if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
572             (ios->timing != MMC_TIMING_UHS_DDR50) &&
573             ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
574                 regval = OMAP_HSMMC_READ(host->base, HCTL);
575                 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
576                         regval |= HSPE;
577                 else
578                         regval &= ~HSPE;
579
580                 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
581         }
582
583         omap_hsmmc_start_clock(host);
584 }
585
586 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
587 {
588         struct mmc_ios *ios = &host->mmc->ios;
589         u32 con;
590
591         con = OMAP_HSMMC_READ(host->base, CON);
592         if (ios->timing == MMC_TIMING_UHS_DDR50)
593                 con |= DDR;     /* configure in DDR mode */
594         else
595                 con &= ~DDR;
596         switch (ios->bus_width) {
597         case MMC_BUS_WIDTH_8:
598                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
599                 break;
600         case MMC_BUS_WIDTH_4:
601                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
602                 OMAP_HSMMC_WRITE(host->base, HCTL,
603                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
604                 break;
605         case MMC_BUS_WIDTH_1:
606                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
607                 OMAP_HSMMC_WRITE(host->base, HCTL,
608                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
609                 break;
610         }
611 }
612
613 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
614 {
615         struct mmc_ios *ios = &host->mmc->ios;
616         u32 con;
617
618         con = OMAP_HSMMC_READ(host->base, CON);
619         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
620                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
621         else
622                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
623 }
624
625 #ifdef CONFIG_PM
626
627 /*
628  * Restore the MMC host context, if it was lost as result of a
629  * power state change.
630  */
631 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
632 {
633         struct mmc_ios *ios = &host->mmc->ios;
634         struct omap_mmc_platform_data *pdata = host->pdata;
635         int context_loss = 0;
636         u32 hctl, capa;
637         unsigned long timeout;
638
639         if (pdata->get_context_loss_count) {
640                 context_loss = pdata->get_context_loss_count(host->dev);
641                 if (context_loss < 0)
642                         return 1;
643         }
644
645         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
646                 context_loss == host->context_loss ? "not " : "");
647         if (host->context_loss == context_loss)
648                 return 1;
649
650         if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE)
651                 return 1;
652
653         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
654                 if (host->power_mode != MMC_POWER_OFF &&
655                     (1 << ios->vdd) <= MMC_VDD_23_24)
656                         hctl = SDVS18;
657                 else
658                         hctl = SDVS30;
659                 capa = VS30 | VS18;
660         } else {
661                 hctl = SDVS18;
662                 capa = VS18;
663         }
664
665         OMAP_HSMMC_WRITE(host->base, HCTL,
666                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
667
668         OMAP_HSMMC_WRITE(host->base, CAPA,
669                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
670
671         OMAP_HSMMC_WRITE(host->base, HCTL,
672                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
673
674         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
675         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
676                 && time_before(jiffies, timeout))
677                 ;
678
679         omap_hsmmc_enable_irq(host, NULL);
680
681         /* Do not initialize card-specific things if the power is off */
682         if (host->power_mode == MMC_POWER_OFF)
683                 goto out;
684
685         omap_hsmmc_set_bus_width(host);
686
687         omap_hsmmc_set_clock(host);
688
689         omap_hsmmc_set_bus_mode(host);
690
691 out:
692         host->context_loss = context_loss;
693
694         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
695         return 0;
696 }
697
698 /*
699  * Save the MMC host context (store the number of power state changes so far).
700  */
701 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
702 {
703         struct omap_mmc_platform_data *pdata = host->pdata;
704         int context_loss;
705
706         if (pdata->get_context_loss_count) {
707                 context_loss = pdata->get_context_loss_count(host->dev);
708                 if (context_loss < 0)
709                         return;
710                 host->context_loss = context_loss;
711         }
712 }
713
714 #else
715
716 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
717 {
718         return 0;
719 }
720
721 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
722 {
723 }
724
725 #endif
726
727 /*
728  * Send init stream sequence to card
729  * before sending IDLE command
730  */
731 static void send_init_stream(struct omap_hsmmc_host *host)
732 {
733         int reg = 0;
734         unsigned long timeout;
735
736         if (host->protect_card)
737                 return;
738         disable_irq(host->irq);
739
740         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK | CIRQ_EN);
741         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK | CIRQ_EN);
742         OMAP_HSMMC_WRITE(host->base, CON,
743                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
744         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
745
746         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
747         while ((reg != CC_EN) && time_before(jiffies, timeout))
748                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
749
750         OMAP_HSMMC_WRITE(host->base, CON,
751                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
752
753         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
754         OMAP_HSMMC_READ(host->base, STAT);
755
756         enable_irq(host->irq);
757 }
758
759 static inline
760 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
761 {
762         int r = 1;
763
764         if (mmc_slot(host).get_cover_state)
765                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
766         return r;
767 }
768
769 static ssize_t
770 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
771                            char *buf)
772 {
773         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
774         struct omap_hsmmc_host *host = mmc_priv(mmc);
775
776         return sprintf(buf, "%s\n",
777                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
778 }
779
780 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
781
782 static ssize_t
783 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
784                         char *buf)
785 {
786         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
787         struct omap_hsmmc_host *host = mmc_priv(mmc);
788
789         return sprintf(buf, "%s\n", mmc_slot(host).name);
790 }
791
792 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
793
794 /*
795  * Configure the response type and send the cmd.
796  */
797 static void
798 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
799         struct mmc_data *data)
800 {
801         int cmdreg = 0, resptype = 0, cmdtype = 0;
802
803         dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
804                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
805         host->cmd = cmd;
806
807         omap_hsmmc_enable_irq(host, cmd);
808
809         host->response_busy = 0;
810         if (cmd->flags & MMC_RSP_PRESENT) {
811                 if (cmd->flags & MMC_RSP_136)
812                         resptype = 1;
813                 else if (cmd->flags & MMC_RSP_BUSY) {
814                         resptype = 3;
815                         host->response_busy = 1;
816                 } else
817                         resptype = 2;
818         }
819
820         /*
821          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
822          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
823          * a val of 0x3, rest 0x0.
824          */
825         if (cmd == host->mrq->stop)
826                 cmdtype = 0x3;
827
828         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
829
830         if (data) {
831                 cmdreg |= DP_SELECT | MSBS | BCE;
832                 if (data->flags & MMC_DATA_READ)
833                         cmdreg |= DDIR;
834                 else
835                         cmdreg &= ~(DDIR);
836         }
837
838         if (host->use_dma)
839                 cmdreg |= DMAE;
840
841         host->req_in_progress = 1;
842
843         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
844         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
845 }
846
847 static int
848 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
849 {
850         if (data->flags & MMC_DATA_WRITE)
851                 return DMA_TO_DEVICE;
852         else
853                 return DMA_FROM_DEVICE;
854 }
855
856 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
857         struct mmc_data *data)
858 {
859         return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
860 }
861
862 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
863 {
864         int dma_ch;
865         unsigned long flags;
866
867         spin_lock_irqsave(&host->irq_lock, flags);
868         host->req_in_progress = 0;
869         dma_ch = host->dma_ch;
870         spin_unlock_irqrestore(&host->irq_lock, flags);
871
872         omap_hsmmc_disable_irq(host);
873         /* Do not complete the request if DMA is still in progress */
874         if (mrq->data && host->use_dma && dma_ch != -1)
875                 return;
876         host->mrq = NULL;
877         mmc_request_done(host->mmc, mrq);
878 }
879
880 /*
881  * Notify the transfer complete to MMC core
882  */
883 static void
884 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
885 {
886         if (!data) {
887                 struct mmc_request *mrq = host->mrq;
888
889                 /* TC before CC from CMD6 - don't know why, but it happens */
890                 if (host->cmd && host->cmd->opcode == 6 &&
891                     host->response_busy) {
892                         host->response_busy = 0;
893                         return;
894                 }
895
896                 omap_hsmmc_request_done(host, mrq);
897                 return;
898         }
899
900         host->data = NULL;
901
902         if (!data->error)
903                 data->bytes_xfered += data->blocks * (data->blksz);
904         else
905                 data->bytes_xfered = 0;
906
907         if (!data->stop) {
908                 omap_hsmmc_request_done(host, data->mrq);
909                 return;
910         }
911         omap_hsmmc_start_command(host, data->stop, NULL);
912 }
913
914 /*
915  * Notify the core about command completion
916  */
917 static void
918 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
919 {
920         host->cmd = NULL;
921
922         if (cmd->flags & MMC_RSP_PRESENT) {
923                 if (cmd->flags & MMC_RSP_136) {
924                         /* response type 2 */
925                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
926                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
927                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
928                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
929                 } else {
930                         /* response types 1, 1b, 3, 4, 5, 6 */
931                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
932                 }
933         }
934         if ((host->data == NULL && !host->response_busy) || cmd->error)
935                 omap_hsmmc_request_done(host, cmd->mrq);
936 }
937
938 /*
939  * DMA clean up for command errors
940  */
941 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
942 {
943         int dma_ch;
944         unsigned long flags;
945
946         host->data->error = errno;
947
948         spin_lock_irqsave(&host->irq_lock, flags);
949         dma_ch = host->dma_ch;
950         host->dma_ch = -1;
951         spin_unlock_irqrestore(&host->irq_lock, flags);
952
953         if (host->use_dma && dma_ch != -1) {
954                 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
955
956                 dmaengine_terminate_all(chan);
957                 dma_unmap_sg(chan->device->dev,
958                         host->data->sg, host->data->sg_len,
959                         omap_hsmmc_get_dma_dir(host, host->data));
960
961                 host->data->host_cookie = 0;
962         }
963         host->data = NULL;
964 }
965
966 /*
967  * Readable error output
968  */
969 #ifdef CONFIG_MMC_DEBUG
970 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
971 {
972         /* --- means reserved bit without definition at documentation */
973         static const char *omap_hsmmc_status_bits[] = {
974                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
975                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
976                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
977                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
978         };
979         char res[256];
980         char *buf = res;
981         int len, i;
982
983         len = sprintf(buf, "MMC IRQ 0x%x :", status);
984         buf += len;
985
986         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
987                 if (status & (1 << i)) {
988                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
989                         buf += len;
990                 }
991
992         dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
993 }
994 #else
995 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
996                                              u32 status)
997 {
998 }
999 #endif  /* CONFIG_MMC_DEBUG */
1000
1001 /*
1002  * MMC controller internal state machines reset
1003  *
1004  * Used to reset command or data internal state machines, using respectively
1005  *  SRC or SRD bit of SYSCTL register
1006  * Can be called from interrupt context
1007  */
1008 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1009                                                    unsigned long bit)
1010 {
1011         unsigned long i = 0;
1012         unsigned long limit = (loops_per_jiffy *
1013                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
1014
1015         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1016                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1017
1018         /*
1019          * OMAP4 ES2 and greater has an updated reset logic.
1020          * Monitor a 0->1 transition first
1021          */
1022         if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1023                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1024                                         && (i++ < limit))
1025                         cpu_relax();
1026         }
1027         i = 0;
1028
1029         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1030                 (i++ < limit))
1031                 cpu_relax();
1032
1033         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1034                 dev_err(mmc_dev(host->mmc),
1035                         "Timeout waiting on controller reset in %s\n",
1036                         __func__);
1037 }
1038
1039 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1040                                         int err, int end_cmd)
1041 {
1042         if (end_cmd) {
1043                 omap_hsmmc_reset_controller_fsm(host, SRC);
1044                 if (host->cmd)
1045                         host->cmd->error = err;
1046         }
1047
1048         if (host->data) {
1049                 omap_hsmmc_reset_controller_fsm(host, SRD);
1050                 omap_hsmmc_dma_cleanup(host, err);
1051         } else if (host->mrq && host->mrq->cmd)
1052                 host->mrq->cmd->error = err;
1053 }
1054
1055 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1056 {
1057         struct mmc_data *data;
1058         int end_cmd = 0, end_trans = 0;
1059
1060         data = host->data;
1061         dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1062
1063         if (status & CIRQ_EN &&
1064             host->mmc->caps & MMC_CAP_SDIO_IRQ &&
1065             host->sdio_int) {
1066                 dev_dbg(mmc_dev(host->mmc), "SDIO Card Interrupt\n");
1067                 mmc_signal_sdio_irq(host->mmc);
1068         }
1069
1070         if (status & ERR_EN) {
1071                 omap_hsmmc_dbg_report_irq(host, status);
1072
1073                 if (status & (CTO_EN | CCRC_EN))
1074                         end_cmd = 1;
1075                 if (status & (CTO_EN | DTO_EN))
1076                         hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1077                 else if (status & (CCRC_EN | DCRC_EN))
1078                         hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1079
1080                 if (host->data || host->response_busy) {
1081                         end_trans = !end_cmd;
1082                         host->response_busy = 0;
1083                 }
1084         }
1085
1086         OMAP_HSMMC_WRITE(host->base, STAT, status);
1087         if (end_cmd || ((status & CC_EN) && host->cmd))
1088                 omap_hsmmc_cmd_done(host, host->cmd);
1089         if ((end_trans || (status & TC_EN)) && host->mrq)
1090                 omap_hsmmc_xfer_done(host, data);
1091 }
1092
1093 /*
1094  * MMC controller IRQ handler
1095  */
1096 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1097 {
1098         struct omap_hsmmc_host *host = dev_id;
1099         int status;
1100
1101         pm_runtime_get_sync(host->dev);
1102         while (1) {
1103                 unsigned int irqm = INT_EN_MASK;
1104
1105                 if (host->sdio_int)
1106                         irqm |= CIRQ_EN;
1107
1108                 status = OMAP_HSMMC_READ(host->base, STAT);
1109                 if (status & irqm)
1110                         omap_hsmmc_do_irq(host, status);
1111                 else
1112                         break;
1113                 OMAP_HSMMC_WRITE(host->base, STAT, status);
1114         }
1115         pm_runtime_put(host->dev);
1116
1117         return IRQ_HANDLED;
1118 }
1119
1120 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1121 {
1122         unsigned long i;
1123
1124         OMAP_HSMMC_WRITE(host->base, HCTL,
1125                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1126         for (i = 0; i < loops_per_jiffy; i++) {
1127                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1128                         break;
1129                 cpu_relax();
1130         }
1131 }
1132
1133 /*
1134  * Switch MMC interface voltage ... only relevant for MMC1.
1135  *
1136  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1137  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1138  * Some chips, like eMMC ones, use internal transceivers.
1139  */
1140 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1141 {
1142         u32 reg_val = 0;
1143         int ret;
1144
1145         /* Disable the clocks */
1146         pm_runtime_put_sync(host->dev);
1147         if (host->dbclk)
1148                 clk_disable_unprepare(host->dbclk);
1149
1150         /* Turn the power off */
1151         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1152
1153         /* Turn the power ON with given VDD 1.8 or 3.0v */
1154         if (!ret)
1155                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1156                                                vdd);
1157         pm_runtime_get_sync(host->dev);
1158         if (host->dbclk)
1159                 clk_prepare_enable(host->dbclk);
1160
1161         if (ret != 0)
1162                 goto err;
1163
1164         OMAP_HSMMC_WRITE(host->base, HCTL,
1165                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1166         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1167
1168         /*
1169          * If a MMC dual voltage card is detected, the set_ios fn calls
1170          * this fn with VDD bit set for 1.8V. Upon card removal from the
1171          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1172          *
1173          * Cope with a bit of slop in the range ... per data sheets:
1174          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1175          *    but recommended values are 1.71V to 1.89V
1176          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1177          *    but recommended values are 2.7V to 3.3V
1178          *
1179          * Board setup code shouldn't permit anything very out-of-range.
1180          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1181          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1182          */
1183         if ((1 << vdd) <= MMC_VDD_23_24)
1184                 reg_val |= SDVS18;
1185         else
1186                 reg_val |= SDVS30;
1187
1188         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1189         set_sd_bus_power(host);
1190
1191         return 0;
1192 err:
1193         dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1194         return ret;
1195 }
1196
1197 /* Protect the card while the cover is open */
1198 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1199 {
1200         if (!mmc_slot(host).get_cover_state)
1201                 return;
1202
1203         host->reqs_blocked = 0;
1204         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1205                 if (host->protect_card) {
1206                         dev_info(host->dev, "%s: cover is closed, "
1207                                          "card is now accessible\n",
1208                                          mmc_hostname(host->mmc));
1209                         host->protect_card = 0;
1210                 }
1211         } else {
1212                 if (!host->protect_card) {
1213                         dev_info(host->dev, "%s: cover is open, "
1214                                          "card is now inaccessible\n",
1215                                          mmc_hostname(host->mmc));
1216                         host->protect_card = 1;
1217                 }
1218         }
1219 }
1220
1221 /*
1222  * irq handler to notify the core about card insertion/removal
1223  */
1224 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1225 {
1226         struct omap_hsmmc_host *host = dev_id;
1227         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1228         int carddetect;
1229
1230         if (host->suspended)
1231                 return IRQ_HANDLED;
1232
1233         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1234
1235         if (slot->card_detect)
1236                 carddetect = slot->card_detect(host->dev, host->slot_id);
1237         else {
1238                 omap_hsmmc_protect_card(host);
1239                 carddetect = -ENOSYS;
1240         }
1241
1242         if (carddetect)
1243                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1244         else
1245                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1246         return IRQ_HANDLED;
1247 }
1248
1249 static void omap_hsmmc_dma_callback(void *param)
1250 {
1251         struct omap_hsmmc_host *host = param;
1252         struct dma_chan *chan;
1253         struct mmc_data *data;
1254         int req_in_progress;
1255
1256         spin_lock_irq(&host->irq_lock);
1257         if (host->dma_ch < 0) {
1258                 spin_unlock_irq(&host->irq_lock);
1259                 return;
1260         }
1261
1262         data = host->mrq->data;
1263         chan = omap_hsmmc_get_dma_chan(host, data);
1264         if (!data->host_cookie)
1265                 dma_unmap_sg(chan->device->dev,
1266                              data->sg, data->sg_len,
1267                              omap_hsmmc_get_dma_dir(host, data));
1268
1269         req_in_progress = host->req_in_progress;
1270         host->dma_ch = -1;
1271         spin_unlock_irq(&host->irq_lock);
1272
1273         /* If DMA has finished after TC, complete the request */
1274         if (!req_in_progress) {
1275                 struct mmc_request *mrq = host->mrq;
1276
1277                 host->mrq = NULL;
1278                 mmc_request_done(host->mmc, mrq);
1279         }
1280 }
1281
1282 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1283                                        struct mmc_data *data,
1284                                        struct omap_hsmmc_next *next,
1285                                        struct dma_chan *chan)
1286 {
1287         int dma_len;
1288
1289         if (!next && data->host_cookie &&
1290             data->host_cookie != host->next_data.cookie) {
1291                 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1292                        " host->next_data.cookie %d\n",
1293                        __func__, data->host_cookie, host->next_data.cookie);
1294                 data->host_cookie = 0;
1295         }
1296
1297         /* Check if next job is already prepared */
1298         if (next ||
1299             (!next && data->host_cookie != host->next_data.cookie)) {
1300                 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1301                                      omap_hsmmc_get_dma_dir(host, data));
1302
1303         } else {
1304                 dma_len = host->next_data.dma_len;
1305                 host->next_data.dma_len = 0;
1306         }
1307
1308
1309         if (dma_len == 0)
1310                 return -EINVAL;
1311
1312         if (next) {
1313                 next->dma_len = dma_len;
1314                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1315         } else
1316                 host->dma_len = dma_len;
1317
1318         return 0;
1319 }
1320
1321 /*
1322  * Routine to configure and start DMA for the MMC card
1323  */
1324 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1325                                         struct mmc_request *req)
1326 {
1327         struct dma_slave_config cfg;
1328         struct dma_async_tx_descriptor *tx;
1329         int ret = 0, i;
1330         struct mmc_data *data = req->data;
1331         struct dma_chan *chan;
1332
1333         /* Sanity check: all the SG entries must be aligned by block size. */
1334         for (i = 0; i < data->sg_len; i++) {
1335                 struct scatterlist *sgl;
1336
1337                 sgl = data->sg + i;
1338                 if (sgl->length % data->blksz)
1339                         return -EINVAL;
1340         }
1341         if ((data->blksz % 4) != 0)
1342                 /* REVISIT: The MMC buffer increments only when MSB is written.
1343                  * Return error for blksz which is non multiple of four.
1344                  */
1345                 return -EINVAL;
1346
1347         BUG_ON(host->dma_ch != -1);
1348
1349         chan = omap_hsmmc_get_dma_chan(host, data);
1350
1351         cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1352         cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1353         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1354         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1355         cfg.src_maxburst = data->blksz / 4;
1356         cfg.dst_maxburst = data->blksz / 4;
1357
1358         ret = dmaengine_slave_config(chan, &cfg);
1359         if (ret)
1360                 return ret;
1361
1362         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1363         if (ret)
1364                 return ret;
1365
1366         tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1367                 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1368                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1369         if (!tx) {
1370                 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1371                 /* FIXME: cleanup */
1372                 return -1;
1373         }
1374
1375         tx->callback = omap_hsmmc_dma_callback;
1376         tx->callback_param = host;
1377
1378         /* Does not fail */
1379         dmaengine_submit(tx);
1380
1381         host->dma_ch = 1;
1382
1383         dma_async_issue_pending(chan);
1384
1385         return 0;
1386 }
1387
1388 static void set_data_timeout(struct omap_hsmmc_host *host,
1389                              unsigned int timeout_ns,
1390                              unsigned int timeout_clks)
1391 {
1392         unsigned int timeout, cycle_ns;
1393         uint32_t reg, clkd, dto = 0;
1394
1395         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1396         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1397         if (clkd == 0)
1398                 clkd = 1;
1399
1400         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1401         timeout = timeout_ns / cycle_ns;
1402         timeout += timeout_clks;
1403         if (timeout) {
1404                 while ((timeout & 0x80000000) == 0) {
1405                         dto += 1;
1406                         timeout <<= 1;
1407                 }
1408                 dto = 31 - dto;
1409                 timeout <<= 1;
1410                 if (timeout && dto)
1411                         dto += 1;
1412                 if (dto >= 13)
1413                         dto -= 13;
1414                 else
1415                         dto = 0;
1416                 if (dto > 14)
1417                         dto = 14;
1418         }
1419
1420         reg &= ~DTO_MASK;
1421         reg |= dto << DTO_SHIFT;
1422         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1423 }
1424
1425 /*
1426  * Configure block length for MMC/SD cards and initiate the transfer.
1427  */
1428 static int
1429 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1430 {
1431         int ret;
1432         host->data = req->data;
1433
1434         if (req->data == NULL) {
1435                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1436                 /*
1437                  * Set an arbitrary 100ms data timeout for commands with
1438                  * busy signal.
1439                  */
1440                 if (req->cmd->flags & MMC_RSP_BUSY)
1441                         set_data_timeout(host, 100000000U, 0);
1442                 return 0;
1443         }
1444
1445         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1446                                         | (req->data->blocks << 16));
1447         set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1448
1449         if (host->use_dma) {
1450                 ret = omap_hsmmc_start_dma_transfer(host, req);
1451                 if (ret != 0) {
1452                         dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1453                         return ret;
1454                 }
1455         }
1456         return 0;
1457 }
1458
1459 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1460                                 int err)
1461 {
1462         struct omap_hsmmc_host *host = mmc_priv(mmc);
1463         struct mmc_data *data = mrq->data;
1464
1465         if (host->use_dma && data->host_cookie) {
1466                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1467
1468                 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1469                              omap_hsmmc_get_dma_dir(host, data));
1470                 data->host_cookie = 0;
1471         }
1472 }
1473
1474 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1475                                bool is_first_req)
1476 {
1477         struct omap_hsmmc_host *host = mmc_priv(mmc);
1478
1479         if (mrq->data->host_cookie) {
1480                 mrq->data->host_cookie = 0;
1481                 return ;
1482         }
1483
1484         if (host->use_dma) {
1485                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1486
1487                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1488                                                 &host->next_data, c))
1489                         mrq->data->host_cookie = 0;
1490         }
1491 }
1492
1493 /*
1494  * Request function. for read/write operation
1495  */
1496 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1497 {
1498         struct omap_hsmmc_host *host = mmc_priv(mmc);
1499         int err;
1500
1501         BUG_ON(host->req_in_progress);
1502         BUG_ON(host->dma_ch != -1);
1503         if (host->protect_card) {
1504                 if (host->reqs_blocked < 3) {
1505                         /*
1506                          * Ensure the controller is left in a consistent
1507                          * state by resetting the command and data state
1508                          * machines.
1509                          */
1510                         omap_hsmmc_reset_controller_fsm(host, SRD);
1511                         omap_hsmmc_reset_controller_fsm(host, SRC);
1512                         host->reqs_blocked += 1;
1513                 }
1514                 req->cmd->error = -EBADF;
1515                 if (req->data)
1516                         req->data->error = -EBADF;
1517                 req->cmd->retries = 0;
1518                 mmc_request_done(mmc, req);
1519                 return;
1520         } else if (host->reqs_blocked)
1521                 host->reqs_blocked = 0;
1522         WARN_ON(host->mrq != NULL);
1523         host->mrq = req;
1524         err = omap_hsmmc_prepare_data(host, req);
1525         if (err) {
1526                 req->cmd->error = err;
1527                 if (req->data)
1528                         req->data->error = err;
1529                 host->mrq = NULL;
1530                 mmc_request_done(mmc, req);
1531                 return;
1532         }
1533
1534         omap_hsmmc_start_command(host, req->cmd, req->data);
1535 }
1536
1537 /* Routine to configure clock values. Exposed API to core */
1538 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1539 {
1540         struct omap_hsmmc_host *host = mmc_priv(mmc);
1541         int do_send_init_stream = 0;
1542
1543         pm_runtime_get_sync(host->dev);
1544
1545         if (ios->power_mode != host->power_mode) {
1546                 switch (ios->power_mode) {
1547                 case MMC_POWER_OFF:
1548                         mmc_slot(host).set_power(host->dev, host->slot_id,
1549                                                  0, 0);
1550                         break;
1551                 case MMC_POWER_UP:
1552                         mmc_slot(host).set_power(host->dev, host->slot_id,
1553                                                  1, ios->vdd);
1554                         break;
1555                 case MMC_POWER_ON:
1556                         do_send_init_stream = 1;
1557                         break;
1558                 }
1559                 host->power_mode = ios->power_mode;
1560         }
1561
1562         /* FIXME: set registers based only on changes to ios */
1563
1564         omap_hsmmc_set_bus_width(host);
1565
1566         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1567                 /* Only MMC1 can interface at 3V without some flavor
1568                  * of external transceiver; but they all handle 1.8V.
1569                  */
1570                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1571                         (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1572                         /*
1573                          * With pbias cell programming missing, this
1574                          * can't be allowed on MMC1 when booting with device
1575                          * tree.
1576                          */
1577                         !host->pbias_disable) {
1578                                 /*
1579                                  * The mmc_select_voltage fn of the core does
1580                                  * not seem to set the power_mode to
1581                                  * MMC_POWER_UP upon recalculating the voltage.
1582                                  * vdd 1.8v.
1583                                  */
1584                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1585                                 dev_dbg(mmc_dev(host->mmc),
1586                                                 "Switch operation failed\n");
1587                 }
1588         }
1589
1590         omap_hsmmc_set_clock(host);
1591
1592         if (do_send_init_stream)
1593                 send_init_stream(host);
1594
1595         omap_hsmmc_set_bus_mode(host);
1596
1597         pm_runtime_put_autosuspend(host->dev);
1598 }
1599
1600 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1601 {
1602         struct omap_hsmmc_host *host = mmc_priv(mmc);
1603
1604         if (!mmc_slot(host).card_detect)
1605                 return -ENOSYS;
1606         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1607 }
1608
1609 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1610 {
1611         struct omap_hsmmc_host *host = mmc_priv(mmc);
1612
1613         if (!mmc_slot(host).get_ro)
1614                 return -ENOSYS;
1615         return mmc_slot(host).get_ro(host->dev, 0);
1616 }
1617
1618 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1619 {
1620         struct omap_hsmmc_host *host = mmc_priv(mmc);
1621
1622         if (mmc_slot(host).init_card)
1623                 mmc_slot(host).init_card(card);
1624 }
1625
1626 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1627 {
1628         struct omap_hsmmc_host *host = mmc_priv(mmc);
1629         unsigned long flags;
1630
1631         spin_lock_irqsave(&host->irq_lock, flags);
1632         host->sdio_int = enable;
1633         if (enable) {
1634                 OMAP_HSMMC_WRITE(host->base, ISE,
1635                         (OMAP_HSMMC_READ(host->base, ISE) | CIRQ_EN));
1636                 OMAP_HSMMC_WRITE(host->base, IE,
1637                         (OMAP_HSMMC_READ(host->base, IE) | CIRQ_EN));
1638         } else {
1639                 OMAP_HSMMC_WRITE(host->base, IE,
1640                         (OMAP_HSMMC_READ(host->base, IE) & (~CIRQ_EN)));
1641                 OMAP_HSMMC_WRITE(host->base, ISE,
1642                         (OMAP_HSMMC_READ(host->base, ISE) & (~CIRQ_EN)));
1643         }
1644         spin_unlock_irqrestore(&host->irq_lock, flags);
1645
1646 }
1647
1648 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1649 {
1650         u32 hctl, capa, value;
1651
1652         /* Only MMC1 supports 3.0V */
1653         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1654                 hctl = SDVS30;
1655                 capa = VS30 | VS18;
1656         } else {
1657                 hctl = SDVS18;
1658                 capa = VS18;
1659         }
1660
1661         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1662         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1663
1664         value = OMAP_HSMMC_READ(host->base, CAPA);
1665         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1666
1667         /* Set SD bus power bit */
1668         set_sd_bus_power(host);
1669 }
1670
1671 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1672 {
1673         struct omap_hsmmc_host *host = mmc_priv(mmc);
1674
1675         pm_runtime_get_sync(host->dev);
1676
1677         return 0;
1678 }
1679
1680 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1681 {
1682         struct omap_hsmmc_host *host = mmc_priv(mmc);
1683
1684         if (mmc->sdio_irqs && !host->irq_requested) {
1685                 /* Skip one 'disable' while irq is requested */
1686                 host->irq_requested = 1;
1687                 return 0;
1688         }
1689         if (!mmc->sdio_irqs && host->irq_requested) {
1690                 /* irqs no longer requested, so can drop the
1691                  * ref
1692                  */
1693                 pm_runtime_put_noidle(host->dev);
1694                 host->irq_requested = 0;
1695         }
1696
1697         pm_runtime_mark_last_busy(host->dev);
1698         pm_runtime_put_autosuspend(host->dev);
1699
1700         return 0;
1701 }
1702
1703 static const struct mmc_host_ops omap_hsmmc_ops = {
1704         .enable = omap_hsmmc_enable_fclk,
1705         .disable = omap_hsmmc_disable_fclk,
1706         .post_req = omap_hsmmc_post_req,
1707         .pre_req = omap_hsmmc_pre_req,
1708         .request = omap_hsmmc_request,
1709         .set_ios = omap_hsmmc_set_ios,
1710         .get_cd = omap_hsmmc_get_cd,
1711         .get_ro = omap_hsmmc_get_ro,
1712         .init_card = omap_hsmmc_init_card,
1713         .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1714 };
1715
1716 #ifdef CONFIG_DEBUG_FS
1717
1718 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1719 {
1720         struct mmc_host *mmc = s->private;
1721         struct omap_hsmmc_host *host = mmc_priv(mmc);
1722         int context_loss = 0;
1723
1724         if (host->pdata->get_context_loss_count)
1725                 context_loss = host->pdata->get_context_loss_count(host->dev);
1726
1727         seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1728                         mmc->index, host->context_loss, context_loss);
1729
1730         if (host->suspended) {
1731                 seq_printf(s, "host suspended, can't read registers\n");
1732                 return 0;
1733         }
1734
1735         pm_runtime_get_sync(host->dev);
1736
1737         seq_printf(s, "CON:\t\t0x%08x\n",
1738                         OMAP_HSMMC_READ(host->base, CON));
1739         seq_printf(s, "HCTL:\t\t0x%08x\n",
1740                         OMAP_HSMMC_READ(host->base, HCTL));
1741         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1742                         OMAP_HSMMC_READ(host->base, SYSCTL));
1743         seq_printf(s, "IE:\t\t0x%08x\n",
1744                         OMAP_HSMMC_READ(host->base, IE));
1745         seq_printf(s, "ISE:\t\t0x%08x\n",
1746                         OMAP_HSMMC_READ(host->base, ISE));
1747         seq_printf(s, "CAPA:\t\t0x%08x\n",
1748                         OMAP_HSMMC_READ(host->base, CAPA));
1749
1750         pm_runtime_mark_last_busy(host->dev);
1751         pm_runtime_put_autosuspend(host->dev);
1752
1753         return 0;
1754 }
1755
1756 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1757 {
1758         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1759 }
1760
1761 static const struct file_operations mmc_regs_fops = {
1762         .open           = omap_hsmmc_regs_open,
1763         .read           = seq_read,
1764         .llseek         = seq_lseek,
1765         .release        = single_release,
1766 };
1767
1768 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1769 {
1770         if (mmc->debugfs_root)
1771                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1772                         mmc, &mmc_regs_fops);
1773 }
1774
1775 #else
1776
1777 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1778 {
1779 }
1780
1781 #endif
1782
1783 #ifdef CONFIG_OF
1784 static u16 omap4_reg_offset = 0x100;
1785
1786 static const struct of_device_id omap_mmc_of_match[] = {
1787         {
1788                 .compatible = "ti,omap2-hsmmc",
1789         },
1790         {
1791                 .compatible = "ti,omap3-hsmmc",
1792         },
1793         {
1794                 .compatible = "ti,omap4-hsmmc",
1795                 .data = &omap4_reg_offset,
1796         },
1797         {},
1798 };
1799 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1800
1801 static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1802 {
1803         struct omap_mmc_platform_data *pdata;
1804         struct device_node *np = dev->of_node;
1805         u32 bus_width, max_freq;
1806         int cd_gpio, wp_gpio, reset_gpio;
1807
1808         cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
1809         wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1810         reset_gpio = of_get_named_gpio(np, "reset-gpios", 0);
1811         if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER)
1812                 return ERR_PTR(-EPROBE_DEFER);
1813
1814         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1815         if (!pdata)
1816                 return NULL; /* out of memory */
1817
1818         if (of_find_property(np, "ti,dual-volt", NULL))
1819                 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1820
1821         /* This driver only supports 1 slot */
1822         pdata->nr_slots = 1;
1823         pdata->slots[0].switch_pin = cd_gpio;
1824         pdata->slots[0].gpio_wp = wp_gpio;
1825         pdata->slots[0].gpio_reset = reset_gpio;
1826
1827         if (of_find_property(np, "ti,non-removable", NULL)) {
1828                 pdata->slots[0].nonremovable = true;
1829                 pdata->slots[0].no_regulator_off_init = true;
1830         }
1831         of_property_read_u32(np, "bus-width", &bus_width);
1832         if (bus_width == 4)
1833                 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1834         else if (bus_width == 8)
1835                 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1836
1837         if (of_find_property(np, "ti,needs-special-reset", NULL))
1838                 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1839
1840         if (!of_property_read_u32(np, "max-frequency", &max_freq))
1841                 pdata->max_freq = max_freq;
1842
1843         if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1844                 pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT;
1845
1846         return pdata;
1847 }
1848 #else
1849 static inline struct omap_mmc_platform_data
1850                         *of_get_hsmmc_pdata(struct device *dev)
1851 {
1852         return NULL;
1853 }
1854 #endif
1855
1856 static int omap_hsmmc_probe(struct platform_device *pdev)
1857 {
1858         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1859         struct mmc_host *mmc;
1860         struct omap_hsmmc_host *host = NULL;
1861         struct resource *res;
1862         int ret, irq;
1863         const struct of_device_id *match;
1864         dma_cap_mask_t mask;
1865         unsigned tx_req, rx_req;
1866         struct pinctrl *pinctrl;
1867
1868         match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1869         if (match) {
1870                 pdata = of_get_hsmmc_pdata(&pdev->dev);
1871
1872                 if (IS_ERR(pdata))
1873                         return PTR_ERR(pdata);
1874
1875                 if (match->data) {
1876                         const u16 *offsetp = match->data;
1877                         pdata->reg_offset = *offsetp;
1878                 }
1879         }
1880
1881         if (pdata == NULL) {
1882                 dev_err(&pdev->dev, "Platform Data is missing\n");
1883                 return -ENXIO;
1884         }
1885
1886         if (pdata->nr_slots == 0) {
1887                 dev_err(&pdev->dev, "No Slots\n");
1888                 return -ENXIO;
1889         }
1890
1891         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1892         irq = platform_get_irq(pdev, 0);
1893         if (res == NULL || irq < 0)
1894                 return -ENXIO;
1895
1896         res = request_mem_region(res->start, resource_size(res), pdev->name);
1897         if (res == NULL)
1898                 return -EBUSY;
1899
1900         ret = omap_hsmmc_gpio_init(pdata);
1901         if (ret)
1902                 goto err;
1903
1904         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1905         if (!mmc) {
1906                 ret = -ENOMEM;
1907                 goto err_alloc;
1908         }
1909
1910         host            = mmc_priv(mmc);
1911         host->mmc       = mmc;
1912         host->pdata     = pdata;
1913         host->dev       = &pdev->dev;
1914         host->use_dma   = 1;
1915         host->dma_ch    = -1;
1916         host->irq       = irq;
1917         host->slot_id   = 0;
1918         host->mapbase   = res->start + pdata->reg_offset;
1919         host->base      = ioremap(host->mapbase, SZ_4K);
1920         host->power_mode = MMC_POWER_OFF;
1921         host->sdio_int  = 0;
1922         host->next_data.cookie = 1;
1923
1924         platform_set_drvdata(pdev, host);
1925
1926         mmc->ops        = &omap_hsmmc_ops;
1927
1928         /*
1929          * If regulator_disable can only put vcc_aux to sleep then there is
1930          * no off state.
1931          */
1932         if (mmc_slot(host).vcc_aux_disable_is_sleep)
1933                 mmc_slot(host).no_off = 1;
1934
1935         mmc->f_min = OMAP_MMC_MIN_CLOCK;
1936
1937         if (pdata->max_freq > 0)
1938                 mmc->f_max = pdata->max_freq;
1939         else
1940                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1941
1942         spin_lock_init(&host->irq_lock);
1943
1944         host->fclk = clk_get(&pdev->dev, "fck");
1945         if (IS_ERR(host->fclk)) {
1946                 ret = PTR_ERR(host->fclk);
1947                 host->fclk = NULL;
1948                 goto err1;
1949         }
1950
1951         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1952                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1953                 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1954         }
1955
1956         pm_runtime_enable(host->dev);
1957         pm_runtime_get_sync(host->dev);
1958         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1959         pm_runtime_use_autosuspend(host->dev);
1960
1961         omap_hsmmc_context_save(host);
1962
1963         /* This can be removed once we support PBIAS with DT */
1964         if (host->dev->of_node && host->mapbase == 0x4809c000)
1965                 host->pbias_disable = 1;
1966
1967         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1968         /*
1969          * MMC can still work without debounce clock.
1970          */
1971         if (IS_ERR(host->dbclk)) {
1972                 host->dbclk = NULL;
1973         } else if (clk_prepare_enable(host->dbclk) != 0) {
1974                 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1975                 clk_put(host->dbclk);
1976                 host->dbclk = NULL;
1977         }
1978
1979         /* Since we do only SG emulation, we can have as many segs
1980          * as we want. */
1981         mmc->max_segs = 1024;
1982
1983         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1984         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1985         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1986         mmc->max_seg_size = mmc->max_req_size;
1987
1988         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1989                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1990
1991         mmc->caps |= mmc_slot(host).caps;
1992         if (mmc->caps & MMC_CAP_8_BIT_DATA)
1993                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1994
1995         if (mmc_slot(host).nonremovable)
1996                 mmc->caps |= MMC_CAP_NONREMOVABLE;
1997
1998         mmc->caps |= MMC_CAP_SDIO_IRQ;
1999         OMAP_HSMMC_WRITE(host->base, CON,
2000                         OMAP_HSMMC_READ(host->base, CON) | (CTPL | CLKEXTFREE));
2001
2002         mmc->pm_caps = mmc_slot(host).pm_caps;
2003
2004         omap_hsmmc_conf_bus_power(host);
2005
2006         if (!pdev->dev.of_node) {
2007                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
2008                 if (!res) {
2009                         dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
2010                         ret = -ENXIO;
2011                         goto err_irq;
2012                 }
2013                 tx_req = res->start;
2014
2015                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
2016                 if (!res) {
2017                         dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
2018                         ret = -ENXIO;
2019                         goto err_irq;
2020                 }
2021                 rx_req = res->start;
2022         }
2023
2024         dma_cap_zero(mask);
2025         dma_cap_set(DMA_SLAVE, mask);
2026
2027         host->rx_chan =
2028                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2029                                                  &rx_req, &pdev->dev, "rx");
2030
2031         if (!host->rx_chan) {
2032                 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
2033                 ret = -ENXIO;
2034                 goto err_irq;
2035         }
2036
2037         host->tx_chan =
2038                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2039                                                  &tx_req, &pdev->dev, "tx");
2040
2041         if (!host->tx_chan) {
2042                 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
2043                 ret = -ENXIO;
2044                 goto err_irq;
2045         }
2046
2047         /* Request IRQ for MMC operations */
2048         ret = request_irq(host->irq, omap_hsmmc_irq, 0,
2049                         mmc_hostname(mmc), host);
2050         if (ret) {
2051                 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2052                 goto err_irq;
2053         }
2054
2055         if (pdata->init != NULL) {
2056                 if (pdata->init(&pdev->dev) != 0) {
2057                         dev_err(mmc_dev(host->mmc),
2058                                 "Unable to configure MMC IRQs\n");
2059                         goto err_irq_cd_init;
2060                 }
2061         }
2062
2063         if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2064                 ret = omap_hsmmc_reg_get(host);
2065                 if (ret)
2066                         goto err_reg;
2067                 host->use_reg = 1;
2068         }
2069
2070         mmc->ocr_avail = mmc_slot(host).ocr_mask;
2071
2072         /* Request IRQ for card detect */
2073         if ((mmc_slot(host).card_detect_irq)) {
2074                 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
2075                                            NULL,
2076                                            omap_hsmmc_detect,
2077                                            IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2078                                            mmc_hostname(mmc), host);
2079                 if (ret) {
2080                         dev_err(mmc_dev(host->mmc),
2081                                 "Unable to grab MMC CD IRQ\n");
2082                         goto err_irq_cd;
2083                 }
2084                 pdata->suspend = omap_hsmmc_suspend_cdirq;
2085                 pdata->resume = omap_hsmmc_resume_cdirq;
2086         }
2087
2088         omap_hsmmc_disable_irq(host);
2089
2090         pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
2091         if (IS_ERR(pinctrl))
2092                 dev_warn(&pdev->dev,
2093                         "pins are not configured from the driver\n");
2094
2095         omap_hsmmc_protect_card(host);
2096
2097         mmc_add_host(mmc);
2098
2099         if (mmc_slot(host).name != NULL) {
2100                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2101                 if (ret < 0)
2102                         goto err_slot_name;
2103         }
2104         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2105                 ret = device_create_file(&mmc->class_dev,
2106                                         &dev_attr_cover_switch);
2107                 if (ret < 0)
2108                         goto err_slot_name;
2109         }
2110
2111         omap_hsmmc_debugfs(mmc);
2112         pm_runtime_mark_last_busy(host->dev);
2113         pm_runtime_put_autosuspend(host->dev);
2114
2115         return 0;
2116
2117 err_slot_name:
2118         mmc_remove_host(mmc);
2119         free_irq(mmc_slot(host).card_detect_irq, host);
2120 err_irq_cd:
2121         if (host->use_reg)
2122                 omap_hsmmc_reg_put(host);
2123 err_reg:
2124         if (host->pdata->cleanup)
2125                 host->pdata->cleanup(&pdev->dev);
2126 err_irq_cd_init:
2127         free_irq(host->irq, host);
2128 err_irq:
2129         if (host->tx_chan)
2130                 dma_release_channel(host->tx_chan);
2131         if (host->rx_chan)
2132                 dma_release_channel(host->rx_chan);
2133         pm_runtime_put_sync(host->dev);
2134         pm_runtime_disable(host->dev);
2135         clk_put(host->fclk);
2136         if (host->dbclk) {
2137                 clk_disable_unprepare(host->dbclk);
2138                 clk_put(host->dbclk);
2139         }
2140 err1:
2141         iounmap(host->base);
2142         mmc_free_host(mmc);
2143 err_alloc:
2144         omap_hsmmc_gpio_free(pdata);
2145 err:
2146         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2147         if (res)
2148                 release_mem_region(res->start, resource_size(res));
2149         return ret;
2150 }
2151
2152 static int omap_hsmmc_remove(struct platform_device *pdev)
2153 {
2154         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2155         struct resource *res;
2156
2157         pm_runtime_get_sync(host->dev);
2158         mmc_remove_host(host->mmc);
2159         if (host->use_reg)
2160                 omap_hsmmc_reg_put(host);
2161         if (host->pdata->cleanup)
2162                 host->pdata->cleanup(&pdev->dev);
2163         free_irq(host->irq, host);
2164         if (mmc_slot(host).card_detect_irq)
2165                 free_irq(mmc_slot(host).card_detect_irq, host);
2166
2167         if (host->tx_chan)
2168                 dma_release_channel(host->tx_chan);
2169         if (host->rx_chan)
2170                 dma_release_channel(host->rx_chan);
2171
2172         pm_runtime_put_sync(host->dev);
2173         pm_runtime_disable(host->dev);
2174         clk_put(host->fclk);
2175         if (host->dbclk) {
2176                 clk_disable_unprepare(host->dbclk);
2177                 clk_put(host->dbclk);
2178         }
2179
2180         omap_hsmmc_gpio_free(host->pdata);
2181         iounmap(host->base);
2182         mmc_free_host(host->mmc);
2183
2184         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2185         if (res)
2186                 release_mem_region(res->start, resource_size(res));
2187
2188         return 0;
2189 }
2190
2191 #ifdef CONFIG_PM
2192 static int omap_hsmmc_prepare(struct device *dev)
2193 {
2194         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2195
2196         if (host->pdata->suspend)
2197                 return host->pdata->suspend(dev, host->slot_id);
2198
2199         return 0;
2200 }
2201
2202 static void omap_hsmmc_complete(struct device *dev)
2203 {
2204         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2205
2206         if (host->pdata->resume)
2207                 host->pdata->resume(dev, host->slot_id);
2208
2209 }
2210
2211 static int omap_hsmmc_suspend(struct device *dev)
2212 {
2213         int ret = 0;
2214         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2215
2216         if (!host)
2217                 return 0;
2218
2219         if (host && host->suspended)
2220                 return 0;
2221
2222         pm_runtime_get_sync(host->dev);
2223         host->suspended = 1;
2224         ret = mmc_suspend_host(host->mmc);
2225
2226         if (ret) {
2227                 host->suspended = 0;
2228                 goto err;
2229         }
2230
2231         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2232                 omap_hsmmc_disable_irq(host);
2233                 OMAP_HSMMC_WRITE(host->base, HCTL,
2234                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2235         }
2236
2237         if (host->dbclk)
2238                 clk_disable_unprepare(host->dbclk);
2239 err:
2240         pm_runtime_put_sync(host->dev);
2241         return ret;
2242 }
2243
2244 /* Routine to resume the MMC device */
2245 static int omap_hsmmc_resume(struct device *dev)
2246 {
2247         int ret = 0;
2248         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2249
2250         if (!host)
2251                 return 0;
2252
2253         if (host && !host->suspended)
2254                 return 0;
2255
2256         pm_runtime_get_sync(host->dev);
2257
2258         if (host->dbclk)
2259                 clk_prepare_enable(host->dbclk);
2260
2261         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2262                 omap_hsmmc_conf_bus_power(host);
2263
2264         omap_hsmmc_protect_card(host);
2265
2266         /* Notify the core to resume the host */
2267         ret = mmc_resume_host(host->mmc);
2268         if (ret == 0)
2269                 host->suspended = 0;
2270
2271         pm_runtime_mark_last_busy(host->dev);
2272         pm_runtime_put_autosuspend(host->dev);
2273
2274         return ret;
2275
2276 }
2277
2278 #else
2279 #define omap_hsmmc_prepare      NULL
2280 #define omap_hsmmc_complete     NULL
2281 #define omap_hsmmc_suspend      NULL
2282 #define omap_hsmmc_resume       NULL
2283 #endif
2284
2285 static int omap_hsmmc_runtime_suspend(struct device *dev)
2286 {
2287         struct omap_hsmmc_host *host;
2288
2289         host = platform_get_drvdata(to_platform_device(dev));
2290         omap_hsmmc_context_save(host);
2291         dev_dbg(dev, "disabled\n");
2292
2293         return 0;
2294 }
2295
2296 static int omap_hsmmc_runtime_resume(struct device *dev)
2297 {
2298         struct omap_hsmmc_host *host;
2299
2300         host = platform_get_drvdata(to_platform_device(dev));
2301         omap_hsmmc_context_restore(host);
2302         dev_dbg(dev, "enabled\n");
2303
2304         return 0;
2305 }
2306
2307 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2308         .suspend        = omap_hsmmc_suspend,
2309         .resume         = omap_hsmmc_resume,
2310         .prepare        = omap_hsmmc_prepare,
2311         .complete       = omap_hsmmc_complete,
2312         .runtime_suspend = omap_hsmmc_runtime_suspend,
2313         .runtime_resume = omap_hsmmc_runtime_resume,
2314 };
2315
2316 static struct platform_driver omap_hsmmc_driver = {
2317         .probe          = omap_hsmmc_probe,
2318         .remove         = omap_hsmmc_remove,
2319         .driver         = {
2320                 .name = DRIVER_NAME,
2321                 .owner = THIS_MODULE,
2322                 .pm = &omap_hsmmc_dev_pm_ops,
2323                 .of_match_table = of_match_ptr(omap_mmc_of_match),
2324         },
2325 };
2326
2327 module_platform_driver(omap_hsmmc_driver);
2328 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2329 MODULE_LICENSE("GPL");
2330 MODULE_ALIAS("platform:" DRIVER_NAME);
2331 MODULE_AUTHOR("Texas Instruments Inc");