[PATCH] 2.5.17 IDE 70
[opensuse:kernel.git] / drivers / ide / hpt366.c
1 /**** vi:set ts=8 sts=8 sw=8:************************************************
2  *
3  * linux/drivers/ide/hpt366.c           Version 0.22    20 Sep 2001
4  *
5  * Copyright (C) 1999-2000              Andre Hedrick <andre@linux-ide.org>
6  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
7  * May be copied or modified under the terms of the GNU General Public License
8  *
9  * Thanks to HighPoint Technologies for their assistance, and hardware.
10  * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
11  * donation of an ABit BP6 mainboard, processor, and memory acellerated
12  * development and support.
13  *
14  * Note that final HPT370 support was done by force extraction of GPL.
15  *
16  * - add function for getting/setting power status of drive
17  * - the HPT370's state machine can get confused. reset it before each dma
18  *   xfer to prevent that from happening.
19  * - reset state engine whenever we get an error.
20  * - check for busmaster state at end of dma.
21  * - use new highpoint timings.
22  * - detect bus speed using highpoint register.
23  * - use pll if we don't have a clock table. added a 66MHz table that's
24  *   just 2x the 33MHz table.
25  * - removed turnaround. NOTE: we never want to switch between pll and
26  *   pci clocks as the chip can glitch in those cases. the highpoint
27  *   approved workaround slows everything down too much to be useful. in
28  *   addition, we would have to serialize access to each chip.
29  *      Adrian Sun <a.sun@sun.com>
30  *
31  * add drive timings for 66MHz PCI bus,
32  * fix ATA Cable signal detection, fix incorrect /proc info
33  * add /proc display for per-drive PIO/DMA/UDMA mode and
34  * per-channel ATA-33/66 Cable detect.
35  *      Duncan Laurie <void@sun.com>
36  *
37  * fixup /proc output for multiple controllers
38  *      Tim Hockin <thockin@sun.com>
39  *
40  * On hpt366:
41  * Reset the hpt366 on error, reset on dma
42  * Fix disabling Fast Interrupt hpt366.
43  *      Mike Waychison <crlf@sun.com>
44  *
45  * 02 May 2002 - HPT374 support (Andre Hedrick <andre@linux-ide.org>)
46  */
47
48 #include <linux/config.h>
49 #include <linux/types.h>
50 #include <linux/kernel.h>
51 #include <linux/delay.h>
52 #include <linux/timer.h>
53 #include <linux/mm.h>
54 #include <linux/ioport.h>
55 #include <linux/blkdev.h>
56 #include <linux/hdreg.h>
57
58 #include <linux/interrupt.h>
59 #include <linux/pci.h>
60 #include <linux/init.h>
61 #include <linux/ide.h>
62
63 #include <asm/uaccess.h>
64 #include <asm/io.h>
65 #include <asm/irq.h>
66
67 #include "ata-timing.h"
68 #include "pcihost.h"
69
70
71 #undef DISPLAY_HPT366_TIMINGS
72
73 /* various tuning parameters */
74 #define HPT_RESET_STATE_ENGINE
75 /*#define HPT_DELAY_INTERRUPT*/
76 /*#define HPT_SERIALIZE_IO*/
77
78 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
79 #include <linux/stat.h>
80 #include <linux/proc_fs.h>
81 #endif  /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
82
83 static const char *quirk_drives[] = {
84         "QUANTUM FIREBALLlct08 08",
85         "QUANTUM FIREBALLP KA6.4",
86         "QUANTUM FIREBALLP LM20.4",
87         "QUANTUM FIREBALLP LM20.5",
88         NULL
89 };
90
91 static const char *bad_ata100_5[] = {
92         "IBM-DTLA-307075",
93         "IBM-DTLA-307060",
94         "IBM-DTLA-307045",
95         "IBM-DTLA-307030",
96         "IBM-DTLA-307020",
97         "IBM-DTLA-307015",
98         "IBM-DTLA-305040",
99         "IBM-DTLA-305030",
100         "IBM-DTLA-305020",
101         "IC35L010AVER07-0",
102         "IC35L020AVER07-0",
103         "IC35L030AVER07-0",
104         "IC35L040AVER07-0",
105         "IC35L060AVER07-0",
106         "WDC AC310200R",
107         NULL
108 };
109
110 static const char *bad_ata66_4[] = {
111         "IBM-DTLA-307075",
112         "IBM-DTLA-307060",
113         "IBM-DTLA-307045",
114         "IBM-DTLA-307030",
115         "IBM-DTLA-307020",
116         "IBM-DTLA-307015",
117         "IBM-DTLA-305040",
118         "IBM-DTLA-305030",
119         "IBM-DTLA-305020",
120         "IC35L010AVER07-0",
121         "IC35L020AVER07-0",
122         "IC35L030AVER07-0",
123         "IC35L040AVER07-0",
124         "IC35L060AVER07-0",
125         "WDC AC310200R",
126         NULL
127 };
128
129 static const char *bad_ata66_3[] = {
130         "WDC AC310200R",
131         NULL
132 };
133
134 static const char *bad_ata33[] = {
135         "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
136         "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
137         "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
138         "Maxtor 90510D4",
139         "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
140         "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
141         "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
142         NULL
143 };
144
145 struct chipset_bus_clock_list_entry {
146         u8              xfer_speed;
147         unsigned int    chipset_settings;
148 };
149
150 /* key for bus clock timings
151  * bit
152  * 0:3    data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
153  *        DMA. cycles = value + 1
154  * 4:8    data_low_time. active time of DIOW_/DIOR_ for PIO and MW
155  *        DMA. cycles = value + 1
156  * 9:12   cmd_high_time. inactive time of DIOW_/DIOR_ during task file
157  *        register access.
158  * 13:17  cmd_low_time. active time of DIOW_/DIOR_ during task file
159  *        register access.
160  * 18:21  udma_cycle_time. clock freq and clock cycles for UDMA xfer.
161  *        during task file register access.
162  * 22:24  pre_high_time. time to initialize 1st cycle for PIO and MW DMA
163  *        xfer.
164  * 25:27  cmd_pre_high_time. time to initialize 1st PIO cycle for task
165  *        register access.
166  * 28     UDMA enable
167  * 29     DMA enable
168  * 30     PIO_MST enable. if set, the chip is in bus master mode during
169  *        PIO.
170  * 31     FIFO enable.
171  */
172 static struct chipset_bus_clock_list_entry forty_base_hpt366[] = {
173         {       XFER_UDMA_4,    0x900fd943      },
174         {       XFER_UDMA_3,    0x900ad943      },
175         {       XFER_UDMA_2,    0x900bd943      },
176         {       XFER_UDMA_1,    0x9008d943      },
177         {       XFER_UDMA_0,    0x9008d943      },
178
179         {       XFER_MW_DMA_2,  0xa008d943      },
180         {       XFER_MW_DMA_1,  0xa010d955      },
181         {       XFER_MW_DMA_0,  0xa010d9fc      },
182
183         {       XFER_PIO_4,     0xc008d963      },
184         {       XFER_PIO_3,     0xc010d974      },
185         {       XFER_PIO_2,     0xc010d997      },
186         {       XFER_PIO_1,     0xc010d9c7      },
187         {       XFER_PIO_0,     0xc018d9d9      },
188         {       0,              0x0120d9d9      }
189 };
190
191 static struct chipset_bus_clock_list_entry thirty_three_base_hpt366[] = {
192         {       XFER_UDMA_4,    0x90c9a731      },
193         {       XFER_UDMA_3,    0x90cfa731      },
194         {       XFER_UDMA_2,    0x90caa731      },
195         {       XFER_UDMA_1,    0x90cba731      },
196         {       XFER_UDMA_0,    0x90c8a731      },
197
198         {       XFER_MW_DMA_2,  0xa0c8a731      },
199         {       XFER_MW_DMA_1,  0xa0c8a732      },      /* 0xa0c8a733 */
200         {       XFER_MW_DMA_0,  0xa0c8a797      },
201
202         {       XFER_PIO_4,     0xc0c8a731      },
203         {       XFER_PIO_3,     0xc0c8a742      },
204         {       XFER_PIO_2,     0xc0d0a753      },
205         {       XFER_PIO_1,     0xc0d0a7a3      },      /* 0xc0d0a793 */
206         {       XFER_PIO_0,     0xc0d0a7aa      },      /* 0xc0d0a7a7 */
207         {       0,              0x0120a7a7      }
208 };
209
210 static struct chipset_bus_clock_list_entry twenty_five_base_hpt366[] = {
211
212         {       XFER_UDMA_4,    0x90c98521      },
213         {       XFER_UDMA_3,    0x90cf8521      },
214         {       XFER_UDMA_2,    0x90cf8521      },
215         {       XFER_UDMA_1,    0x90cb8521      },
216         {       XFER_UDMA_0,    0x90cb8521      },
217
218         {       XFER_MW_DMA_2,  0xa0ca8521      },
219         {       XFER_MW_DMA_1,  0xa0ca8532      },
220         {       XFER_MW_DMA_0,  0xa0ca8575      },
221
222         {       XFER_PIO_4,     0xc0ca8521      },
223         {       XFER_PIO_3,     0xc0ca8532      },
224         {       XFER_PIO_2,     0xc0ca8542      },
225         {       XFER_PIO_1,     0xc0d08572      },
226         {       XFER_PIO_0,     0xc0d08585      },
227         {       0,              0x01208585      }
228 };
229
230 #if 1
231 /* these are the current (4 sep 2001) timings from highpoint */
232 static struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
233         {       XFER_UDMA_5,    0x12446231      },
234         {       XFER_UDMA_4,    0x12446231      },
235         {       XFER_UDMA_3,    0x126c6231      },
236         {       XFER_UDMA_2,    0x12486231      },
237         {       XFER_UDMA_1,    0x124c6233      },
238         {       XFER_UDMA_0,    0x12506297      },
239
240         {       XFER_MW_DMA_2,  0x22406c31      },
241         {       XFER_MW_DMA_1,  0x22406c33      },
242         {       XFER_MW_DMA_0,  0x22406c97      },
243
244         {       XFER_PIO_4,     0x06414e31      },
245         {       XFER_PIO_3,     0x06414e42      },
246         {       XFER_PIO_2,     0x06414e53      },
247         {       XFER_PIO_1,     0x06814e93      },
248         {       XFER_PIO_0,     0x06814ea7      },
249         {       0,              0x06814ea7      }
250 };
251
252 /* 2x 33MHz timings */
253 static struct chipset_bus_clock_list_entry sixty_six_base_hpt370[] = {
254         {       XFER_UDMA_5,    0x1488e673       },
255         {       XFER_UDMA_4,    0x1488e673       },
256         {       XFER_UDMA_3,    0x1498e673       },
257         {       XFER_UDMA_2,    0x1490e673       },
258         {       XFER_UDMA_1,    0x1498e677       },
259         {       XFER_UDMA_0,    0x14a0e73f       },
260
261         {       XFER_MW_DMA_2,  0x2480fa73       },
262         {       XFER_MW_DMA_1,  0x2480fa77       },
263         {       XFER_MW_DMA_0,  0x2480fb3f       },
264
265         {       XFER_PIO_4,     0x0c82be73       },
266         {       XFER_PIO_3,     0x0c82be95       },
267         {       XFER_PIO_2,     0x0c82beb7       },
268         {       XFER_PIO_1,     0x0d02bf37       },
269         {       XFER_PIO_0,     0x0d02bf5f       },
270         {       0,              0x0d02bf5f       }
271 };
272 #else
273 /* from highpoint documentation. these are old values */
274 static struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
275         {       XFER_UDMA_5,    0x16454e31      },
276         {       XFER_UDMA_4,    0x16454e31      },
277         {       XFER_UDMA_3,    0x166d4e31      },
278         {       XFER_UDMA_2,    0x16494e31      },
279         {       XFER_UDMA_1,    0x164d4e31      },
280         {       XFER_UDMA_0,    0x16514e31      },
281
282         {       XFER_MW_DMA_2,  0x26514e21      },
283         {       XFER_MW_DMA_1,  0x26514e33      },
284         {       XFER_MW_DMA_0,  0x26514e97      },
285
286         {       XFER_PIO_4,     0x06514e21      },
287         {       XFER_PIO_3,     0x06514e22      },
288         {       XFER_PIO_2,     0x06514e33      },
289         {       XFER_PIO_1,     0x06914e43      },
290         {       XFER_PIO_0,     0x06914e57      },
291         {       0,              0x06514e57      }
292 };
293
294 static struct chipset_bus_clock_list_entry sixty_six_base_hpt370[] = {
295         {       XFER_UDMA_5,    0x14846231      },
296         {       XFER_UDMA_4,    0x14886231      },
297         {       XFER_UDMA_3,    0x148c6231      },
298         {       XFER_UDMA_2,    0x148c6231      },
299         {       XFER_UDMA_1,    0x14906231      },
300         {       XFER_UDMA_0,    0x14986231      },
301
302         {       XFER_MW_DMA_2,  0x26514e21      },
303         {       XFER_MW_DMA_1,  0x26514e33      },
304         {       XFER_MW_DMA_0,  0x26514e97      },
305
306         {       XFER_PIO_4,     0x06514e21      },
307         {       XFER_PIO_3,     0x06514e22      },
308         {       XFER_PIO_2,     0x06514e33      },
309         {       XFER_PIO_1,     0x06914e43      },
310         {       XFER_PIO_0,     0x06914e57      },
311         {       0,              0x06514e57      }
312 };
313 #endif
314
315 static struct chipset_bus_clock_list_entry fifty_base_hpt370[] = {
316         {       XFER_UDMA_5,    0x12848242      },
317         {       XFER_UDMA_4,    0x12ac8242      },
318         {       XFER_UDMA_3,    0x128c8242      },
319         {       XFER_UDMA_2,    0x120c8242      },
320         {       XFER_UDMA_1,    0x12148254      },
321         {       XFER_UDMA_0,    0x121882ea      },
322
323         {       XFER_MW_DMA_2,  0x22808242      },
324         {       XFER_MW_DMA_1,  0x22808254      },
325         {       XFER_MW_DMA_0,  0x228082ea      },
326
327         {       XFER_PIO_4,     0x0a81f442      },
328         {       XFER_PIO_3,     0x0a81f443      },
329         {       XFER_PIO_2,     0x0a81f454      },
330         {       XFER_PIO_1,     0x0ac1f465      },
331         {       XFER_PIO_0,     0x0ac1f48a      },
332         {       0,              0x0ac1f48a      }
333 };
334
335 static struct chipset_bus_clock_list_entry thirty_three_base_hpt372[] = {
336         {       XFER_UDMA_6,    0x1c81dc62      },
337         {       XFER_UDMA_5,    0x1c6ddc62      },
338         {       XFER_UDMA_4,    0x1c8ddc62      },
339         {       XFER_UDMA_3,    0x1c8edc62      },      /* checkme */
340         {       XFER_UDMA_2,    0x1c91dc62      },
341         {       XFER_UDMA_1,    0x1c9adc62      },      /* checkme */
342         {       XFER_UDMA_0,    0x1c82dc62      },      /* checkme */
343
344         {       XFER_MW_DMA_2,  0x2c829262      },
345         {       XFER_MW_DMA_1,  0x2c829266      },      /* checkme */
346         {       XFER_MW_DMA_0,  0x2c82922e      },      /* checkme */
347
348         {       XFER_PIO_4,     0x0c829c62      },
349         {       XFER_PIO_3,     0x0c829c84      },
350         {       XFER_PIO_2,     0x0c829ca6      },
351         {       XFER_PIO_1,     0x0d029d26      },
352         {       XFER_PIO_0,     0x0d029d5e      },
353         {       0,              0x0d029d5e      }
354 };
355
356 static struct chipset_bus_clock_list_entry fifty_base_hpt372[] = {
357         {       XFER_UDMA_5,    0x12848242      },
358         {       XFER_UDMA_4,    0x12ac8242      },
359         {       XFER_UDMA_3,    0x128c8242      },
360         {       XFER_UDMA_2,    0x120c8242      },
361         {       XFER_UDMA_1,    0x12148254      },
362         {       XFER_UDMA_0,    0x121882ea      },
363
364         {       XFER_MW_DMA_2,  0x22808242      },
365         {       XFER_MW_DMA_1,  0x22808254      },
366         {       XFER_MW_DMA_0,  0x228082ea      },
367
368         {       XFER_PIO_4,     0x0a81f442      },
369         {       XFER_PIO_3,     0x0a81f443      },
370         {       XFER_PIO_2,     0x0a81f454      },
371         {       XFER_PIO_1,     0x0ac1f465      },
372         {       XFER_PIO_0,     0x0ac1f48a      },
373         {       0,              0x0a81f443      }
374 };
375
376 static struct chipset_bus_clock_list_entry sixty_six_base_hpt372[] = {
377         {       XFER_UDMA_6,    0x1c869c62      },
378         {       XFER_UDMA_5,    0x1cae9c62      },
379         {       XFER_UDMA_4,    0x1c8a9c62      },
380         {       XFER_UDMA_3,    0x1c8e9c62      },
381         {       XFER_UDMA_2,    0x1c929c62      },
382         {       XFER_UDMA_1,    0x1c9a9c62      },
383         {       XFER_UDMA_0,    0x1c829c62      },
384
385         {       XFER_MW_DMA_2,  0x2c829c62      },
386         {       XFER_MW_DMA_1,  0x2c829c66      },
387         {       XFER_MW_DMA_0,  0x2c829d2e      },
388
389         {       XFER_PIO_4,     0x0c829c62      },
390         {       XFER_PIO_3,     0x0c829c84      },
391         {       XFER_PIO_2,     0x0c829ca6      },
392         {       XFER_PIO_1,     0x0d029d26      },
393         {       XFER_PIO_0,     0x0d029d5e      },
394         {       0,              0x0d029d26      }
395 };
396
397 static struct chipset_bus_clock_list_entry thirty_three_base_hpt374[] = {
398         {       XFER_UDMA_6,    0x12808242      },
399         {       XFER_UDMA_5,    0x12848242      },
400         {       XFER_UDMA_4,    0x12ac8242      },
401         {       XFER_UDMA_3,    0x128c8242      },
402         {       XFER_UDMA_2,    0x120c8242      },
403         {       XFER_UDMA_1,    0x12148254      },
404         {       XFER_UDMA_0,    0x121882ea      },
405
406         {       XFER_MW_DMA_2,  0x22808242      },
407         {       XFER_MW_DMA_1,  0x22808254      },
408         {       XFER_MW_DMA_0,  0x228082ea      },
409
410         {       XFER_PIO_4,     0x0a81f442      },
411         {       XFER_PIO_3,     0x0a81f443      },
412         {       XFER_PIO_2,     0x0a81f454      },
413         {       XFER_PIO_1,     0x0ac1f465      },
414         {       XFER_PIO_0,     0x0ac1f48a      },
415         {       0,              0x06814e93      }
416 };
417
418 #if 0
419 static struct chipset_bus_clock_list_entry fifty_base_hpt374[] = {
420         {       XFER_UDMA_6,    },
421         {       XFER_UDMA_5,    },
422         {       XFER_UDMA_4,    },
423         {       XFER_UDMA_3,    },
424         {       XFER_UDMA_2,    },
425         {       XFER_UDMA_1,    },
426         {       XFER_UDMA_0,    },
427         {       XFER_MW_DMA_2,  },
428         {       XFER_MW_DMA_1,  },
429         {       XFER_MW_DMA_0,  },
430         {       XFER_PIO_4,     },
431         {       XFER_PIO_3,     },
432         {       XFER_PIO_2,     },
433         {       XFER_PIO_1,     },
434         {       XFER_PIO_0,     },
435         {       0,      }
436 };
437 #endif
438 #if 0
439 static struct chipset_bus_clock_list_entry sixty_six_base_hpt374[] = {
440         {       XFER_UDMA_6,    0x12406231      },      /* checkme */
441         {       XFER_UDMA_5,    0x12446231      },
442                                 0x14846231
443         {       XFER_UDMA_4,            0x16814ea7      },
444                                 0x14886231
445         {       XFER_UDMA_3,            0x16814ea7      },
446                                 0x148c6231
447         {       XFER_UDMA_2,            0x16814ea7      },
448                                 0x148c6231
449         {       XFER_UDMA_1,            0x16814ea7      },
450                                 0x14906231
451         {       XFER_UDMA_0,            0x16814ea7      },
452                                 0x14986231
453         {       XFER_MW_DMA_2,          0x16814ea7      },
454                                 0x26514e21
455         {       XFER_MW_DMA_1,          0x16814ea7      },
456                                 0x26514e97
457         {       XFER_MW_DMA_0,          0x16814ea7      },
458                                 0x26514e97
459         {       XFER_PIO_4,             0x06814ea7      },
460                                 0x06514e21
461         {       XFER_PIO_3,             0x06814ea7      },
462                                 0x06514e22
463         {       XFER_PIO_2,             0x06814ea7      },
464                                 0x06514e33
465         {       XFER_PIO_1,             0x06814ea7      },
466                                 0x06914e43
467         {       XFER_PIO_0,             0x06814ea7      },
468                                 0x06914e57
469         {       0,              0x06814ea7      }
470 };
471 #endif
472
473 #define HPT366_DEBUG_DRIVE_INFO         0
474 #define HPT374_ALLOW_ATA133_6           0
475 #define HPT372_ALLOW_ATA133_6           1
476 #define HPT370_ALLOW_ATA100_5           1
477 #define HPT366_ALLOW_ATA66_4            1
478 #define HPT366_ALLOW_ATA66_3            1
479 #define HPT366_MAX_DEVS                 8
480
481 #define F_LOW_PCI_33      0x23
482 #define F_LOW_PCI_40      0x29
483 #define F_LOW_PCI_50      0x2d
484 #define F_LOW_PCI_66      0x42
485
486 static struct pci_dev *hpt_devs[HPT366_MAX_DEVS];
487 static int n_hpt_devs;
488
489 static u8 hpt366_proc = 0;
490
491 static unsigned int hpt_min_rev(struct pci_dev *dev, int rev);
492
493 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
494 static int hpt366_get_info(char *, char **, off_t, int);
495 extern int (*hpt366_display_info)(char *, char **, off_t, int); /* ide-proc.c */
496
497 static int hpt366_get_info (char *buffer, char **addr, off_t offset, int count)
498 {
499         char *p = buffer;
500         char *chipset_nums[] = {"366", "366",  "368",
501                                 "370", "370A", "372",
502                                 "??",  "374" };
503         int i;
504
505         p += sprintf(p, "\n                             "
506                 "HighPoint HPT366/368/370/372/374\n");
507         for (i = 0; i < n_hpt_devs; i++) {
508                 struct pci_dev *dev = hpt_devs[i];
509                 unsigned short iobase = dev->resource[4].start;
510                 u32 class_rev;
511                 u8 c0, c1;
512
513                 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
514                 class_rev &= 0xff;
515
516                 p += sprintf(p, "\nController: %d\n", i);
517                 p += sprintf(p, "Chipset: HPT%s\n",
518                         class_rev < sizeof(chipset_nums) / sizeof(char *) ? chipset_nums[class_rev] : "???");
519                 p += sprintf(p, "--------------- Primary Channel "
520                                 "--------------- Secondary Channel "
521                                 "--------------\n");
522
523                 /* get the bus master status registers */
524                 c0 = inb_p(iobase + 0x2);
525                 c1 = inb_p(iobase + 0xa);
526                 p += sprintf(p, "Enabled:        %s"
527                                 "                             %s\n",
528                         (c0 & 0x80) ? "no" : "yes",
529                         (c1 & 0x80) ? "no" : "yes");
530
531                 if (hpt_min_rev(dev, 3)) {
532                         u8 cbl;
533                         cbl = inb_p(iobase + 0x7b);
534                         outb_p(cbl | 1, iobase + 0x7b);
535                         outb_p(cbl & ~1, iobase + 0x7b);
536                         cbl = inb_p(iobase + 0x7a);
537                         p += sprintf(p, "Cable:          ATA-%d"
538                                         "                          ATA-%d\n",
539                                 (cbl & 0x02) ? 33 : 66,
540                                 (cbl & 0x01) ? 33 : 66);
541                         p += sprintf(p, "\n");
542                 }
543
544                 p += sprintf(p, "--------------- drive0 --------- drive1 "
545                                 "------- drive0 ---------- drive1 -------\n");
546                 p += sprintf(p, "DMA capable:    %s              %s" 
547                                 "            %s               %s\n",
548                         (c0 & 0x20) ? "yes" : "no ", 
549                         (c0 & 0x40) ? "yes" : "no ",
550                         (c1 & 0x20) ? "yes" : "no ", 
551                         (c1 & 0x40) ? "yes" : "no ");
552
553                 {
554                         u8 c2, c3;
555                         /* older revs don't have these registers mapped
556                          * into io space */
557                         pci_read_config_byte(dev, 0x43, &c0);
558                         pci_read_config_byte(dev, 0x47, &c1);
559                         pci_read_config_byte(dev, 0x4b, &c2);
560                         pci_read_config_byte(dev, 0x4f, &c3);
561
562                         p += sprintf(p, "Mode:           %s             %s"
563                                         "           %s              %s\n",
564                                 (c0 & 0x10) ? "UDMA" : (c0 & 0x20) ? "DMA " :
565                                         (c0 & 0x80) ? "PIO " : "off ",
566                                 (c1 & 0x10) ? "UDMA" : (c1 & 0x20) ? "DMA " :
567                                         (c1 & 0x80) ? "PIO " : "off ",
568                                 (c2 & 0x10) ? "UDMA" : (c2 & 0x20) ? "DMA " :
569                                         (c2 & 0x80) ? "PIO " : "off ",
570                                 (c3 & 0x10) ? "UDMA" : (c3 & 0x20) ? "DMA " :
571                                         (c3 & 0x80) ? "PIO " : "off ");
572                 }
573         }
574         p += sprintf(p, "\n");
575
576         return p-buffer;/* => must be less than 4k! */
577 }
578 #endif  /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
579
580 static int check_in_drive_lists(struct ata_device *drive, const char **list)
581 {
582         struct hd_driveid *id = drive->id;
583
584         if (quirk_drives == list) {
585                 while (*list) {
586                         if (strstr(id->model, *list++)) {
587                                 return 1;
588                         }
589                 }
590         } else {
591                 while (*list) {
592                         if (!strcmp(*list++,id->model)) {
593                                 return 1;
594                         }
595                 }
596         }
597         return 0;
598 }
599
600 static unsigned int hpt_revision(struct pci_dev *dev)
601 {
602         unsigned int class_rev;
603         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
604         class_rev &= 0xff;
605
606         switch(dev->device) {
607                 case PCI_DEVICE_ID_TTI_HPT374:
608                         class_rev = PCI_DEVICE_ID_TTI_HPT374; break;
609                 case PCI_DEVICE_ID_TTI_HPT372:
610                         class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
611                 default:
612                         break;
613         }
614         return class_rev;
615 }
616
617 static unsigned int hpt_min_rev(struct pci_dev *dev, int rev)
618 {
619         return (hpt_revision(dev) >= rev) ? 1 : 0;
620 }
621
622 static int hpt3xx_ratemask(struct ata_device *drive)
623 {
624         struct pci_dev *dev = drive->channel->pci_dev;
625         int map = XFER_UDMA;
626
627         if (hpt_min_rev(dev, 8)) {                      /* HPT374 */
628                 if (HPT374_ALLOW_ATA133_6)
629                         map |= XFER_UDMA_133;
630                 map |= (XFER_UDMA_100 | XFER_UDMA_66);
631         } else if (hpt_min_rev(dev, 5)) {               /* HPT372 */
632                 if (HPT372_ALLOW_ATA133_6)
633                         map |= XFER_UDMA_133;
634                 map |= (XFER_UDMA_100 | XFER_UDMA_66);
635         } else if (hpt_min_rev(dev, 4)) {               /* HPT370A */
636                 if (HPT370_ALLOW_ATA100_5)
637                         map |= XFER_UDMA_100;
638                 map |= XFER_UDMA_66;
639         } else if (hpt_min_rev(dev, 3)) {               /* HPT370 */
640                 if (HPT370_ALLOW_ATA100_5)
641                         map |= XFER_UDMA_100;
642                 map |= XFER_UDMA_66;
643                 if (check_in_drive_lists(drive, bad_ata33))
644                         return 0;
645         } else {                                        /* HPT366 and HPT368 */
646                 map |= XFER_UDMA_66;
647                 if (check_in_drive_lists(drive, bad_ata33))
648                         return 0;
649         }
650
651         if (!eighty_ninty_three(drive))
652                 return XFER_UDMA;
653
654         return map;
655 }
656
657
658 static unsigned int pci_bus_clock_list(byte speed, struct chipset_bus_clock_list_entry * chipset_table)
659 {
660         for ( ; chipset_table->xfer_speed ; chipset_table++)
661                 if (chipset_table->xfer_speed == speed) {
662                         return chipset_table->chipset_settings;
663                 }
664         return chipset_table->chipset_settings;
665 }
666
667 static void hpt366_tune_chipset(struct ata_device *drive, byte speed)
668 {
669         struct pci_dev *dev     = drive->channel->pci_dev;
670         byte regtime            = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
671         byte regfast            = (drive->channel->unit) ? 0x55 : 0x51;
672                         /*
673                          * since the channel is always 0 it does not matter.
674                          */
675
676         unsigned int reg1       = 0;
677         unsigned int reg2       = 0;
678         byte drive_fast         = 0;
679
680         /*
681          * Disable the "fast interrupt" prediction.
682          */
683         pci_read_config_byte(dev, regfast, &drive_fast);
684         if (drive_fast & 0x80)
685                 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
686
687         pci_read_config_dword(dev, regtime, &reg1);
688         reg2 = pci_bus_clock_list(speed,
689                 (struct chipset_bus_clock_list_entry *) dev->sysdata);
690         /*
691          * Disable on-chip PIO FIFO/buffer (to avoid problems handling I/O errors later)
692          */
693         if (speed >= XFER_MW_DMA_0) {
694                 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
695         } else {
696                 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
697         }
698         reg2 &= ~0x80000000;
699
700         pci_write_config_dword(dev, regtime, reg2);
701 }
702
703 static void hpt368_tune_chipset(struct ata_device *drive, byte speed)
704 {
705         hpt366_tune_chipset(drive, speed);
706 }
707
708 static void hpt370_tune_chipset(struct ata_device *drive, byte speed)
709 {
710         byte regfast            = (drive->channel->unit) ? 0x55 : 0x51;
711         unsigned int list_conf  = 0;
712         unsigned int drive_conf = 0;
713         unsigned int conf_mask  = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
714         byte drive_pci          = 0x40 + (drive->dn * 4);
715         byte new_fast, drive_fast               = 0;
716         struct pci_dev *dev     = drive->channel->pci_dev;
717
718         /*
719          * Disable the "fast interrupt" prediction.
720          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
721          */
722         pci_read_config_byte(dev, regfast, &drive_fast);
723         new_fast = drive_fast;
724         if (new_fast & 0x02)
725                 new_fast &= ~0x02;
726
727 #ifdef HPT_DELAY_INTERRUPT
728         if (new_fast & 0x01)
729                 new_fast &= ~0x01;
730 #else
731         if ((new_fast & 0x01) == 0)
732                 new_fast |= 0x01;
733 #endif
734         if (new_fast != drive_fast)
735                 pci_write_config_byte(drive->channel->pci_dev, regfast, new_fast);
736
737         list_conf = pci_bus_clock_list(speed,
738                                        (struct chipset_bus_clock_list_entry *)
739                                        dev->sysdata);
740
741         pci_read_config_dword(dev, drive_pci, &drive_conf);
742         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
743
744         if (speed < XFER_MW_DMA_0) {
745                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
746         }
747
748         pci_write_config_dword(dev, drive_pci, list_conf);
749 }
750
751 static void hpt372_tune_chipset(struct ata_device *drive, byte speed)
752 {
753         byte regfast            = (drive->channel->unit) ? 0x55 : 0x51;
754         unsigned int list_conf  = 0;
755         unsigned int drive_conf = 0;
756         unsigned int conf_mask  = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
757         byte drive_pci          = 0x40 + (drive->dn * 4);
758         byte drive_fast         = 0;
759         struct pci_dev *dev     = drive->channel->pci_dev;
760
761         /*
762          * Disable the "fast interrupt" prediction.
763          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
764          */
765         pci_read_config_byte(dev, regfast, &drive_fast);
766         drive_fast &= ~0x07;
767         pci_write_config_byte(drive->channel->pci_dev, regfast, drive_fast);
768
769         list_conf = pci_bus_clock_list(speed,
770                         (struct chipset_bus_clock_list_entry *)
771                                         dev->sysdata);
772         pci_read_config_dword(dev, drive_pci, &drive_conf);
773         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
774         if (speed < XFER_MW_DMA_0)
775                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
776         pci_write_config_dword(dev, drive_pci, list_conf);
777 }
778
779 static void hpt374_tune_chipset(struct ata_device *drive, byte speed)
780 {
781         hpt372_tune_chipset(drive, speed);
782 }
783
784 static int hpt3xx_tune_chipset(struct ata_device *drive, byte speed)
785 {
786         struct pci_dev *dev = drive->channel->pci_dev;
787
788         if ((drive->type != ATA_DISK) && (speed < XFER_SW_DMA_0))
789                 return -1;
790
791         if (!drive->init_speed)
792                 drive->init_speed = speed;
793
794         if (hpt_min_rev(dev, 7)) {
795                 hpt374_tune_chipset(drive, speed);
796         } else if (hpt_min_rev(dev, 5)) {
797                 hpt372_tune_chipset(drive, speed);
798         } else if (hpt_min_rev(dev, 3)) {
799                 hpt370_tune_chipset(drive, speed);
800         } else if (hpt_min_rev(dev, 2)) {
801                 hpt368_tune_chipset(drive, speed);
802         } else {
803                 hpt366_tune_chipset(drive, speed);
804         }
805         drive->current_speed = speed;
806         return ((int) ide_config_drive_speed(drive, speed));
807 }
808
809 static void config_chipset_for_pio(struct ata_device *drive)
810 {
811         unsigned short eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
812         unsigned short xfer_pio = drive->id->eide_pio_modes;
813         byte    timing, speed, pio;
814
815         pio = ata_timing_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
816
817         if (xfer_pio > 4)
818                 xfer_pio = 0;
819
820         if (drive->id->eide_pio_iordy > 0) {
821                 for (xfer_pio = 5;
822                         xfer_pio>0 &&
823                         drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
824                         xfer_pio--);
825         } else {
826                 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
827                            (drive->id->eide_pio_modes & 2) ? 0x04 :
828                            (drive->id->eide_pio_modes & 1) ? 0x03 :
829                            (drive->id->tPIO & 2) ? 0x02 :
830                            (drive->id->tPIO & 1) ? 0x01 : xfer_pio;
831         }
832
833         timing = (xfer_pio >= pio) ? xfer_pio : pio;
834
835         switch(timing) {
836                 case 4: speed = XFER_PIO_4;break;
837                 case 3: speed = XFER_PIO_3;break;
838                 case 2: speed = XFER_PIO_2;break;
839                 case 1: speed = XFER_PIO_1;break;
840                 default:
841                         speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
842                         break;
843         }
844         (void) hpt3xx_tune_chipset(drive, speed);
845 }
846
847 static void hpt3xx_tune_drive(struct ata_device *drive, byte pio)
848 {
849         byte speed;
850         switch(pio) {
851                 case 4:         speed = XFER_PIO_4;break;
852                 case 3:         speed = XFER_PIO_3;break;
853                 case 2:         speed = XFER_PIO_2;break;
854                 case 1:         speed = XFER_PIO_1;break;
855                 default:        speed = XFER_PIO_0;break;
856         }
857         (void) hpt3xx_tune_chipset(drive, speed);
858 }
859
860 #ifdef CONFIG_BLK_DEV_IDEDMA
861 static int config_chipset_for_dma(struct ata_device *drive)
862 {
863         struct pci_dev *dev = drive->channel->pci_dev;
864         int map;
865         byte mode;
866
867         /* FIXME: remove this --bkz */
868         config_chipset_for_pio(drive);
869
870         if (drive->type != ATA_DISK)
871                 return 0;
872
873         /* FIXME: check SWDMA modes --bkz */
874         map = hpt3xx_ratemask(drive) | XFER_MWDMA;
875         mode = ata_timing_mode(drive, map);
876
877         /* FIXME: badlists need futher investigation --bkz
878                   bad_ata100_5 is for HPT370/370A,
879                   bad_ata66_4, bad_ata66_3 and bad_ata33 are for HPT366/368
880          */
881         if (mode == XFER_UDMA_5 && hpt_min_rev(dev, 5)) {
882                 if (check_in_drive_lists(drive, bad_ata100_5)) {
883                         /* FIXME: make XFER_UDMA_66/100/133
884                                   independent of XFER_UDMA --bkz */
885                         map &= ~XFER_UDMA_100;
886                         map |= XFER_UDMA;
887                         mode = ata_timing_mode(drive, map);
888                 }
889         }
890         if (mode == XFER_UDMA_4 && hpt_min_rev(dev, 3)) {
891                 if (check_in_drive_lists(drive, bad_ata66_4)) {
892                         if (drive->id->dma_ultra & 0x0008) {
893                                 mode = XFER_UDMA_3;
894                         } else {
895                                 map &= ~XFER_UDMA_66;
896                                 map |= XFER_UDMA;
897                                 mode = ata_timing_mode(drive, map);
898                         }
899                 }
900         }
901         if (mode == XFER_UDMA_3 && hpt_min_rev(dev, 3)) {
902                 if (check_in_drive_lists(drive, bad_ata66_3)) {
903                         map &= ~XFER_UDMA_66;
904                         map |= XFER_UDMA;
905                         mode = ata_timing_mode(drive, map);
906                 }
907         }
908         if (check_in_drive_lists(drive, bad_ata33) && hpt_min_rev(dev, 3))
909                 mode = ata_timing_mode(drive, XFER_MWDMA);
910
911         return !hpt3xx_tune_chipset(drive, mode);
912 }
913
914 static int hpt3xx_quirkproc(struct ata_device *drive)
915 {
916         return ((int) check_in_drive_lists(drive, quirk_drives));
917 }
918
919 static void hpt3xx_intrproc(struct ata_device *drive)
920 {
921         if (drive->quirk_list) {
922                 /* drives in the quirk_list may not like intr setups/cleanups */
923         } else {
924                 OUT_BYTE((drive)->ctl|2, drive->channel->io_ports[IDE_CONTROL_OFFSET]);
925         }
926 }
927
928 static void hpt3xx_maskproc(struct ata_device *drive, int mask)
929 {
930         struct pci_dev *dev = drive->channel->pci_dev;
931
932         if (drive->quirk_list) {
933                 if (hpt_min_rev(dev, 3)) {
934                         byte reg5a = 0;
935                         pci_read_config_byte(dev, 0x5a, &reg5a);
936                         if (((reg5a & 0x10) >> 4) != mask)
937                                 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
938                 } else {
939                         if (mask) {
940                                 disable_irq(drive->channel->irq);
941                         } else {
942                                 enable_irq(drive->channel->irq);
943                         }
944                 }
945         } else {
946                 if (IDE_CONTROL_REG)
947                         OUT_BYTE(mask ? (drive->ctl | 2) : (drive->ctl & ~2), IDE_CONTROL_REG);
948         }
949 }
950
951 static int config_drive_xfer_rate(struct ata_device *drive)
952 {
953         struct hd_driveid *id = drive->id;
954         int on = 1;
955         int verbose = 1;
956
957         if (id && (id->capability & 1) && drive->channel->autodma) {
958                 /* Consult the list of known "bad" drives */
959                 if (udma_black_list(drive)) {
960                         on = 0;
961                         goto fast_ata_pio;
962                 }
963                 on = 0;
964                 verbose = 0;
965                 if (id->field_valid & 4) {
966                         if (id->dma_ultra & 0x007F) {
967                                 /* Force if Capable UltraDMA */
968                                 on = config_chipset_for_dma(drive);
969                                 if ((id->field_valid & 2) &&
970                                     (!on))
971                                         goto try_dma_modes;
972                         }
973                 } else if (id->field_valid & 2) {
974 try_dma_modes:
975                         if (id->dma_mword & 0x0007) {
976                                 /* Force if Capable regular DMA modes */
977                                 on = config_chipset_for_dma(drive);
978                                 if (!on)
979                                         goto no_dma_set;
980                         }
981                 } else if (udma_white_list(drive)) {
982                         if (id->eide_dma_time > 150) {
983                                 goto no_dma_set;
984                         }
985                         /* Consult the list of known "good" drives */
986                         on = config_chipset_for_dma(drive);
987                         if (!on)
988                                 goto no_dma_set;
989                 } else {
990                         goto fast_ata_pio;
991                 }
992         } else if ((id->capability & 8) || (id->field_valid & 2)) {
993 fast_ata_pio:
994                 on = 0;
995                 verbose = 0;
996 no_dma_set:
997
998                 config_chipset_for_pio(drive);
999         }
1000         udma_enable(drive, on, verbose);
1001
1002         return 0;
1003 }
1004
1005 static void hpt366_udma_irq_lost(struct ata_device *drive)
1006 {
1007         u8 reg50h = 0, reg52h = 0, reg5ah = 0;
1008
1009         pci_read_config_byte(drive->channel->pci_dev, 0x50, &reg50h);
1010         pci_read_config_byte(drive->channel->pci_dev, 0x52, &reg52h);
1011         pci_read_config_byte(drive->channel->pci_dev, 0x5a, &reg5ah);
1012         printk("%s: (%s)  reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
1013                         drive->name, __FUNCTION__, reg50h, reg52h, reg5ah);
1014         if (reg5ah & 0x10)
1015                 pci_write_config_byte(drive->channel->pci_dev, 0x5a, reg5ah & ~0x10);
1016 }
1017
1018 /*
1019  * This is specific to the HPT366 UDMA bios chipset
1020  * by HighPoint|Triones Technologies, Inc.
1021  */
1022 static int hpt366_dmaproc(struct ata_device *drive)
1023 {
1024         return config_drive_xfer_rate(drive);
1025 }
1026
1027 static void do_udma_start(struct ata_device *drive)
1028 {
1029         struct ata_channel *ch = drive->channel;
1030
1031         u8 regstate = ch->unit ? 0x54 : 0x50;
1032         pci_write_config_byte(ch->pci_dev, regstate, 0x37);
1033         udelay(10);
1034 }
1035
1036 static int hpt370_udma_start(struct ata_device *drive, struct request *__rq)
1037 {
1038         struct ata_channel *ch = drive->channel;
1039
1040         do_udma_start(drive);
1041
1042         /* Note that this is done *after* the cmd has been issued to the drive,
1043          * as per the BM-IDE spec.  The Promise Ultra33 doesn't work correctly
1044          * when we do this part before issuing the drive cmd.
1045          */
1046
1047         outb(inb(ch->dma_base) | 1, ch->dma_base);      /* start DMA */
1048
1049         return 0;
1050 }
1051
1052 static void do_timeout_irq(struct ata_device *drive)
1053 {
1054         u8 dma_stat;
1055         u8 regstate = drive->channel->unit ? 0x54 : 0x50;
1056         u8 reginfo = drive->channel->unit ? 0x56 : 0x52;
1057         unsigned long dma_base = drive->channel->dma_base;
1058
1059         pci_read_config_byte(drive->channel->pci_dev, reginfo, &dma_stat);
1060         printk(KERN_INFO "%s: %d bytes in FIFO\n", drive->name, dma_stat);
1061         pci_write_config_byte(drive->channel->pci_dev, regstate, 0x37);
1062         udelay(10);
1063         dma_stat = inb(dma_base);
1064         outb(dma_stat & ~0x1, dma_base); /* stop dma */
1065         dma_stat = inb(dma_base + 2);
1066         outb(dma_stat | 0x6, dma_base+2); /* clear errors */
1067
1068 }
1069
1070 static void hpt370_udma_timeout(struct ata_device *drive)
1071 {
1072         do_timeout_irq(drive);
1073         do_udma_start(drive);
1074 }
1075
1076 static void hpt370_udma_irq_lost(struct ata_device *drive)
1077 {
1078         do_timeout_irq(drive);
1079         do_udma_start(drive);
1080 }
1081
1082 static int hpt370_udma_stop(struct ata_device *drive)
1083 {
1084         struct ata_channel *ch = drive->channel;
1085         unsigned long dma_base = ch->dma_base;
1086         u8 dma_stat;
1087
1088         dma_stat = inb(dma_base + 2);
1089         if (dma_stat & 0x01) {
1090                 udelay(20); /* wait a little */
1091                 dma_stat = inb(dma_base + 2);
1092         }
1093         if ((dma_stat & 0x01) != 0) {
1094                 do_timeout_irq(drive);
1095                 do_udma_start(drive);
1096         }
1097
1098         drive->waiting_for_dma = 0;
1099         outb(inb(dma_base)&~1, dma_base);       /* stop DMA */
1100         dma_stat = inb(dma_base+2);             /* get DMA status */
1101         outb(dma_stat|6, dma_base+2);           /* clear the INTR & ERROR bits */
1102         udma_destroy_table(ch);                 /* purge DMA mappings */
1103
1104         return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;     /* verify good DMA status */
1105 }
1106
1107 static int hpt370_dmaproc(struct ata_device *drive)
1108 {
1109         return config_drive_xfer_rate(drive);
1110 }
1111
1112 static int hpt374_udma_stop(struct ata_device *drive)
1113 {
1114         struct ata_channel *ch = drive->channel;
1115         struct pci_dev *dev = drive->channel->pci_dev;
1116         unsigned long dma_base = ch->dma_base;
1117         u8 mscreg = ch->unit ? 0x54 : 0x50;
1118         u8 dma_stat;
1119         u8 bwsr_mask = ch->unit ? 0x02 : 0x01;
1120         u8 bwsr_stat, msc_stat;
1121         pci_read_config_byte(dev, 0x6a, &bwsr_stat);
1122         pci_read_config_byte(dev, mscreg, &msc_stat);
1123         if ((bwsr_stat & bwsr_mask) == bwsr_mask)
1124                 pci_write_config_byte(dev, mscreg, msc_stat|0x30);
1125
1126         drive->waiting_for_dma = 0;
1127         outb(inb(dma_base)&~1, dma_base);       /* stop DMA */
1128         dma_stat = inb(dma_base+2);             /* get DMA status */
1129         outb(dma_stat|6, dma_base+2);           /* clear the INTR & ERROR bits */
1130         udma_destroy_table(ch);                 /* purge DMA mappings */
1131
1132         return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;     /* verify good DMA status */
1133 }
1134
1135 static int hpt374_dmaproc(struct ata_device *drive)
1136 {
1137         return config_drive_xfer_rate(drive);
1138 }
1139 #endif
1140
1141 /*
1142  * Since SUN Cobalt is attempting to do this operation, I should disclose
1143  * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
1144  * HOTSWAP ATA Infrastructure.
1145  */
1146 static void hpt3xx_reset(struct ata_device *drive)
1147 {
1148 #if 0
1149         unsigned long high_16   = pci_resource_start(drive->channel->pci_dev, 4);
1150         byte reset              = (drive->channel->unit) ? 0x80 : 0x40;
1151         byte reg59h             = 0;
1152
1153         pci_read_config_byte(drive->channel->pci_dev, 0x59, &reg59h);
1154         pci_write_config_byte(drive->channel->pci_dev, 0x59, reg59h|reset);
1155         pci_write_config_byte(drive->channel->pci_dev, 0x59, reg59h);
1156 #endif
1157 }
1158
1159 #if 0
1160 static int hpt3xx_tristate(struct ata_device * drive, int state)
1161 {
1162         struct ata_channel *ch  = drive->channel;
1163         struct pci_dev *dev     = ch->pci_dev;
1164         byte reset              = (ch->unit) ? 0x80 : 0x40;
1165         byte state_reg          = (ch->unit) ? 0x57 : 0x53;
1166         byte reg59h             = 0;
1167         byte regXXh             = 0;
1168
1169         if (!ch)
1170                 return -EINVAL;
1171
1172 //      ch->bus_state = state;
1173
1174         pci_read_config_byte(dev, 0x59, &reg59h);
1175         pci_read_config_byte(dev, state_reg, &regXXh);
1176
1177         if (state) {
1178                 // reset drives...
1179                 pci_write_config_byte(dev, state_reg, regXXh|0x80);
1180                 pci_write_config_byte(dev, 0x59, reg59h|reset);
1181         } else {
1182                 pci_write_config_byte(dev, 0x59, reg59h & ~(reset));
1183                 pci_write_config_byte(dev, state_reg, regXXh & ~(0x80));
1184                 // reset drives...
1185         }
1186         return 0;
1187 }
1188 #endif
1189
1190 /*
1191  * set/get power state for a drive.
1192  * turning the power off does the following things:
1193  *   1) soft-reset the drive
1194  *   2) tri-states the ide bus
1195  *
1196  * when we turn things back on, we need to re-initialize things.
1197  */
1198 #define TRISTATE_BIT  0x8000
1199 static int hpt370_busproc(struct ata_device * drive, int state)
1200 {
1201         struct ata_channel *ch = drive->channel;
1202         u8 tristate, resetmask, bus_reg;
1203         u16 tri_reg;
1204
1205         if (!ch)
1206                 return -EINVAL;
1207
1208         ch->bus_state = state;
1209
1210         if (ch->unit) {
1211                 /* secondary channel */
1212                 tristate = 0x56;
1213                 resetmask = 0x80;
1214         } else {
1215                 /* primary channel */
1216                 tristate = 0x52;
1217                 resetmask = 0x40;
1218         }
1219
1220         /* grab status */
1221         pci_read_config_word(ch->pci_dev, tristate, &tri_reg);
1222         pci_read_config_byte(ch->pci_dev, 0x59, &bus_reg);
1223
1224         /* set the state. we don't set it if we don't need to do so.
1225          * make sure that the drive knows that it has failed if it's off */
1226         switch (state) {
1227         case BUSSTATE_ON:
1228                 ch->drives[0].failures = 0;
1229                 ch->drives[1].failures = 0;
1230                 if ((bus_reg & resetmask) == 0)
1231                         return 0;
1232                 tri_reg &= ~TRISTATE_BIT;
1233                 bus_reg &= ~resetmask;
1234                 break;
1235         case BUSSTATE_OFF:
1236                 ch->drives[0].failures = ch->drives[0].max_failures + 1;
1237                 ch->drives[1].failures = ch->drives[1].max_failures + 1;
1238                 if ((tri_reg & TRISTATE_BIT) == 0 && (bus_reg & resetmask))
1239                         return 0;
1240                 tri_reg &= ~TRISTATE_BIT;
1241                 bus_reg |= resetmask;
1242                 break;
1243         case BUSSTATE_TRISTATE:
1244                 ch->drives[0].failures = ch->drives[0].max_failures + 1;
1245                 ch->drives[1].failures = ch->drives[1].max_failures + 1;
1246                 if ((tri_reg & TRISTATE_BIT) && (bus_reg & resetmask))
1247                         return 0;
1248                 tri_reg |= TRISTATE_BIT;
1249                 bus_reg |= resetmask;
1250                 break;
1251         }
1252         pci_write_config_byte(ch->pci_dev, 0x59, bus_reg);
1253         pci_write_config_word(ch->pci_dev, tristate, tri_reg);
1254
1255         return 0;
1256 }
1257
1258 static void __init hpt37x_init(struct pci_dev *dev)
1259 {
1260         int adjust, i;
1261         u16 freq;
1262         u32 pll;
1263         u8 reg5bh;
1264
1265         /*
1266          * default to pci clock. make sure MA15/16 are set to output
1267          * to prevent drives having problems with 40-pin cables.
1268          */
1269         pci_write_config_byte(dev, 0x5b, 0x23);
1270
1271         /*
1272          * set up the PLL. we need to adjust it so that it's stable.
1273          * freq = Tpll * 192 / Tpci
1274          */
1275         pci_read_config_word(dev, 0x78, &freq);
1276         freq &= 0x1FF;
1277         if (freq < 0x9c) {
1278                 pll = F_LOW_PCI_33;
1279                 if (hpt_min_rev(dev, 7)) {
1280                         dev->sysdata = (void *) thirty_three_base_hpt374;
1281                 } else if (hpt_min_rev(dev, 5)) {
1282                         dev->sysdata = (void *) thirty_three_base_hpt372;
1283                 } else {
1284                         dev->sysdata = (void *) thirty_three_base_hpt370;
1285                 }
1286                 printk("HPT37X: using 33MHz PCI clock\n");
1287         } else if (freq < 0xb0) {
1288                 pll = F_LOW_PCI_40;
1289         } else if (freq < 0xc8) {
1290                 pll = F_LOW_PCI_50;
1291                 if (hpt_min_rev(dev, 7)) {
1292         //              dev->sysdata = (void *) fifty_base_hpt374;
1293                         BUG();
1294                 } else if (hpt_min_rev(dev, 5)) {
1295                         dev->sysdata = (void *) fifty_base_hpt372;
1296                 } else {
1297                         dev->sysdata = (void *) fifty_base_hpt370;
1298                 }
1299                 printk("HPT37X: using 50MHz PCI clock\n");
1300         } else {
1301                 pll = F_LOW_PCI_66;
1302                 if (hpt_min_rev(dev, 7)) {
1303         //              dev->sysdata = (void *) sixty_six_base_hpt374;
1304                         BUG();
1305                 } else if (hpt_min_rev(dev, 5)) {
1306                         dev->sysdata = (void *) sixty_six_base_hpt372;
1307                 } else {
1308                         dev->sysdata = (void *) sixty_six_base_hpt370;
1309                 }
1310                 printk("HPT37X: using 66MHz PCI clock\n");
1311         }
1312
1313         /*
1314          * only try the pll if we don't have a table for the clock
1315          * speed that we're running at. NOTE: the internal PLL will
1316          * result in slow reads when using a 33MHz PCI clock. we also
1317          * don't like to use the PLL because it will cause glitches
1318          * on PRST/SRST when the HPT state engine gets reset.
1319          */
1320         if (dev->sysdata)
1321                 goto init_hpt37X_done;
1322
1323         /*
1324          * adjust PLL based upon PCI clock, enable it, and wait for
1325          * stabilization.
1326          */
1327         adjust = 0;
1328         freq = (pll < F_LOW_PCI_50) ? 2 : 4;
1329         while (adjust++ < 6) {
1330                 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
1331                                        pll | 0x100);
1332
1333                 /* wait for clock stabilization */
1334                 for (i = 0; i < 0x50000; i++) {
1335                         pci_read_config_byte(dev, 0x5b, &reg5bh);
1336                         if (reg5bh & 0x80) {
1337                                 /* spin looking for the clock to destabilize */
1338                                 for (i = 0; i < 0x1000; ++i) {
1339                                         pci_read_config_byte(dev, 0x5b,
1340                                                              &reg5bh);
1341                                         if ((reg5bh & 0x80) == 0)
1342                                                 goto pll_recal;
1343                                 }
1344                                 pci_read_config_dword(dev, 0x5c, &pll);
1345                                 pci_write_config_dword(dev, 0x5c,
1346                                                        pll & ~0x100);
1347                                 pci_write_config_byte(dev, 0x5b, 0x21);
1348                                 if (hpt_min_rev(dev, 7)) {
1349         //      dev->sysdata = (void *) fifty_base_hpt374;
1350                                         BUG();
1351                                 } else if (hpt_min_rev(dev, 5)) {
1352                                         dev->sysdata = (void *) fifty_base_hpt372;
1353                                 } else {
1354                                         dev->sysdata = (void *) fifty_base_hpt370;
1355                                 }
1356                                 printk("HPT37X: using 50MHz internal PLL\n");
1357                                 goto init_hpt37X_done;
1358                         }
1359                 }
1360 pll_recal:
1361                 if (adjust & 1)
1362                         pll -= (adjust >> 1);
1363                 else
1364                         pll += (adjust >> 1);
1365         }
1366
1367 init_hpt37X_done:
1368         /* reset state engine */
1369         pci_write_config_byte(dev, 0x50, 0x37);
1370         pci_write_config_byte(dev, 0x54, 0x37);
1371         udelay(100);
1372 }
1373
1374 static void __init hpt366_init(struct pci_dev *dev)
1375 {
1376         unsigned int reg1       = 0;
1377         u8 drive_fast           = 0;
1378
1379         /*
1380          * Disable the "fast interrupt" prediction.
1381          */
1382         pci_read_config_byte(dev, 0x51, &drive_fast);
1383         if (drive_fast & 0x80)
1384                 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
1385         pci_read_config_dword(dev, 0x40, &reg1);
1386
1387         /* detect bus speed by looking at control reg timing: */
1388         switch((reg1 >> 8) & 7) {
1389                 case 5:
1390                         dev->sysdata = (void *) forty_base_hpt366;
1391                         break;
1392                 case 9:
1393                         dev->sysdata = (void *) twenty_five_base_hpt366;
1394                         break;
1395                 case 7:
1396                 default:
1397                         dev->sysdata = (void *) thirty_three_base_hpt366;
1398                         break;
1399         }
1400 }
1401
1402 static unsigned int __init hpt366_init_chipset(struct pci_dev *dev)
1403 {
1404         u8 test = 0;
1405
1406         if (dev->resource[PCI_ROM_RESOURCE].start)
1407                 pci_write_config_byte(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1408
1409         pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &test);
1410         if (test != (L1_CACHE_BYTES / 4))
1411                 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1412
1413         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &test);
1414         if (test != 0x78)
1415                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1416
1417         pci_read_config_byte(dev, PCI_MIN_GNT, &test);
1418         if (test != 0x08)
1419                 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1420
1421         pci_read_config_byte(dev, PCI_MAX_LAT, &test);
1422         if (test != 0x08)
1423                 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1424
1425         if (hpt_min_rev(dev, 3))
1426                 hpt37x_init(dev);
1427         else
1428                 hpt366_init(dev);
1429
1430         if (n_hpt_devs < HPT366_MAX_DEVS)
1431                 hpt_devs[n_hpt_devs++] = dev;
1432
1433 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
1434         if (!hpt366_proc) {
1435                 hpt366_proc = 1;
1436                 hpt366_display_info = &hpt366_get_info;
1437         }
1438 #endif
1439
1440         return dev->irq;
1441 }
1442
1443 static unsigned int __init hpt366_ata66_check(struct ata_channel *ch)
1444 {
1445         u8 ata66        = 0;
1446         u8 regmask      = (ch->unit) ? 0x01 : 0x02;
1447
1448         pci_read_config_byte(ch->pci_dev, 0x5a, &ata66);
1449 #ifdef DEBUG
1450         printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1451                 ata66, (ata66 & regmask) ? "33" : "66",
1452                 PCI_FUNC(ch->pci_dev->devfn));
1453 #endif
1454         return ((ata66 & regmask) ? 0 : 1);
1455 }
1456
1457 static void __init hpt366_init_channel(struct ata_channel *ch)
1458 {
1459         struct pci_dev *dev = ch->pci_dev;
1460
1461         ch->tuneproc = hpt3xx_tune_drive;
1462         ch->speedproc = hpt3xx_tune_chipset;
1463         ch->quirkproc = hpt3xx_quirkproc;
1464         ch->intrproc = hpt3xx_intrproc;
1465         ch->maskproc = hpt3xx_maskproc;
1466
1467 #ifdef HPT_SERIALIZE_IO
1468         /* serialize access to this device */
1469         if (ch->mate)
1470                 ch->serialized = ch->mate->serialized = 1;
1471 #endif
1472
1473 #ifdef CONFIG_BLK_DEV_IDEDMA
1474         if (ch->dma_base) {
1475                 if (hpt_min_rev(dev, 3)) {
1476                         byte reg5ah = 0;
1477                         pci_read_config_byte(dev, 0x5a, &reg5ah);
1478                         if (reg5ah & 0x10)      /* interrupt force enable */
1479                                 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
1480                         /*
1481                          * set up ioctl for power status.
1482                          * note: power affects both
1483                          * drives on each channel
1484                          */
1485                         ch->resetproc   = hpt3xx_reset;
1486                         ch->busproc     = hpt370_busproc;
1487
1488                         if (hpt_min_rev(dev, 7)) {
1489                                 ch->udma_stop = hpt374_udma_stop;
1490                                 ch->XXX_udma = hpt374_dmaproc;
1491                         } else if (hpt_min_rev(dev, 5)) {
1492                                 ch->udma_stop = hpt374_udma_stop;
1493                                 ch->XXX_udma = hpt374_dmaproc;
1494                         } else if (hpt_min_rev(dev, 3)) {
1495                                 ch->udma_start = hpt370_udma_start;
1496                                 ch->udma_stop = hpt370_udma_stop;
1497                                 ch->udma_timeout = hpt370_udma_timeout;
1498                                 ch->udma_irq_lost = hpt370_udma_irq_lost;
1499                                 ch->XXX_udma = hpt370_dmaproc;
1500                         }
1501                 } else if (hpt_min_rev(dev, 2)) {
1502                         ch->udma_irq_lost = hpt366_udma_irq_lost;
1503 //                      ch->resetproc = hpt3xx_reset;
1504 //                      ch->busproc = hpt3xx_tristate;
1505                         ch->XXX_udma = hpt366_dmaproc;
1506                 } else {
1507                         ch->udma_irq_lost = hpt366_udma_irq_lost;
1508 //                      ch->resetproc = hpt3xx_reset;
1509 //                      ch->busproc = hpt3xx_tristate;
1510                         ch->XXX_udma = hpt366_dmaproc;
1511                 }
1512                 if (!noautodma)
1513                         ch->autodma = 1;
1514                 else
1515                         ch->autodma = 0;
1516                 ch->highmem = 1;
1517         } else {
1518                 ch->autodma = 0;
1519                 ch->drives[0].autotune = 1;
1520                 ch->drives[1].autotune = 1;
1521         }
1522 #else
1523         ch->drives[0].autotune = 1;
1524         ch->drives[1].autotune = 1;
1525         ch->autodma = 0;
1526 #endif
1527 }
1528
1529 static void __init hpt366_init_dma(struct ata_channel *ch, unsigned long dmabase)
1530 {
1531         u8 masterdma = 0;
1532         u8 slavedma = 0;
1533         u8 dma_new = 0;
1534         u8 dma_old = inb(dmabase+2);
1535         u8 primary      = ch->unit ? 0x4b : 0x43;
1536         u8 secondary    = ch->unit ? 0x4f : 0x47;
1537
1538         dma_new = dma_old;
1539         pci_read_config_byte(ch->pci_dev, primary, &masterdma);
1540         pci_read_config_byte(ch->pci_dev, secondary, &slavedma);
1541
1542         if (masterdma & 0x30)
1543                 dma_new |= 0x20;
1544         if (slavedma & 0x30)
1545                 dma_new |= 0x40;
1546         if (dma_new != dma_old)
1547                 outb(dma_new, dmabase+2);
1548
1549         ata_init_dma(ch, dmabase);
1550 }
1551
1552
1553 /* module data table */
1554 static struct ata_pci_device chipsets[] __initdata = {
1555         {
1556                 vendor: PCI_VENDOR_ID_TTI,
1557                 device: PCI_DEVICE_ID_TTI_HPT366,
1558                 init_chipset: hpt366_init_chipset,
1559                 ata66_check: hpt366_ata66_check,
1560                 init_channel: hpt366_init_channel,
1561                 init_dma: hpt366_init_dma,
1562                 bootable: OFF_BOARD,
1563                 extra: 240,
1564                 flags: ATA_F_IRQ | ATA_F_HPTHACK | ATA_F_DMA
1565         },
1566         {
1567                 vendor: PCI_VENDOR_ID_TTI,
1568                 device: PCI_DEVICE_ID_TTI_HPT372,
1569                 init_chipset: hpt366_init_chipset,
1570                 ata66_check: hpt366_ata66_check,
1571                 init_channel: hpt366_init_channel,
1572                 init_dma: hpt366_init_dma,
1573                 bootable: OFF_BOARD,
1574                 extra: 0,
1575                 flags: ATA_F_IRQ | ATA_F_HPTHACK | ATA_F_DMA
1576         },
1577         {
1578                 vendor: PCI_VENDOR_ID_TTI,
1579                 device: PCI_DEVICE_ID_TTI_HPT374,
1580                 init_chipset: hpt366_init_chipset,
1581                 ata66_check: hpt366_ata66_check,
1582                 init_channel: hpt366_init_channel,
1583                 init_dma: hpt366_init_dma,
1584                 bootable: OFF_BOARD,
1585                 extra: 0,
1586                 flags: ATA_F_IRQ | ATA_F_HPTHACK | ATA_F_DMA
1587         },
1588 };
1589
1590 int __init init_hpt366(void)
1591 {
1592         int i;
1593
1594         for (i = 0; i < ARRAY_SIZE(chipsets); ++i) {
1595                 ata_register_chipset(&chipsets[i]);
1596         }
1597
1598     return 0;
1599 }