v2.4.8 -> v2.4.8.1
[opensuse:kernel.git] / drivers / sound / es1371.c
1 /*****************************************************************************/
2
3 /*
4  *      es1371.c  --  Creative Ensoniq ES1371.
5  *
6  *      Copyright (C) 1998-2001  Thomas Sailer (t.sailer@alumni.ethz.ch)
7  *
8  *      This program is free software; you can redistribute it and/or modify
9  *      it under the terms of the GNU General Public License as published by
10  *      the Free Software Foundation; either version 2 of the License, or
11  *      (at your option) any later version.
12  *
13  *      This program is distributed in the hope that it will be useful,
14  *      but WITHOUT ANY WARRANTY; without even the implied warranty of
15  *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  *      GNU General Public License for more details.
17  *
18  *      You should have received a copy of the GNU General Public License
19  *      along with this program; if not, write to the Free Software
20  *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  *
22  * Special thanks to Ensoniq
23  *
24  *
25  * Module command line parameters:
26  *   joystick must be set to the base I/O-Port to be used for
27  *   the gameport. Legal values are 0x200, 0x208, 0x210 and 0x218.         
28  *   The gameport is mirrored eight times.
29  *        
30  *  Supported devices:
31  *  /dev/dsp    standard /dev/dsp device, (mostly) OSS compatible
32  *  /dev/mixer  standard /dev/mixer device, (mostly) OSS compatible
33  *  /dev/dsp1   additional DAC, like /dev/dsp, but outputs to mixer "SYNTH" setting
34  *  /dev/midi   simple MIDI UART interface, no ioctl
35  *
36  *  NOTE: the card does not have any FM/Wavetable synthesizer, it is supposed
37  *  to be done in software. That is what /dev/dac is for. By now (Q2 1998)
38  *  there are several MIDI to PCM (WAV) packages, one of them is timidity.
39  *
40  *  Revision history
41  *    04.06.1998   0.1   Initial release
42  *                       Mixer stuff should be overhauled; especially optional AC97 mixer bits
43  *                       should be detected. This results in strange behaviour of some mixer
44  *                       settings, like master volume and mic.
45  *    08.06.1998   0.2   First release using Alan Cox' soundcore instead of miscdevice
46  *    03.08.1998   0.3   Do not include modversions.h
47  *                       Now mixer behaviour can basically be selected between
48  *                       "OSS documented" and "OSS actual" behaviour
49  *    31.08.1998   0.4   Fix realplayer problems - dac.count issues
50  *    27.10.1998   0.5   Fix joystick support
51  *                       -- Oliver Neukum (c188@org.chemie.uni-muenchen.de)
52  *    10.12.1998   0.6   Fix drain_dac trying to wait on not yet initialized DMA
53  *    23.12.1998   0.7   Fix a few f_file & FMODE_ bugs
54  *                       Don't wake up app until there are fragsize bytes to read/write
55  *    06.01.1999   0.8   remove the silly SA_INTERRUPT flag.
56  *                       hopefully killed the egcs section type conflict
57  *    12.03.1999   0.9   cinfo.blocks should be reset after GETxPTR ioctl.
58  *                       reported by Johan Maes <joma@telindus.be>
59  *    22.03.1999   0.10  return EAGAIN instead of EBUSY when O_NONBLOCK
60  *                       read/write cannot be executed
61  *    07.04.1999   0.11  implemented the following ioctl's: SOUND_PCM_READ_RATE, 
62  *                       SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS; 
63  *                       Alpha fixes reported by Peter Jones <pjones@redhat.com>
64  *                       Another Alpha fix (wait_src_ready in init routine)
65  *                       reported by "Ivan N. Kokshaysky" <ink@jurassic.park.msu.ru>
66  *                       Note: joystick address handling might still be wrong on archs
67  *                       other than i386
68  *    15.06.1999   0.12  Fix bad allocation bug.
69  *                       Thanks to Deti Fliegl <fliegl@in.tum.de>
70  *    28.06.1999   0.13  Add pci_set_master
71  *    03.08.1999   0.14  adapt to Linus' new __setup/__initcall
72  *                       added kernel command line option "es1371=joystickaddr"
73  *                       removed CONFIG_SOUND_ES1371_JOYPORT_BOOT kludge
74  *    10.08.1999   0.15  (Re)added S/PDIF module option for cards revision >= 4.
75  *                       Initial version by Dave Platt <dplatt@snulbug.mtview.ca.us>.
76  *                       module_init/__setup fixes
77  *    08.16.1999   0.16  Joe Cotellese <joec@ensoniq.com>
78  *                       Added detection for ES1371 revision ID so that we can
79  *                       detect the ES1373 and later parts.
80  *                       added AC97 #defines for readability
81  *                       added a /proc file system for dumping hardware state
82  *                       updated SRC and CODEC w/r functions to accomodate bugs
83  *                       in some versions of the ES137x chips.
84  *    31.08.1999   0.17  add spin_lock_init
85  *                       replaced current->state = x with set_current_state(x)
86  *    03.09.1999   0.18  change read semantics for MIDI to match
87  *                       OSS more closely; remove possible wakeup race
88  *    21.10.1999   0.19  Round sampling rates, requested by
89  *                       Kasamatsu Kenichi <t29w0267@ip.media.kyoto-u.ac.jp>
90  *    27.10.1999   0.20  Added SigmaTel 3D enhancement string
91  *                       Codec ID printing changes
92  *    28.10.1999   0.21  More waitqueue races fixed
93  *                       Joe Cotellese <joec@ensoniq.com>
94  *                       Changed PCI detection routine so we can more easily
95  *                       detect ES137x chip and derivatives.
96  *    05.01.2000   0.22  Should now work with rev7 boards; patch by
97  *                       Eric Lemar, elemar@cs.washington.edu
98  *    08.01.2000   0.23  Prevent some ioctl's from returning bad count values on underrun/overrun;
99  *                       Tim Janik's BSE (Bedevilled Sound Engine) found this
100  *    07.02.2000   0.24  Use pci_alloc_consistent and pci_register_driver
101  *    07.02.2000   0.25  Use ac97_codec
102  *    01.03.2000   0.26  SPDIF patch by Mikael Bouillot <mikael.bouillot@bigfoot.com>
103  *                       Use pci_module_init
104  *    21.11.2000   0.27  Initialize dma buffers in poll, otherwise poll may return a bogus mask
105  *    12.12.2000   0.28  More dma buffer initializations, patch from
106  *                       Tjeerd Mulder <tjeerd.mulder@fujitsu-siemens.com>
107  *    05.01.2001   0.29  Hopefully updates will not be required anymore when Creative bumps
108  *                       the CT5880 revision.
109  *                       suggested by Stephan Müller <smueller@chronox.de>
110  *    31.01.2001   0.30  Register/Unregister gameport
111  *                       Fix SETTRIGGER non OSS API conformity
112  *    14.07.2001   0.31  Add list of laptops needing amplifier control
113  */
114
115 /*****************************************************************************/
116       
117 #include <linux/version.h>
118 #include <linux/module.h>
119 #include <linux/string.h>
120 #include <linux/ioport.h>
121 #include <linux/sched.h>
122 #include <linux/delay.h>
123 #include <linux/sound.h>
124 #include <linux/slab.h>
125 #include <linux/soundcard.h>
126 #include <linux/pci.h>
127 #include <linux/init.h>
128 #include <linux/poll.h>
129 #include <linux/bitops.h>
130 #include <linux/proc_fs.h>
131 #include <linux/spinlock.h>
132 #include <linux/smp_lock.h>
133 #include <linux/ac97_codec.h>
134 #include <linux/wrapper.h>
135 #include <asm/io.h>
136 #include <asm/dma.h>
137 #include <asm/uaccess.h>
138 #include <asm/hardirq.h>
139
140 #if defined(CONFIG_INPUT_ANALOG) || defined(CONFIG_INPUT_ANALOG_MODULE)
141 #include <linux/gameport.h>
142 #else
143 struct gameport {
144         int io;
145         int size;
146 };
147
148 extern inline void gameport_register_port(struct gameport *gameport)
149 {
150 }
151
152 extern inline void gameport_unregister_port(struct gameport *gameport)
153 {
154 }
155 #endif
156
157 /* --------------------------------------------------------------------- */
158
159 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
160 #define ES1371_DEBUG
161 #define DBG(x) {}
162 /*#define DBG(x) {x}*/
163
164 /* --------------------------------------------------------------------- */
165
166 #ifndef PCI_VENDOR_ID_ENSONIQ
167 #define PCI_VENDOR_ID_ENSONIQ        0x1274    
168 #endif
169
170 #ifndef PCI_VENDOR_ID_ECTIVA
171 #define PCI_VENDOR_ID_ECTIVA         0x1102
172 #endif
173
174 #ifndef PCI_DEVICE_ID_ENSONIQ_ES1371
175 #define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371
176 #endif
177
178 #ifndef PCI_DEVICE_ID_ENSONIQ_CT5880
179 #define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880
180 #endif
181
182 #ifndef PCI_DEVICE_ID_ECTIVA_EV1938
183 #define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938
184 #endif
185
186 /* ES1371 chip ID */
187 /* This is a little confusing because all ES1371 compatible chips have the
188    same DEVICE_ID, the only thing differentiating them is the REV_ID field.
189    This is only significant if you want to enable features on the later parts.
190    Yes, I know it's stupid and why didn't we use the sub IDs?
191 */
192 #define ES1371REV_ES1373_A  0x04
193 #define ES1371REV_ES1373_B  0x06
194 #define ES1371REV_CT5880_A  0x07
195 #define CT5880REV_CT5880_C  0x02
196 #define CT5880REV_CT5880_D  0x03
197 #define ES1371REV_ES1371_B  0x09
198 #define EV1938REV_EV1938_A  0x00
199 #define ES1371REV_ES1373_8  0x08
200
201 #define ES1371_MAGIC  ((PCI_VENDOR_ID_ENSONIQ<<16)|PCI_DEVICE_ID_ENSONIQ_ES1371)
202
203 #define ES1371_EXTENT             0x40
204 #define JOY_EXTENT                8
205
206 #define ES1371_REG_CONTROL        0x00
207 #define ES1371_REG_STATUS         0x04 /* on the 5880 it is control/status */
208 #define ES1371_REG_UART_DATA      0x08
209 #define ES1371_REG_UART_STATUS    0x09
210 #define ES1371_REG_UART_CONTROL   0x09
211 #define ES1371_REG_UART_TEST      0x0a
212 #define ES1371_REG_MEMPAGE        0x0c
213 #define ES1371_REG_SRCONV         0x10
214 #define ES1371_REG_CODEC          0x14
215 #define ES1371_REG_LEGACY         0x18
216 #define ES1371_REG_SERIAL_CONTROL 0x20
217 #define ES1371_REG_DAC1_SCOUNT    0x24
218 #define ES1371_REG_DAC2_SCOUNT    0x28
219 #define ES1371_REG_ADC_SCOUNT     0x2c
220
221 #define ES1371_REG_DAC1_FRAMEADR  0xc30
222 #define ES1371_REG_DAC1_FRAMECNT  0xc34
223 #define ES1371_REG_DAC2_FRAMEADR  0xc38
224 #define ES1371_REG_DAC2_FRAMECNT  0xc3c
225 #define ES1371_REG_ADC_FRAMEADR   0xd30
226 #define ES1371_REG_ADC_FRAMECNT   0xd34
227
228 #define ES1371_FMT_U8_MONO     0
229 #define ES1371_FMT_U8_STEREO   1
230 #define ES1371_FMT_S16_MONO    2
231 #define ES1371_FMT_S16_STEREO  3
232 #define ES1371_FMT_STEREO      1
233 #define ES1371_FMT_S16         2
234 #define ES1371_FMT_MASK        3
235
236 static const unsigned sample_size[] = { 1, 2, 2, 4 };
237 static const unsigned sample_shift[] = { 0, 1, 1, 2 };
238
239 #define CTRL_RECEN_B    0x08000000  /* 1 = don't mix analog in to digital out */
240 #define CTRL_SPDIFEN_B  0x04000000
241 #define CTRL_JOY_SHIFT  24
242 #define CTRL_JOY_MASK   3
243 #define CTRL_JOY_200    0x00000000  /* joystick base address */
244 #define CTRL_JOY_208    0x01000000
245 #define CTRL_JOY_210    0x02000000
246 #define CTRL_JOY_218    0x03000000
247 #define CTRL_GPIO_IN0   0x00100000  /* general purpose inputs/outputs */
248 #define CTRL_GPIO_IN1   0x00200000
249 #define CTRL_GPIO_IN2   0x00400000
250 #define CTRL_GPIO_IN3   0x00800000
251 #define CTRL_GPIO_OUT0  0x00010000
252 #define CTRL_GPIO_OUT1  0x00020000
253 #define CTRL_GPIO_OUT2  0x00040000
254 #define CTRL_GPIO_OUT3  0x00080000
255 #define CTRL_MSFMTSEL   0x00008000  /* MPEG serial data fmt: 0 = Sony, 1 = I2S */
256 #define CTRL_SYNCRES    0x00004000  /* AC97 warm reset */
257 #define CTRL_ADCSTOP    0x00002000  /* stop ADC transfers */
258 #define CTRL_PWR_INTRM  0x00001000  /* 1 = power level ints enabled */
259 #define CTRL_M_CB       0x00000800  /* recording source: 0 = ADC, 1 = MPEG */
260 #define CTRL_CCB_INTRM  0x00000400  /* 1 = CCB "voice" ints enabled */
261 #define CTRL_PDLEV0     0x00000000  /* power down level */
262 #define CTRL_PDLEV1     0x00000100
263 #define CTRL_PDLEV2     0x00000200
264 #define CTRL_PDLEV3     0x00000300
265 #define CTRL_BREQ       0x00000080  /* 1 = test mode (internal mem test) */
266 #define CTRL_DAC1_EN    0x00000040  /* enable DAC1 */
267 #define CTRL_DAC2_EN    0x00000020  /* enable DAC2 */
268 #define CTRL_ADC_EN     0x00000010  /* enable ADC */
269 #define CTRL_UART_EN    0x00000008  /* enable MIDI uart */
270 #define CTRL_JYSTK_EN   0x00000004  /* enable Joystick port */
271 #define CTRL_XTALCLKDIS 0x00000002  /* 1 = disable crystal clock input */
272 #define CTRL_PCICLKDIS  0x00000001  /* 1 = disable PCI clock distribution */
273
274
275 #define STAT_INTR       0x80000000  /* wired or of all interrupt bits */
276 #define CSTAT_5880_AC97_RST 0x20000000 /* CT5880 Reset bit */
277 #define STAT_EN_SPDIF   0x00040000  /* enable S/PDIF circuitry */
278 #define STAT_TS_SPDIF   0x00020000  /* test S/PDIF circuitry */
279 #define STAT_TESTMODE   0x00010000  /* test ASIC */
280 #define STAT_SYNC_ERR   0x00000100  /* 1 = codec sync error */
281 #define STAT_VC         0x000000c0  /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */
282 #define STAT_SH_VC      6
283 #define STAT_MPWR       0x00000020  /* power level interrupt */
284 #define STAT_MCCB       0x00000010  /* CCB int pending */
285 #define STAT_UART       0x00000008  /* UART int pending */
286 #define STAT_DAC1       0x00000004  /* DAC1 int pending */
287 #define STAT_DAC2       0x00000002  /* DAC2 int pending */
288 #define STAT_ADC        0x00000001  /* ADC int pending */
289
290 #define USTAT_RXINT     0x80        /* UART rx int pending */
291 #define USTAT_TXINT     0x04        /* UART tx int pending */
292 #define USTAT_TXRDY     0x02        /* UART tx ready */
293 #define USTAT_RXRDY     0x01        /* UART rx ready */
294
295 #define UCTRL_RXINTEN   0x80        /* 1 = enable RX ints */
296 #define UCTRL_TXINTEN   0x60        /* TX int enable field mask */
297 #define UCTRL_ENA_TXINT 0x20        /* enable TX int */
298 #define UCTRL_CNTRL     0x03        /* control field */
299 #define UCTRL_CNTRL_SWR 0x03        /* software reset command */
300
301 /* sample rate converter */
302 #define SRC_OKSTATE        1
303
304 #define SRC_RAMADDR_MASK   0xfe000000
305 #define SRC_RAMADDR_SHIFT  25
306 #define SRC_DAC1FREEZE     (1UL << 21)
307 #define SRC_DAC2FREEZE      (1UL << 20)
308 #define SRC_ADCFREEZE      (1UL << 19)
309
310
311 #define SRC_WE             0x01000000  /* read/write control for SRC RAM */
312 #define SRC_BUSY           0x00800000  /* SRC busy */
313 #define SRC_DIS            0x00400000  /* 1 = disable SRC */
314 #define SRC_DDAC1          0x00200000  /* 1 = disable accum update for DAC1 */
315 #define SRC_DDAC2          0x00100000  /* 1 = disable accum update for DAC2 */
316 #define SRC_DADC           0x00080000  /* 1 = disable accum update for ADC2 */
317 #define SRC_CTLMASK        0x00780000
318 #define SRC_RAMDATA_MASK   0x0000ffff
319 #define SRC_RAMDATA_SHIFT  0
320
321 #define SRCREG_ADC      0x78
322 #define SRCREG_DAC1     0x70
323 #define SRCREG_DAC2     0x74
324 #define SRCREG_VOL_ADC  0x6c
325 #define SRCREG_VOL_DAC1 0x7c
326 #define SRCREG_VOL_DAC2 0x7e
327
328 #define SRCREG_TRUNC_N     0x00
329 #define SRCREG_INT_REGS    0x01
330 #define SRCREG_ACCUM_FRAC  0x02
331 #define SRCREG_VFREQ_FRAC  0x03
332
333 #define CODEC_PIRD        0x00800000  /* 0 = write AC97 register */
334 #define CODEC_PIADD_MASK  0x007f0000
335 #define CODEC_PIADD_SHIFT 16
336 #define CODEC_PIDAT_MASK  0x0000ffff
337 #define CODEC_PIDAT_SHIFT 0
338
339 #define CODEC_RDY         0x80000000  /* AC97 read data valid */
340 #define CODEC_WIP         0x40000000  /* AC97 write in progress */
341 #define CODEC_PORD        0x00800000  /* 0 = write AC97 register */
342 #define CODEC_POADD_MASK  0x007f0000
343 #define CODEC_POADD_SHIFT 16
344 #define CODEC_PODAT_MASK  0x0000ffff
345 #define CODEC_PODAT_SHIFT 0
346
347
348 #define LEGACY_JFAST      0x80000000  /* fast joystick timing */
349 #define LEGACY_FIRQ       0x01000000  /* force IRQ */
350
351 #define SCTRL_DACTEST     0x00400000  /* 1 = DAC test, test vector generation purposes */
352 #define SCTRL_P2ENDINC    0x00380000  /*  */
353 #define SCTRL_SH_P2ENDINC 19
354 #define SCTRL_P2STINC     0x00070000  /*  */
355 #define SCTRL_SH_P2STINC  16
356 #define SCTRL_R1LOOPSEL   0x00008000  /* 0 = loop mode */
357 #define SCTRL_P2LOOPSEL   0x00004000  /* 0 = loop mode */
358 #define SCTRL_P1LOOPSEL   0x00002000  /* 0 = loop mode */
359 #define SCTRL_P2PAUSE     0x00001000  /* 1 = pause mode */
360 #define SCTRL_P1PAUSE     0x00000800  /* 1 = pause mode */
361 #define SCTRL_R1INTEN     0x00000400  /* enable interrupt */
362 #define SCTRL_P2INTEN     0x00000200  /* enable interrupt */
363 #define SCTRL_P1INTEN     0x00000100  /* enable interrupt */
364 #define SCTRL_P1SCTRLD    0x00000080  /* reload sample count register for DAC1 */
365 #define SCTRL_P2DACSEN    0x00000040  /* 1 = DAC2 play back last sample when disabled */
366 #define SCTRL_R1SEB       0x00000020  /* 1 = 16bit */
367 #define SCTRL_R1SMB       0x00000010  /* 1 = stereo */
368 #define SCTRL_R1FMT       0x00000030  /* format mask */
369 #define SCTRL_SH_R1FMT    4
370 #define SCTRL_P2SEB       0x00000008  /* 1 = 16bit */
371 #define SCTRL_P2SMB       0x00000004  /* 1 = stereo */
372 #define SCTRL_P2FMT       0x0000000c  /* format mask */
373 #define SCTRL_SH_P2FMT    2
374 #define SCTRL_P1SEB       0x00000002  /* 1 = 16bit */
375 #define SCTRL_P1SMB       0x00000001  /* 1 = stereo */
376 #define SCTRL_P1FMT       0x00000003  /* format mask */
377 #define SCTRL_SH_P1FMT    0
378
379
380 /* misc stuff */
381 #define POLL_COUNT   0x1000
382 #define FMODE_DAC         4           /* slight misuse of mode_t */
383
384 /* MIDI buffer sizes */
385
386 #define MIDIINBUF  256
387 #define MIDIOUTBUF 256
388
389 #define FMODE_MIDI_SHIFT 3
390 #define FMODE_MIDI_READ  (FMODE_READ << FMODE_MIDI_SHIFT)
391 #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
392
393 #define ES1371_MODULE_NAME "es1371"
394 #define PFX ES1371_MODULE_NAME ": "
395
396 /* --------------------------------------------------------------------- */
397
398 struct es1371_state {
399         /* magic */
400         unsigned int magic;
401
402         /* list of es1371 devices */
403         struct list_head devs;
404
405         /* the corresponding pci_dev structure */
406         struct pci_dev *dev;
407
408         /* soundcore stuff */
409         int dev_audio;
410         int dev_dac;
411         int dev_midi;
412         
413         /* hardware resources */
414         unsigned long io; /* long for SPARC */
415         unsigned int irq;
416
417         /* PCI ID's */
418         u16 vendor;
419         u16 device;
420         u8 rev; /* the chip revision */
421
422         /* options */
423         int spdif_volume; /* S/PDIF output is enabled if != -1 */
424
425 #ifdef ES1371_DEBUG
426         /* debug /proc entry */
427         struct proc_dir_entry *ps;
428 #endif /* ES1371_DEBUG */
429
430         struct ac97_codec codec;
431
432         /* wave stuff */
433         unsigned ctrl;
434         unsigned sctrl;
435         unsigned dac1rate, dac2rate, adcrate;
436
437         spinlock_t lock;
438         struct semaphore open_sem;
439         mode_t open_mode;
440         wait_queue_head_t open_wait;
441
442         struct dmabuf {
443                 void *rawbuf;
444                 dma_addr_t dmaaddr;
445                 unsigned buforder;
446                 unsigned numfrag;
447                 unsigned fragshift;
448                 unsigned hwptr, swptr;
449                 unsigned total_bytes;
450                 int count;
451                 unsigned error; /* over/underrun */
452                 wait_queue_head_t wait;
453                 /* redundant, but makes calculations easier */
454                 unsigned fragsize;
455                 unsigned dmasize;
456                 unsigned fragsamples;
457                 /* OSS stuff */
458                 unsigned mapped:1;
459                 unsigned ready:1;
460                 unsigned endcleared:1;
461                 unsigned enabled:1;
462                 unsigned ossfragshift;
463                 int ossmaxfrags;
464                 unsigned subdivision;
465         } dma_dac1, dma_dac2, dma_adc;
466
467         /* midi stuff */
468         struct {
469                 unsigned ird, iwr, icnt;
470                 unsigned ord, owr, ocnt;
471                 wait_queue_head_t iwait;
472                 wait_queue_head_t owait;
473                 unsigned char ibuf[MIDIINBUF];
474                 unsigned char obuf[MIDIOUTBUF];
475         } midi;
476
477         struct gameport gameport;
478         struct semaphore sem;
479 };
480
481 /* --------------------------------------------------------------------- */
482
483 static LIST_HEAD(devs);
484
485 /* --------------------------------------------------------------------- */
486
487 static inline unsigned ld2(unsigned int x)
488 {
489         unsigned r = 0;
490         
491         if (x >= 0x10000) {
492                 x >>= 16;
493                 r += 16;
494         }
495         if (x >= 0x100) {
496                 x >>= 8;
497                 r += 8;
498         }
499         if (x >= 0x10) {
500                 x >>= 4;
501                 r += 4;
502         }
503         if (x >= 4) {
504                 x >>= 2;
505                 r += 2;
506         }
507         if (x >= 2)
508                 r++;
509         return r;
510 }
511
512 /* --------------------------------------------------------------------- */
513
514 static unsigned wait_src_ready(struct es1371_state *s)
515 {
516         unsigned int t, r;
517
518         for (t = 0; t < POLL_COUNT; t++) {
519                 if (!((r = inl(s->io + ES1371_REG_SRCONV)) & SRC_BUSY))
520                         return r;
521                 udelay(1);
522         }
523         printk(KERN_DEBUG PFX "sample rate converter timeout r = 0x%08x\n", r);
524         return r;
525 }
526
527 static unsigned src_read(struct es1371_state *s, unsigned reg)
528 {
529         unsigned int temp,i,orig;
530
531         /* wait for ready */
532         temp = wait_src_ready (s);
533
534         /* we can only access the SRC at certain times, make sure
535            we're allowed to before we read */
536            
537         orig = temp;
538         /* expose the SRC state bits */
539         outl ( (temp & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT) | 0x10000UL,
540                s->io + ES1371_REG_SRCONV);
541
542         /* now, wait for busy and the correct time to read */
543         temp = wait_src_ready (s);
544
545         if ( (temp & 0x00870000UL ) != ( SRC_OKSTATE << 16 )){
546                 /* wait for the right state */
547                 for (i=0; i<POLL_COUNT; i++){
548                         temp = inl (s->io + ES1371_REG_SRCONV);
549                         if ( (temp & 0x00870000UL ) == ( SRC_OKSTATE << 16 ))
550                                 break;
551                 }
552         }
553
554         /* hide the state bits */
555         outl ((orig & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT), s->io + ES1371_REG_SRCONV);
556         return temp;
557                         
558                 
559 }
560
561 static void src_write(struct es1371_state *s, unsigned reg, unsigned data)
562 {
563       
564         unsigned int r;
565
566         r = wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC);
567         r |= (reg << SRC_RAMADDR_SHIFT) & SRC_RAMADDR_MASK;
568         r |= (data << SRC_RAMDATA_SHIFT) & SRC_RAMDATA_MASK;
569         outl(r | SRC_WE, s->io + ES1371_REG_SRCONV);
570
571 }
572
573 /* --------------------------------------------------------------------- */
574
575 /* most of the following here is black magic */
576 static void set_adc_rate(struct es1371_state *s, unsigned rate)
577 {
578         unsigned long flags;
579         unsigned int n, truncm, freq;
580
581         if (rate > 48000)
582                 rate = 48000;
583         if (rate < 4000)
584                 rate = 4000;
585         n = rate / 3000;
586         if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
587                 n--;
588         truncm = (21 * n - 1) | 1;
589         freq = ((48000UL << 15) / rate) * n;
590         s->adcrate = (48000UL << 15) / (freq / n);
591         spin_lock_irqsave(&s->lock, flags);
592         if (rate >= 24000) {
593                 if (truncm > 239)
594                         truncm = 239;
595                 src_write(s, SRCREG_ADC+SRCREG_TRUNC_N, 
596                           (((239 - truncm) >> 1) << 9) | (n << 4));
597         } else {
598                 if (truncm > 119)
599                         truncm = 119;
600                 src_write(s, SRCREG_ADC+SRCREG_TRUNC_N, 
601                           0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
602         }               
603         src_write(s, SRCREG_ADC+SRCREG_INT_REGS, 
604                   (src_read(s, SRCREG_ADC+SRCREG_INT_REGS) & 0x00ff) |
605                   ((freq >> 5) & 0xfc00));
606         src_write(s, SRCREG_ADC+SRCREG_VFREQ_FRAC, freq & 0x7fff);
607         src_write(s, SRCREG_VOL_ADC, n << 8);
608         src_write(s, SRCREG_VOL_ADC+1, n << 8);
609         spin_unlock_irqrestore(&s->lock, flags);
610 }
611
612
613 static void set_dac1_rate(struct es1371_state *s, unsigned rate)
614 {
615         unsigned long flags;
616         unsigned int freq, r;
617
618         if (rate > 48000)
619                 rate = 48000;
620         if (rate < 4000)
621                 rate = 4000;
622         freq = ((rate << 15) + 1500) / 3000;
623         s->dac1rate = (freq * 3000 + 16384) >> 15;
624         spin_lock_irqsave(&s->lock, flags);
625         r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC)) | SRC_DDAC1;
626         outl(r, s->io + ES1371_REG_SRCONV);
627         src_write(s, SRCREG_DAC1+SRCREG_INT_REGS, 
628                   (src_read(s, SRCREG_DAC1+SRCREG_INT_REGS) & 0x00ff) |
629                   ((freq >> 5) & 0xfc00));
630         src_write(s, SRCREG_DAC1+SRCREG_VFREQ_FRAC, freq & 0x7fff);
631         r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC));
632         outl(r, s->io + ES1371_REG_SRCONV);
633         spin_unlock_irqrestore(&s->lock, flags);
634 }
635
636 static void set_dac2_rate(struct es1371_state *s, unsigned rate)
637 {
638         unsigned long flags;
639         unsigned int freq, r;
640
641         if (rate > 48000)
642                 rate = 48000;
643         if (rate < 4000)
644                 rate = 4000;
645         freq = ((rate << 15) + 1500) / 3000;
646         s->dac2rate = (freq * 3000 + 16384) >> 15;
647         spin_lock_irqsave(&s->lock, flags);
648         r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC)) | SRC_DDAC2;
649         outl(r, s->io + ES1371_REG_SRCONV);
650         src_write(s, SRCREG_DAC2+SRCREG_INT_REGS, 
651                   (src_read(s, SRCREG_DAC2+SRCREG_INT_REGS) & 0x00ff) |
652                   ((freq >> 5) & 0xfc00));
653         src_write(s, SRCREG_DAC2+SRCREG_VFREQ_FRAC, freq & 0x7fff);
654         r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC));
655         outl(r, s->io + ES1371_REG_SRCONV);
656         spin_unlock_irqrestore(&s->lock, flags);
657 }
658
659 /* --------------------------------------------------------------------- */
660
661 static void __init src_init(struct es1371_state *s)
662 {
663         unsigned int i;
664
665         /* before we enable or disable the SRC we need
666            to wait for it to become ready */
667         wait_src_ready(s);
668
669         outl(SRC_DIS, s->io + ES1371_REG_SRCONV);
670
671         for (i = 0; i < 0x80; i++)
672                 src_write(s, i, 0);
673
674         src_write(s, SRCREG_DAC1+SRCREG_TRUNC_N, 16 << 4);
675         src_write(s, SRCREG_DAC1+SRCREG_INT_REGS, 16 << 10);
676         src_write(s, SRCREG_DAC2+SRCREG_TRUNC_N, 16 << 4);
677         src_write(s, SRCREG_DAC2+SRCREG_INT_REGS, 16 << 10);
678         src_write(s, SRCREG_VOL_ADC, 1 << 12);
679         src_write(s, SRCREG_VOL_ADC+1, 1 << 12);
680         src_write(s, SRCREG_VOL_DAC1, 1 << 12);
681         src_write(s, SRCREG_VOL_DAC1+1, 1 << 12);
682         src_write(s, SRCREG_VOL_DAC2, 1 << 12);
683         src_write(s, SRCREG_VOL_DAC2+1, 1 << 12);
684         set_adc_rate(s, 22050);
685         set_dac1_rate(s, 22050);
686         set_dac2_rate(s, 22050);
687
688         /* WARNING:
689          * enabling the sample rate converter without properly programming
690          * its parameters causes the chip to lock up (the SRC busy bit will
691          * be stuck high, and I've found no way to rectify this other than
692          * power cycle)
693          */
694         wait_src_ready(s);
695         outl(0, s->io+ES1371_REG_SRCONV);
696 }
697
698 /* --------------------------------------------------------------------- */
699
700 static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
701 {
702         struct es1371_state *s = (struct es1371_state *)codec->private_data;
703         unsigned long flags;
704         unsigned t, x;
705         
706         for (t = 0; t < POLL_COUNT; t++)
707                 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
708                         break;
709         spin_lock_irqsave(&s->lock, flags);
710
711         /* save the current state for later */
712         x = wait_src_ready(s);
713
714         /* enable SRC state data in SRC mux */
715         outl((x & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC)) | 0x00010000,
716              s->io+ES1371_REG_SRCONV);
717
718         /* wait for not busy (state 0) first to avoid
719            transition states */
720         for (t=0; t<POLL_COUNT; t++){
721                 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
722                     break;
723                 udelay(1);
724         }
725         
726         /* wait for a SAFE time to write addr/data and then do it, dammit */
727         for (t=0; t<POLL_COUNT; t++){
728                 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
729                     break;
730                 udelay(1);
731         }
732
733         outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) |
734              ((data << CODEC_PODAT_SHIFT) & CODEC_PODAT_MASK), s->io+ES1371_REG_CODEC);
735
736         /* restore SRC reg */
737         wait_src_ready(s);
738         outl(x, s->io+ES1371_REG_SRCONV);
739         spin_unlock_irqrestore(&s->lock, flags);
740 }
741
742 static u16 rdcodec(struct ac97_codec *codec, u8 addr)
743 {
744         struct es1371_state *s = (struct es1371_state *)codec->private_data;
745         unsigned long flags;
746         unsigned t, x;
747
748         /* wait for WIP to go away */
749         for (t = 0; t < 0x1000; t++)
750                 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
751                         break;
752         spin_lock_irqsave(&s->lock, flags);
753
754         /* save the current state for later */
755         x = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC));
756
757         /* enable SRC state data in SRC mux */
758         outl( x | 0x00010000,
759               s->io+ES1371_REG_SRCONV);
760
761         /* wait for not busy (state 0) first to avoid
762            transition states */
763         for (t=0; t<POLL_COUNT; t++){
764                 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
765                     break;
766                 udelay(1);
767         }
768         
769         /* wait for a SAFE time to write addr/data and then do it, dammit */
770         for (t=0; t<POLL_COUNT; t++){
771                 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
772                     break;
773                 udelay(1);
774         }
775
776         outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) | CODEC_PORD, s->io+ES1371_REG_CODEC);
777         /* restore SRC reg */
778         wait_src_ready(s);
779         outl(x, s->io+ES1371_REG_SRCONV);
780         spin_unlock_irqrestore(&s->lock, flags);
781
782         /* wait for WIP again */
783         for (t = 0; t < 0x1000; t++)
784                 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
785                         break;
786         
787         /* now wait for the stinkin' data (RDY) */
788         for (t = 0; t < POLL_COUNT; t++)
789                 if ((x = inl(s->io+ES1371_REG_CODEC)) & CODEC_RDY)
790                         break;
791         
792         return ((x & CODEC_PIDAT_MASK) >> CODEC_PIDAT_SHIFT);
793 }
794
795 /* --------------------------------------------------------------------- */
796
797 static inline void stop_adc(struct es1371_state *s)
798 {
799         unsigned long flags;
800
801         spin_lock_irqsave(&s->lock, flags);
802         s->ctrl &= ~CTRL_ADC_EN;
803         outl(s->ctrl, s->io+ES1371_REG_CONTROL);
804         spin_unlock_irqrestore(&s->lock, flags);
805 }       
806
807 static inline void stop_dac1(struct es1371_state *s)
808 {
809         unsigned long flags;
810
811         spin_lock_irqsave(&s->lock, flags);
812         s->ctrl &= ~CTRL_DAC1_EN;
813         outl(s->ctrl, s->io+ES1371_REG_CONTROL);
814         spin_unlock_irqrestore(&s->lock, flags);
815 }       
816
817 static inline void stop_dac2(struct es1371_state *s)
818 {
819         unsigned long flags;
820
821         spin_lock_irqsave(&s->lock, flags);
822         s->ctrl &= ~CTRL_DAC2_EN;
823         outl(s->ctrl, s->io+ES1371_REG_CONTROL);
824         spin_unlock_irqrestore(&s->lock, flags);
825 }       
826
827 static void start_dac1(struct es1371_state *s)
828 {
829         unsigned long flags;
830         unsigned fragremain, fshift;
831
832         spin_lock_irqsave(&s->lock, flags);
833         if (!(s->ctrl & CTRL_DAC1_EN) && (s->dma_dac1.mapped || s->dma_dac1.count > 0)
834             && s->dma_dac1.ready) {
835                 s->ctrl |= CTRL_DAC1_EN;
836                 s->sctrl = (s->sctrl & ~(SCTRL_P1LOOPSEL | SCTRL_P1PAUSE | SCTRL_P1SCTRLD)) | SCTRL_P1INTEN;
837                 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
838                 fragremain = ((- s->dma_dac1.hwptr) & (s->dma_dac1.fragsize-1));
839                 fshift = sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT];
840                 if (fragremain < 2*fshift)
841                         fragremain = s->dma_dac1.fragsize;
842                 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
843                 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
844                 outl((s->dma_dac1.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
845         }
846         spin_unlock_irqrestore(&s->lock, flags);
847 }       
848
849 static void start_dac2(struct es1371_state *s)
850 {
851         unsigned long flags;
852         unsigned fragremain, fshift;
853
854         spin_lock_irqsave(&s->lock, flags);
855         if (!(s->ctrl & CTRL_DAC2_EN) && (s->dma_dac2.mapped || s->dma_dac2.count > 0)
856             && s->dma_dac2.ready) {
857                 s->ctrl |= CTRL_DAC2_EN;
858                 s->sctrl = (s->sctrl & ~(SCTRL_P2LOOPSEL | SCTRL_P2PAUSE | SCTRL_P2DACSEN | 
859                                          SCTRL_P2ENDINC | SCTRL_P2STINC)) | SCTRL_P2INTEN |
860                         (((s->sctrl & SCTRL_P2FMT) ? 2 : 1) << SCTRL_SH_P2ENDINC) | 
861                         (0 << SCTRL_SH_P2STINC);
862                 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
863                 fragremain = ((- s->dma_dac2.hwptr) & (s->dma_dac2.fragsize-1));
864                 fshift = sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT];
865                 if (fragremain < 2*fshift)
866                         fragremain = s->dma_dac2.fragsize;
867                 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
868                 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
869                 outl((s->dma_dac2.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
870         }
871         spin_unlock_irqrestore(&s->lock, flags);
872 }       
873
874 static void start_adc(struct es1371_state *s)
875 {
876         unsigned long flags;
877         unsigned fragremain, fshift;
878
879         spin_lock_irqsave(&s->lock, flags);
880         if (!(s->ctrl & CTRL_ADC_EN) && (s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
881             && s->dma_adc.ready) {
882                 s->ctrl |= CTRL_ADC_EN;
883                 s->sctrl = (s->sctrl & ~SCTRL_R1LOOPSEL) | SCTRL_R1INTEN;
884                 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
885                 fragremain = ((- s->dma_adc.hwptr) & (s->dma_adc.fragsize-1));
886                 fshift = sample_shift[(s->sctrl & SCTRL_R1FMT) >> SCTRL_SH_R1FMT];
887                 if (fragremain < 2*fshift)
888                         fragremain = s->dma_adc.fragsize;
889                 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
890                 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
891                 outl((s->dma_adc.fragsize >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
892         }
893         spin_unlock_irqrestore(&s->lock, flags);
894 }       
895
896 /* --------------------------------------------------------------------- */
897
898 #define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
899 #define DMABUF_MINORDER 1
900
901
902 static inline void dealloc_dmabuf(struct es1371_state *s, struct dmabuf *db)
903 {
904         struct page *page, *pend;
905
906         if (db->rawbuf) {
907                 /* undo marking the pages as reserved */
908                 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
909                 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
910                         mem_map_unreserve(page);
911                 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
912         }
913         db->rawbuf = NULL;
914         db->mapped = db->ready = 0;
915 }
916
917 static int prog_dmabuf(struct es1371_state *s, struct dmabuf *db, unsigned rate, unsigned fmt, unsigned reg)
918 {
919         int order;
920         unsigned bytepersec;
921         unsigned bufs;
922         struct page *page, *pend;
923
924         db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
925         if (!db->rawbuf) {
926                 db->ready = db->mapped = 0;
927                 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
928                         if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
929                                 break;
930                 if (!db->rawbuf)
931                         return -ENOMEM;
932                 db->buforder = order;
933                 /* now mark the pages as reserved; otherwise remap_page_range doesn't do what we want */
934                 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
935                 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
936                         mem_map_reserve(page);
937         }
938         fmt &= ES1371_FMT_MASK;
939         bytepersec = rate << sample_shift[fmt];
940         bufs = PAGE_SIZE << db->buforder;
941         if (db->ossfragshift) {
942                 if ((1000 << db->ossfragshift) < bytepersec)
943                         db->fragshift = ld2(bytepersec/1000);
944                 else
945                         db->fragshift = db->ossfragshift;
946         } else {
947                 db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
948                 if (db->fragshift < 3)
949                         db->fragshift = 3;
950         }
951         db->numfrag = bufs >> db->fragshift;
952         while (db->numfrag < 4 && db->fragshift > 3) {
953                 db->fragshift--;
954                 db->numfrag = bufs >> db->fragshift;
955         }
956         db->fragsize = 1 << db->fragshift;
957         if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
958                 db->numfrag = db->ossmaxfrags;
959         db->fragsamples = db->fragsize >> sample_shift[fmt];
960         db->dmasize = db->numfrag << db->fragshift;
961         memset(db->rawbuf, (fmt & ES1371_FMT_S16) ? 0 : 0x80, db->dmasize);
962         outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
963         outl(db->dmaaddr, s->io+(reg & 0xff));
964         outl((db->dmasize >> 2)-1, s->io+((reg + 4) & 0xff));
965         db->enabled = 1;
966         db->ready = 1;
967         return 0;
968 }
969
970 static inline int prog_dmabuf_adc(struct es1371_state *s)
971 {
972         stop_adc(s);
973         return prog_dmabuf(s, &s->dma_adc, s->adcrate, (s->sctrl >> SCTRL_SH_R1FMT) & ES1371_FMT_MASK, 
974                            ES1371_REG_ADC_FRAMEADR);
975 }
976
977 static inline int prog_dmabuf_dac2(struct es1371_state *s)
978 {
979         stop_dac2(s);
980         return prog_dmabuf(s, &s->dma_dac2, s->dac2rate, (s->sctrl >> SCTRL_SH_P2FMT) & ES1371_FMT_MASK, 
981                            ES1371_REG_DAC2_FRAMEADR);
982 }
983
984 static inline int prog_dmabuf_dac1(struct es1371_state *s)
985 {
986         stop_dac1(s);
987         return prog_dmabuf(s, &s->dma_dac1, s->dac1rate, (s->sctrl >> SCTRL_SH_P1FMT) & ES1371_FMT_MASK,
988                            ES1371_REG_DAC1_FRAMEADR);
989 }
990
991 static inline unsigned get_hwptr(struct es1371_state *s, struct dmabuf *db, unsigned reg)
992 {
993         unsigned hwptr, diff;
994
995         outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
996         hwptr = (inl(s->io+(reg & 0xff)) >> 14) & 0x3fffc;
997         diff = (db->dmasize + hwptr - db->hwptr) % db->dmasize;
998         db->hwptr = hwptr;
999         return diff;
1000 }
1001
1002 static inline void clear_advance(void *buf, unsigned bsize, unsigned bptr, unsigned len, unsigned char c)
1003 {
1004         if (bptr + len > bsize) {
1005                 unsigned x = bsize - bptr;
1006                 memset(((char *)buf) + bptr, c, x);
1007                 bptr = 0;
1008                 len -= x;
1009         }
1010         memset(((char *)buf) + bptr, c, len);
1011 }
1012
1013 /* call with spinlock held! */
1014 static void es1371_update_ptr(struct es1371_state *s)
1015 {
1016         int diff;
1017
1018         /* update ADC pointer */
1019         if (s->ctrl & CTRL_ADC_EN) {
1020                 diff = get_hwptr(s, &s->dma_adc, ES1371_REG_ADC_FRAMECNT);
1021                 s->dma_adc.total_bytes += diff;
1022                 s->dma_adc.count += diff;
1023                 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize) 
1024                         wake_up(&s->dma_adc.wait);
1025                 if (!s->dma_adc.mapped) {
1026                         if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
1027                                 s->ctrl &= ~CTRL_ADC_EN;
1028                                 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1029                                 s->dma_adc.error++;
1030                         }
1031                 }
1032         }
1033         /* update DAC1 pointer */
1034         if (s->ctrl & CTRL_DAC1_EN) {
1035                 diff = get_hwptr(s, &s->dma_dac1, ES1371_REG_DAC1_FRAMECNT);
1036                 s->dma_dac1.total_bytes += diff;
1037                 if (s->dma_dac1.mapped) {
1038                         s->dma_dac1.count += diff;
1039                         if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize)
1040                                 wake_up(&s->dma_dac1.wait);
1041                 } else {
1042                         s->dma_dac1.count -= diff;
1043                         if (s->dma_dac1.count <= 0) {
1044                                 s->ctrl &= ~CTRL_DAC1_EN;
1045                                 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1046                                 s->dma_dac1.error++;
1047                         } else if (s->dma_dac1.count <= (signed)s->dma_dac1.fragsize && !s->dma_dac1.endcleared) {
1048                                 clear_advance(s->dma_dac1.rawbuf, s->dma_dac1.dmasize, s->dma_dac1.swptr, 
1049                                               s->dma_dac1.fragsize, (s->sctrl & SCTRL_P1SEB) ? 0 : 0x80);
1050                                 s->dma_dac1.endcleared = 1;
1051                         }
1052                         if (s->dma_dac1.count + (signed)s->dma_dac1.fragsize <= (signed)s->dma_dac1.dmasize)
1053                                 wake_up(&s->dma_dac1.wait);
1054                 }
1055         }
1056         /* update DAC2 pointer */
1057         if (s->ctrl & CTRL_DAC2_EN) {
1058                 diff = get_hwptr(s, &s->dma_dac2, ES1371_REG_DAC2_FRAMECNT);
1059                 s->dma_dac2.total_bytes += diff;
1060                 if (s->dma_dac2.mapped) {
1061                         s->dma_dac2.count += diff;
1062                         if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize)
1063                                 wake_up(&s->dma_dac2.wait);
1064                 } else {
1065                         s->dma_dac2.count -= diff;
1066                         if (s->dma_dac2.count <= 0) {
1067                                 s->ctrl &= ~CTRL_DAC2_EN;
1068                                 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1069                                 s->dma_dac2.error++;
1070                         } else if (s->dma_dac2.count <= (signed)s->dma_dac2.fragsize && !s->dma_dac2.endcleared) {
1071                                 clear_advance(s->dma_dac2.rawbuf, s->dma_dac2.dmasize, s->dma_dac2.swptr, 
1072                                               s->dma_dac2.fragsize, (s->sctrl & SCTRL_P2SEB) ? 0 : 0x80);
1073                                 s->dma_dac2.endcleared = 1;
1074                         }
1075                         if (s->dma_dac2.count + (signed)s->dma_dac2.fragsize <= (signed)s->dma_dac2.dmasize)
1076                                 wake_up(&s->dma_dac2.wait);
1077                 }
1078         }
1079 }
1080
1081 /* hold spinlock for the following! */
1082 static void es1371_handle_midi(struct es1371_state *s)
1083 {
1084         unsigned char ch;
1085         int wake;
1086
1087         if (!(s->ctrl & CTRL_UART_EN))
1088                 return;
1089         wake = 0;
1090         while (inb(s->io+ES1371_REG_UART_STATUS) & USTAT_RXRDY) {
1091                 ch = inb(s->io+ES1371_REG_UART_DATA);
1092                 if (s->midi.icnt < MIDIINBUF) {
1093                         s->midi.ibuf[s->midi.iwr] = ch;
1094                         s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
1095                         s->midi.icnt++;
1096                 }
1097                 wake = 1;
1098         }
1099         if (wake)
1100                 wake_up(&s->midi.iwait);
1101         wake = 0;
1102         while ((inb(s->io+ES1371_REG_UART_STATUS) & USTAT_TXRDY) && s->midi.ocnt > 0) {
1103                 outb(s->midi.obuf[s->midi.ord], s->io+ES1371_REG_UART_DATA);
1104                 s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
1105                 s->midi.ocnt--;
1106                 if (s->midi.ocnt < MIDIOUTBUF-16)
1107                         wake = 1;
1108         }
1109         if (wake)
1110                 wake_up(&s->midi.owait);
1111         outb((s->midi.ocnt > 0) ? UCTRL_RXINTEN | UCTRL_ENA_TXINT : UCTRL_RXINTEN, s->io+ES1371_REG_UART_CONTROL);
1112 }
1113
1114 static void es1371_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1115 {
1116         struct es1371_state *s = (struct es1371_state *)dev_id;
1117         unsigned int intsrc, sctl;
1118         
1119         /* fastpath out, to ease interrupt sharing */
1120         intsrc = inl(s->io+ES1371_REG_STATUS);
1121         if (!(intsrc & 0x80000000))
1122                 return;
1123         spin_lock(&s->lock);
1124         /* clear audio interrupts first */
1125         sctl = s->sctrl;
1126         if (intsrc & STAT_ADC)
1127                 sctl &= ~SCTRL_R1INTEN;
1128         if (intsrc & STAT_DAC1)
1129                 sctl &= ~SCTRL_P1INTEN;
1130         if (intsrc & STAT_DAC2)
1131                 sctl &= ~SCTRL_P2INTEN;
1132         outl(sctl, s->io+ES1371_REG_SERIAL_CONTROL);
1133         outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1134         es1371_update_ptr(s);
1135         es1371_handle_midi(s);
1136         spin_unlock(&s->lock);
1137 }
1138
1139 /* --------------------------------------------------------------------- */
1140
1141 static const char invalid_magic[] = KERN_CRIT PFX "invalid magic value\n";
1142
1143 #define VALIDATE_STATE(s)                         \
1144 ({                                                \
1145         if (!(s) || (s)->magic != ES1371_MAGIC) { \
1146                 printk(invalid_magic);            \
1147                 return -ENXIO;                    \
1148         }                                         \
1149 })
1150
1151 /* --------------------------------------------------------------------- */
1152
1153 /* Conversion table for S/PDIF PCM volume emulation through the SRC */
1154 /* dB-linear table of DAC vol values; -0dB to -46.5dB with mute */
1155 static const unsigned short DACVolTable[101] =
1156 {
1157         0x1000, 0x0f2a, 0x0e60, 0x0da0, 0x0cea, 0x0c3e, 0x0b9a, 0x0aff,
1158         0x0a6d, 0x09e1, 0x095e, 0x08e1, 0x086a, 0x07fa, 0x078f, 0x072a,
1159         0x06cb, 0x0670, 0x061a, 0x05c9, 0x057b, 0x0532, 0x04ed, 0x04ab,
1160         0x046d, 0x0432, 0x03fa, 0x03c5, 0x0392, 0x0363, 0x0335, 0x030b,
1161         0x02e2, 0x02bc, 0x0297, 0x0275, 0x0254, 0x0235, 0x0217, 0x01fb,
1162         0x01e1, 0x01c8, 0x01b0, 0x0199, 0x0184, 0x0170, 0x015d, 0x014b,
1163         0x0139, 0x0129, 0x0119, 0x010b, 0x00fd, 0x00f0, 0x00e3, 0x00d7,
1164         0x00cc, 0x00c1, 0x00b7, 0x00ae, 0x00a5, 0x009c, 0x0094, 0x008c,
1165         0x0085, 0x007e, 0x0077, 0x0071, 0x006b, 0x0066, 0x0060, 0x005b,
1166         0x0057, 0x0052, 0x004e, 0x004a, 0x0046, 0x0042, 0x003f, 0x003c,
1167         0x0038, 0x0036, 0x0033, 0x0030, 0x002e, 0x002b, 0x0029, 0x0027,
1168         0x0025, 0x0023, 0x0021, 0x001f, 0x001e, 0x001c, 0x001b, 0x0019,
1169         0x0018, 0x0017, 0x0016, 0x0014, 0x0000
1170 };
1171
1172 /*
1173  * when we are in S/PDIF mode, we want to disable any analog output so
1174  * we filter the mixer ioctls 
1175  */
1176 static int mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd, unsigned long arg)
1177 {
1178         struct es1371_state *s = (struct es1371_state *)codec->private_data;
1179         int val;
1180         unsigned long flags;
1181         unsigned int left, right;
1182
1183         VALIDATE_STATE(s);
1184         /* filter mixer ioctls to catch PCM and MASTER volume when in S/PDIF mode */
1185         if (s->spdif_volume == -1)
1186                 return codec->mixer_ioctl(codec, cmd, arg);
1187         switch (cmd) {
1188         case SOUND_MIXER_WRITE_VOLUME:
1189                 return 0;
1190
1191         case SOUND_MIXER_WRITE_PCM:   /* use SRC for PCM volume */
1192                 if (get_user(val, (int *)arg))
1193                         return -EFAULT;
1194                 right = ((val >> 8)  & 0xff);
1195                 left = (val  & 0xff);
1196                 if (right > 100)
1197                         right = 100;
1198                 if (left > 100)
1199                         left = 100;
1200                 s->spdif_volume = (right << 8) | left;
1201                 spin_lock_irqsave(&s->lock, flags);
1202                 src_write(s, SRCREG_VOL_DAC2, DACVolTable[100 - left]);
1203                 src_write(s, SRCREG_VOL_DAC2+1, DACVolTable[100 - right]);
1204                 spin_unlock_irqrestore(&s->lock, flags);
1205                 return 0;
1206         
1207         case SOUND_MIXER_READ_PCM:
1208                 return put_user(s->spdif_volume, (int *)arg);
1209         }
1210         return codec->mixer_ioctl(codec, cmd, arg);
1211 }
1212
1213 /* --------------------------------------------------------------------- */
1214
1215 /*
1216  * AC97 Mixer Register to Connections mapping of the Concert 97 board
1217  *
1218  * AC97_MASTER_VOL_STEREO   Line Out
1219  * AC97_MASTER_VOL_MONO     TAD Output
1220  * AC97_PCBEEP_VOL          none
1221  * AC97_PHONE_VOL           TAD Input (mono)
1222  * AC97_MIC_VOL             MIC Input (mono)
1223  * AC97_LINEIN_VOL          Line Input (stereo)
1224  * AC97_CD_VOL              CD Input (stereo)
1225  * AC97_VIDEO_VOL           none
1226  * AC97_AUX_VOL             Aux Input (stereo)
1227  * AC97_PCMOUT_VOL          Wave Output (stereo)
1228  */
1229
1230 static int es1371_open_mixdev(struct inode *inode, struct file *file)
1231 {
1232         int minor = MINOR(inode->i_rdev);
1233         struct list_head *list;
1234         struct es1371_state *s;
1235
1236         for (list = devs.next; ; list = list->next) {
1237                 if (list == &devs)
1238                         return -ENODEV;
1239                 s = list_entry(list, struct es1371_state, devs);
1240                 if (s->codec.dev_mixer == minor)
1241                         break;
1242         }
1243         VALIDATE_STATE(s);
1244         file->private_data = s;
1245         return 0;
1246 }
1247
1248 static int es1371_release_mixdev(struct inode *inode, struct file *file)
1249 {
1250         struct es1371_state *s = (struct es1371_state *)file->private_data;
1251         
1252         VALIDATE_STATE(s);
1253         return 0;
1254 }
1255
1256 static int es1371_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1257 {
1258         struct es1371_state *s = (struct es1371_state *)file->private_data;
1259         struct ac97_codec *codec = &s->codec;
1260
1261         return mixdev_ioctl(codec, cmd, arg);
1262 }
1263
1264 static /*const*/ struct file_operations es1371_mixer_fops = {
1265         owner:          THIS_MODULE,
1266         llseek:         no_llseek,
1267         ioctl:          es1371_ioctl_mixdev,
1268         open:           es1371_open_mixdev,
1269         release:        es1371_release_mixdev,
1270 };
1271
1272 /* --------------------------------------------------------------------- */
1273
1274 static int drain_dac1(struct es1371_state *s, int nonblock)
1275 {
1276         DECLARE_WAITQUEUE(wait, current);
1277         unsigned long flags;
1278         int count, tmo;
1279         
1280         if (s->dma_dac1.mapped || !s->dma_dac1.ready)
1281                 return 0;
1282         add_wait_queue(&s->dma_dac1.wait, &wait);
1283         for (;;) {
1284                 __set_current_state(TASK_INTERRUPTIBLE);
1285                 spin_lock_irqsave(&s->lock, flags);
1286                 count = s->dma_dac1.count;
1287                 spin_unlock_irqrestore(&s->lock, flags);
1288                 if (count <= 0)
1289                         break;
1290                 if (signal_pending(current))
1291                         break;
1292                 if (nonblock) {
1293                         remove_wait_queue(&s->dma_dac1.wait, &wait);
1294                         set_current_state(TASK_RUNNING);
1295                         return -EBUSY;
1296                 }
1297                 tmo = 3 * HZ * (count + s->dma_dac1.fragsize) / 2 / s->dac1rate;
1298                 tmo >>= sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT];
1299                 if (!schedule_timeout(tmo + 1))
1300                         DBG(printk(KERN_DEBUG PFX "dac1 dma timed out??\n");)
1301         }
1302         remove_wait_queue(&s->dma_dac1.wait, &wait);
1303         set_current_state(TASK_RUNNING);
1304         if (signal_pending(current))
1305                 return -ERESTARTSYS;
1306         return 0;
1307 }
1308
1309 static int drain_dac2(struct es1371_state *s, int nonblock)
1310 {
1311         DECLARE_WAITQUEUE(wait, current);
1312         unsigned long flags;
1313         int count, tmo;
1314
1315         if (s->dma_dac2.mapped || !s->dma_dac2.ready)
1316                 return 0;
1317         add_wait_queue(&s->dma_dac2.wait, &wait);
1318         for (;;) {
1319                 __set_current_state(TASK_UNINTERRUPTIBLE);
1320                 spin_lock_irqsave(&s->lock, flags);
1321                 count = s->dma_dac2.count;
1322                 spin_unlock_irqrestore(&s->lock, flags);
1323                 if (count <= 0)
1324                         break;
1325                 if (signal_pending(current))
1326                         break;
1327                 if (nonblock) {
1328                         remove_wait_queue(&s->dma_dac2.wait, &wait);
1329                         set_current_state(TASK_RUNNING);
1330                         return -EBUSY;
1331                 }
1332                 tmo = 3 * HZ * (count + s->dma_dac2.fragsize) / 2 / s->dac2rate;
1333                 tmo >>= sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT];
1334                 if (!schedule_timeout(tmo + 1))
1335                         DBG(printk(KERN_DEBUG PFX "dac2 dma timed out??\n");)
1336         }
1337         remove_wait_queue(&s->dma_dac2.wait, &wait);
1338         set_current_state(TASK_RUNNING);
1339         if (signal_pending(current))
1340                 return -ERESTARTSYS;
1341         return 0;
1342 }
1343
1344 /* --------------------------------------------------------------------- */
1345
1346 static ssize_t es1371_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1347 {
1348         struct es1371_state *s = (struct es1371_state *)file->private_data;
1349         DECLARE_WAITQUEUE(wait, current);
1350         ssize_t ret = 0;
1351         unsigned long flags;
1352         unsigned swptr;
1353         int cnt;
1354
1355         VALIDATE_STATE(s);
1356         if (ppos != &file->f_pos)
1357                 return -ESPIPE;
1358         if (s->dma_adc.mapped)
1359                 return -ENXIO;
1360         if (!access_ok(VERIFY_WRITE, buffer, count))
1361                 return -EFAULT;
1362         down(&s->sem);
1363         if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1364                 goto out2;
1365         
1366         add_wait_queue(&s->dma_adc.wait, &wait);
1367         while (count > 0) {
1368                 spin_lock_irqsave(&s->lock, flags);
1369                 swptr = s->dma_adc.swptr;
1370                 cnt = s->dma_adc.dmasize-swptr;
1371                 if (s->dma_adc.count < cnt)
1372                         cnt = s->dma_adc.count;
1373                 if (cnt <= 0)
1374                         __set_current_state(TASK_INTERRUPTIBLE);
1375                 spin_unlock_irqrestore(&s->lock, flags);
1376                 if (cnt > count)
1377                         cnt = count;
1378                 if (cnt <= 0) {
1379                         if (s->dma_adc.enabled)
1380                                 start_adc(s);
1381                         if (file->f_flags & O_NONBLOCK) {
1382                                 if (!ret)
1383                                         ret = -EAGAIN;
1384                                 goto out;
1385                         }
1386                         up(&s->sem);
1387                         schedule();
1388                         if (signal_pending(current)) {
1389                                 if (!ret)
1390                                         ret = -ERESTARTSYS;
1391                                 goto out2;
1392                         }
1393                         down(&s->sem);
1394                         if (s->dma_adc.mapped)
1395                         {
1396                                 ret = -ENXIO;
1397                                 goto out;
1398                         }
1399                         continue;
1400                 }
1401                 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
1402                         if (!ret)
1403                                 ret = -EFAULT;
1404                         goto out;
1405                 }
1406                 swptr = (swptr + cnt) % s->dma_adc.dmasize;
1407                 spin_lock_irqsave(&s->lock, flags);
1408                 s->dma_adc.swptr = swptr;
1409                 s->dma_adc.count -= cnt;
1410                 spin_unlock_irqrestore(&s->lock, flags);
1411                 count -= cnt;
1412                 buffer += cnt;
1413                 ret += cnt;
1414                 if (s->dma_adc.enabled)
1415                         start_adc(s);
1416         }
1417 out:
1418         up(&s->sem);
1419 out2:
1420         remove_wait_queue(&s->dma_adc.wait, &wait);
1421         set_current_state(TASK_RUNNING);
1422         return ret;
1423 }
1424
1425 static ssize_t es1371_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
1426 {
1427         struct es1371_state *s = (struct es1371_state *)file->private_data;
1428         DECLARE_WAITQUEUE(wait, current);
1429         ssize_t ret;
1430         unsigned long flags;
1431         unsigned swptr;
1432         int cnt;
1433
1434         VALIDATE_STATE(s);
1435         if (ppos != &file->f_pos)
1436                 return -ESPIPE;
1437         if (s->dma_dac2.mapped)
1438                 return -ENXIO;
1439         if (!access_ok(VERIFY_READ, buffer, count))
1440                 return -EFAULT;
1441         down(&s->sem);  
1442         if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
1443                 goto out3;
1444         ret = 0;
1445         add_wait_queue(&s->dma_dac2.wait, &wait);
1446         while (count > 0) {
1447                 spin_lock_irqsave(&s->lock, flags);
1448                 if (s->dma_dac2.count < 0) {
1449                         s->dma_dac2.count = 0;
1450                         s->dma_dac2.swptr = s->dma_dac2.hwptr;
1451                 }
1452                 swptr = s->dma_dac2.swptr;
1453                 cnt = s->dma_dac2.dmasize-swptr;
1454                 if (s->dma_dac2.count + cnt > s->dma_dac2.dmasize)
1455                         cnt = s->dma_dac2.dmasize - s->dma_dac2.count;
1456                 if (cnt <= 0)
1457                         __set_current_state(TASK_INTERRUPTIBLE);
1458                 spin_unlock_irqrestore(&s->lock, flags);
1459                 if (cnt > count)
1460                         cnt = count;
1461                 if (cnt <= 0) {
1462                         if (s->dma_dac2.enabled)
1463                                 start_dac2(s);
1464                         if (file->f_flags & O_NONBLOCK) {
1465                                 if (!ret)
1466                                         ret = -EAGAIN;
1467                                 goto out;
1468                         }       
1469                         up(&s->sem);
1470                         schedule();
1471                         if (signal_pending(current)) {
1472                                 if (!ret)
1473                                         ret = -ERESTARTSYS;
1474                                 goto out2;
1475                         }
1476                         down(&s->sem);
1477                         if (s->dma_dac2.mapped)
1478                         {
1479                                 ret = -ENXIO;
1480                                 goto out;
1481                         }
1482                         continue;
1483                 }
1484                 if (copy_from_user(s->dma_dac2.rawbuf + swptr, buffer, cnt)) {
1485                         if (!ret)
1486                                 ret = -EFAULT;
1487                         goto out;
1488                 }
1489                 swptr = (swptr + cnt) % s->dma_dac2.dmasize;
1490                 spin_lock_irqsave(&s->lock, flags);
1491                 s->dma_dac2.swptr = swptr;
1492                 s->dma_dac2.count += cnt;
1493                 s->dma_dac2.endcleared = 0;
1494                 spin_unlock_irqrestore(&s->lock, flags);
1495                 count -= cnt;
1496                 buffer += cnt;
1497                 ret += cnt;
1498                 if (s->dma_dac2.enabled)
1499                         start_dac2(s);
1500         }
1501 out:
1502         up(&s->sem);
1503 out2:
1504         remove_wait_queue(&s->dma_dac2.wait, &wait);
1505 out3:   
1506         set_current_state(TASK_RUNNING);
1507         return ret;
1508 }
1509
1510 /* No kernel lock - we have our own spinlock */
1511 static unsigned int es1371_poll(struct file *file, struct poll_table_struct *wait)
1512 {
1513         struct es1371_state *s = (struct es1371_state *)file->private_data;
1514         unsigned long flags;
1515         unsigned int mask = 0;
1516
1517         VALIDATE_STATE(s);
1518         if (file->f_mode & FMODE_WRITE) {
1519                 if (!s->dma_dac2.ready && prog_dmabuf_dac2(s))
1520                         return 0;
1521                 poll_wait(file, &s->dma_dac2.wait, wait);
1522         }
1523         if (file->f_mode & FMODE_READ) {
1524                 if (!s->dma_adc.ready && prog_dmabuf_adc(s))
1525                         return 0;
1526                 poll_wait(file, &s->dma_adc.wait, wait);
1527         }
1528         spin_lock_irqsave(&s->lock, flags);
1529         es1371_update_ptr(s);
1530         if (file->f_mode & FMODE_READ) {
1531                         if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1532                                 mask |= POLLIN | POLLRDNORM;
1533         }
1534         if (file->f_mode & FMODE_WRITE) {
1535                 if (s->dma_dac2.mapped) {
1536                         if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize) 
1537                                 mask |= POLLOUT | POLLWRNORM;
1538                 } else {
1539                         if ((signed)s->dma_dac2.dmasize >= s->dma_dac2.count + (signed)s->dma_dac2.fragsize)
1540                                 mask |= POLLOUT | POLLWRNORM;
1541                 }
1542         }
1543         spin_unlock_irqrestore(&s->lock, flags);
1544         return mask;
1545 }
1546
1547 static int es1371_mmap(struct file *file, struct vm_area_struct *vma)
1548 {
1549         struct es1371_state *s = (struct es1371_state *)file->private_data;
1550         struct dmabuf *db;
1551         int ret = 0;
1552         unsigned long size;
1553
1554         VALIDATE_STATE(s);
1555         lock_kernel();
1556         down(&s->sem);
1557         
1558         if (vma->vm_flags & VM_WRITE) {
1559                 if ((ret = prog_dmabuf_dac2(s)) != 0) {
1560                         goto out;
1561                 }
1562                 db = &s->dma_dac2;
1563         } else if (vma->vm_flags & VM_READ) {
1564                 if ((ret = prog_dmabuf_adc(s)) != 0) {
1565                         goto out;
1566                 }
1567                 db = &s->dma_adc;
1568         } else {
1569                 ret = -EINVAL;
1570                 goto out;
1571         }
1572         if (vma->vm_pgoff != 0) {
1573                 ret = -EINVAL;
1574                 goto out;
1575         }
1576         size = vma->vm_end - vma->vm_start;
1577         if (size > (PAGE_SIZE << db->buforder)) {
1578                 ret = -EINVAL;
1579                 goto out;
1580         }
1581         if (remap_page_range(vma->vm_start, virt_to_phys(db->rawbuf), size, vma->vm_page_prot)) {
1582                 ret = -EAGAIN;
1583                 goto out;
1584         }
1585         db->mapped = 1;
1586 out:
1587         up(&s->sem);
1588         unlock_kernel();
1589         return ret;
1590 }
1591
1592 static int es1371_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1593 {
1594         struct es1371_state *s = (struct es1371_state *)file->private_data;
1595         unsigned long flags;
1596         audio_buf_info abinfo;
1597         count_info cinfo;
1598         int count;
1599         int val, mapped, ret;
1600
1601         VALIDATE_STATE(s);
1602         mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac2.mapped) ||
1603                 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1604         switch (cmd) {
1605         case OSS_GETVERSION:
1606                 return put_user(SOUND_VERSION, (int *)arg);
1607
1608         case SNDCTL_DSP_SYNC:
1609                 if (file->f_mode & FMODE_WRITE)
1610                         return drain_dac2(s, 0/*file->f_flags & O_NONBLOCK*/);
1611                 return 0;
1612                 
1613         case SNDCTL_DSP_SETDUPLEX:
1614                 return 0;
1615
1616         case SNDCTL_DSP_GETCAPS:
1617                 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1618                 
1619         case SNDCTL_DSP_RESET:
1620                 if (file->f_mode & FMODE_WRITE) {
1621                         stop_dac2(s);
1622                         synchronize_irq();
1623                         s->dma_dac2.swptr = s->dma_dac2.hwptr = s->dma_dac2.count = s->dma_dac2.total_bytes = 0;
1624                 }
1625                 if (file->f_mode & FMODE_READ) {
1626                         stop_adc(s);
1627                         synchronize_irq();
1628                         s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
1629                 }
1630                 return 0;
1631
1632         case SNDCTL_DSP_SPEED:
1633                 if (get_user(val, (int *)arg))
1634                         return -EFAULT;
1635                 if (val >= 0) {
1636                         if (file->f_mode & FMODE_READ) {
1637                                 stop_adc(s);
1638                                 s->dma_adc.ready = 0;
1639                                 set_adc_rate(s, val);
1640                         }
1641                         if (file->f_mode & FMODE_WRITE) {
1642                                 stop_dac2(s);
1643                                 s->dma_dac2.ready = 0;
1644                                 set_dac2_rate(s, val);
1645                         }
1646                 }
1647                 return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, (int *)arg);
1648
1649         case SNDCTL_DSP_STEREO:
1650                 if (get_user(val, (int *)arg))
1651                         return -EFAULT;
1652                 if (file->f_mode & FMODE_READ) {
1653                         stop_adc(s);
1654                         s->dma_adc.ready = 0;
1655                         spin_lock_irqsave(&s->lock, flags);
1656                         if (val)
1657                                 s->sctrl |= SCTRL_R1SMB;
1658                         else
1659                                 s->sctrl &= ~SCTRL_R1SMB;
1660                         outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1661                         spin_unlock_irqrestore(&s->lock, flags);
1662                 }
1663                 if (file->f_mode & FMODE_WRITE) {
1664                         stop_dac2(s);
1665                         s->dma_dac2.ready = 0;
1666                         spin_lock_irqsave(&s->lock, flags);
1667                         if (val)
1668                                 s->sctrl |= SCTRL_P2SMB;
1669                         else
1670                                 s->sctrl &= ~SCTRL_P2SMB;
1671                         outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1672                         spin_unlock_irqrestore(&s->lock, flags);
1673                 }
1674                 return 0;
1675
1676         case SNDCTL_DSP_CHANNELS:
1677                 if (get_user(val, (int *)arg))
1678                         return -EFAULT;
1679                 if (val != 0) {
1680                         if (file->f_mode & FMODE_READ) {
1681                                 stop_adc(s);
1682                                 s->dma_adc.ready = 0;
1683                                 spin_lock_irqsave(&s->lock, flags);
1684                                 if (val >= 2)
1685                                         s->sctrl |= SCTRL_R1SMB;
1686                                 else
1687                                         s->sctrl &= ~SCTRL_R1SMB;
1688                                 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1689                                 spin_unlock_irqrestore(&s->lock, flags);
1690                         }
1691                         if (file->f_mode & FMODE_WRITE) {
1692                                 stop_dac2(s);
1693                                 s->dma_dac2.ready = 0;
1694                                 spin_lock_irqsave(&s->lock, flags);
1695                                 if (val >= 2)
1696                                         s->sctrl |= SCTRL_P2SMB;
1697                                 else
1698                                         s->sctrl &= ~SCTRL_P2SMB;
1699                                 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1700                                 spin_unlock_irqrestore(&s->lock, flags);
1701                         }
1702                 }
1703                 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, (int *)arg);
1704                 
1705         case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1706                 return put_user(AFMT_S16_LE|AFMT_U8, (int *)arg);
1707                 
1708         case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1709                 if (get_user(val, (int *)arg))
1710                         return -EFAULT;
1711                 if (val != AFMT_QUERY) {
1712                         if (file->f_mode & FMODE_READ) {
1713                                 stop_adc(s);
1714                                 s->dma_adc.ready = 0;
1715                                 spin_lock_irqsave(&s->lock, flags);
1716                                 if (val == AFMT_S16_LE)
1717                                         s->sctrl |= SCTRL_R1SEB;
1718                                 else
1719                                         s->sctrl &= ~SCTRL_R1SEB;
1720                                 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1721                                 spin_unlock_irqrestore(&s->lock, flags);
1722                         }
1723                         if (file->f_mode & FMODE_WRITE) {
1724                                 stop_dac2(s);
1725                                 s->dma_dac2.ready = 0;
1726                                 spin_lock_irqsave(&s->lock, flags);
1727                                 if (val == AFMT_S16_LE)
1728                                         s->sctrl |= SCTRL_P2SEB;
1729                                 else
1730                                         s->sctrl &= ~SCTRL_P2SEB;
1731                                 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1732                                 spin_unlock_irqrestore(&s->lock, flags);
1733                         }
1734                 }
1735                 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ? 
1736                                 AFMT_S16_LE : AFMT_U8, (int *)arg);
1737                 
1738         case SNDCTL_DSP_POST:
1739                 return 0;
1740
1741         case SNDCTL_DSP_GETTRIGGER:
1742                 val = 0;
1743                 if (file->f_mode & FMODE_READ && s->ctrl & CTRL_ADC_EN) 
1744                         val |= PCM_ENABLE_INPUT;
1745                 if (file->f_mode & FMODE_WRITE && s->ctrl & CTRL_DAC2_EN) 
1746                         val |= PCM_ENABLE_OUTPUT;
1747                 return put_user(val, (int *)arg);
1748                 
1749         case SNDCTL_DSP_SETTRIGGER:
1750                 if (get_user(val, (int *)arg))
1751                         return -EFAULT;
1752                 if (file->f_mode & FMODE_READ) {
1753                         if (val & PCM_ENABLE_INPUT) {
1754                                 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1755                                         return ret;
1756                                 s->dma_adc.enabled = 1;
1757                                 start_adc(s);
1758                         } else {
1759                                 s->dma_adc.enabled = 0;
1760                                 stop_adc(s);
1761                         }
1762                 }
1763                 if (file->f_mode & FMODE_WRITE) {
1764                         if (val & PCM_ENABLE_OUTPUT) {
1765                                 if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
1766                                         return ret;
1767                                 s->dma_dac2.enabled = 1;
1768                                 start_dac2(s);
1769                         } else {
1770                                 s->dma_dac2.enabled = 0;
1771                                 stop_dac2(s);
1772                         }
1773                 }
1774                 return 0;
1775
1776         case SNDCTL_DSP_GETOSPACE:
1777                 if (!(file->f_mode & FMODE_WRITE))
1778                         return -EINVAL;
1779                 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
1780                         return val;
1781                 spin_lock_irqsave(&s->lock, flags);
1782                 es1371_update_ptr(s);
1783                 abinfo.fragsize = s->dma_dac2.fragsize;
1784                 count = s->dma_dac2.count;
1785                 if (count < 0)
1786                         count = 0;
1787                 abinfo.bytes = s->dma_dac2.dmasize - count;
1788                 abinfo.fragstotal = s->dma_dac2.numfrag;
1789                 abinfo.fragments = abinfo.bytes >> s->dma_dac2.fragshift;      
1790                 spin_unlock_irqrestore(&s->lock, flags);
1791                 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1792
1793         case SNDCTL_DSP_GETISPACE:
1794                 if (!(file->f_mode & FMODE_READ))
1795                         return -EINVAL;
1796                 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1797                         return val;
1798                 spin_lock_irqsave(&s->lock, flags);
1799                 es1371_update_ptr(s);
1800                 abinfo.fragsize = s->dma_adc.fragsize;
1801                 count = s->dma_adc.count;
1802                 if (count < 0)
1803                         count = 0;
1804                 abinfo.bytes = count;
1805                 abinfo.fragstotal = s->dma_adc.numfrag;
1806                 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;      
1807                 spin_unlock_irqrestore(&s->lock, flags);
1808                 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1809                 
1810         case SNDCTL_DSP_NONBLOCK:
1811                 file->f_flags |= O_NONBLOCK;
1812                 return 0;
1813
1814         case SNDCTL_DSP_GETODELAY:
1815                 if (!(file->f_mode & FMODE_WRITE))
1816                         return -EINVAL;
1817                 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
1818                         return val;
1819                 spin_lock_irqsave(&s->lock, flags);
1820                 es1371_update_ptr(s);
1821                 count = s->dma_dac2.count;
1822                 spin_unlock_irqrestore(&s->lock, flags);
1823                 if (count < 0)
1824                         count = 0;
1825                 return put_user(count, (int *)arg);
1826
1827         case SNDCTL_DSP_GETIPTR:
1828                 if (!(file->f_mode & FMODE_READ))
1829                         return -EINVAL;
1830                 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1831                         return val;
1832                 spin_lock_irqsave(&s->lock, flags);
1833                 es1371_update_ptr(s);
1834                 cinfo.bytes = s->dma_adc.total_bytes;
1835                 count = s->dma_adc.count;
1836                 if (count < 0)
1837                         count = 0;
1838                 cinfo.blocks = count >> s->dma_adc.fragshift;
1839                 cinfo.ptr = s->dma_adc.hwptr;
1840                 if (s->dma_adc.mapped)
1841                         s->dma_adc.count &= s->dma_adc.fragsize-1;
1842                 spin_unlock_irqrestore(&s->lock, flags);
1843                 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
1844
1845         case SNDCTL_DSP_GETOPTR:
1846                 if (!(file->f_mode & FMODE_WRITE))
1847                         return -EINVAL;
1848                 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
1849                         return val;
1850                 spin_lock_irqsave(&s->lock, flags);
1851                 es1371_update_ptr(s);
1852                 cinfo.bytes = s->dma_dac2.total_bytes;
1853                 count = s->dma_dac2.count;
1854                 if (count < 0)
1855                         count = 0;
1856                 cinfo.blocks = count >> s->dma_dac2.fragshift;
1857                 cinfo.ptr = s->dma_dac2.hwptr;
1858                 if (s->dma_dac2.mapped)
1859                         s->dma_dac2.count &= s->dma_dac2.fragsize-1;
1860                 spin_unlock_irqrestore(&s->lock, flags);
1861                 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
1862
1863         case SNDCTL_DSP_GETBLKSIZE:
1864                 if (file->f_mode & FMODE_WRITE) {
1865                         if ((val = prog_dmabuf_dac2(s)))
1866                                 return val;
1867                         return put_user(s->dma_dac2.fragsize, (int *)arg);
1868                 }
1869                 if ((val = prog_dmabuf_adc(s)))
1870                         return val;
1871                 return put_user(s->dma_adc.fragsize, (int *)arg);
1872
1873         case SNDCTL_DSP_SETFRAGMENT:
1874                 if (get_user(val, (int *)arg))
1875                         return -EFAULT;
1876                 if (file->f_mode & FMODE_READ) {
1877                         s->dma_adc.ossfragshift = val & 0xffff;
1878                         s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1879                         if (s->dma_adc.ossfragshift < 4)
1880                                 s->dma_adc.ossfragshift = 4;
1881                         if (s->dma_adc.ossfragshift > 15)
1882                                 s->dma_adc.ossfragshift = 15;
1883                         if (s->dma_adc.ossmaxfrags < 4)
1884                                 s->dma_adc.ossmaxfrags = 4;
1885                 }
1886                 if (file->f_mode & FMODE_WRITE) {
1887                         s->dma_dac2.ossfragshift = val & 0xffff;
1888                         s->dma_dac2.ossmaxfrags = (val >> 16) & 0xffff;
1889                         if (s->dma_dac2.ossfragshift < 4)
1890                                 s->dma_dac2.ossfragshift = 4;
1891                         if (s->dma_dac2.ossfragshift > 15)
1892                                 s->dma_dac2.ossfragshift = 15;
1893                         if (s->dma_dac2.ossmaxfrags < 4)
1894                                 s->dma_dac2.ossmaxfrags = 4;
1895                 }
1896                 return 0;
1897
1898         case SNDCTL_DSP_SUBDIVIDE:
1899                 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1900                     (file->f_mode & FMODE_WRITE && s->dma_dac2.subdivision))
1901                         return -EINVAL;
1902                 if (get_user(val, (int *)arg))
1903                         return -EFAULT;
1904                 if (val != 1 && val != 2 && val != 4)
1905                         return -EINVAL;
1906                 if (file->f_mode & FMODE_READ)
1907                         s->dma_adc.subdivision = val;
1908                 if (file->f_mode & FMODE_WRITE)
1909                         s->dma_dac2.subdivision = val;
1910                 return 0;
1911
1912         case SOUND_PCM_READ_RATE:
1913                 return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, (int *)arg);
1914
1915         case SOUND_PCM_READ_CHANNELS:
1916                 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, (int *)arg);
1917                 
1918         case SOUND_PCM_READ_BITS:
1919                 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ? 16 : 8, (int *)arg);
1920
1921         case SOUND_PCM_WRITE_FILTER:
1922         case SNDCTL_DSP_SETSYNCRO:
1923         case SOUND_PCM_READ_FILTER:
1924                 return -EINVAL;
1925                 
1926         }
1927         return mixdev_ioctl(&s->codec, cmd, arg);
1928 }
1929
1930 static int es1371_open(struct inode *inode, struct file *file)
1931 {
1932         int minor = MINOR(inode->i_rdev);
1933         DECLARE_WAITQUEUE(wait, current);
1934         unsigned long flags;
1935         struct list_head *list;
1936         struct es1371_state *s;
1937
1938         for (list = devs.next; ; list = list->next) {
1939                 if (list == &devs)
1940                         return -ENODEV;
1941                 s = list_entry(list, struct es1371_state, devs);
1942                 if (!((s->dev_audio ^ minor) & ~0xf))
1943                         break;
1944         }
1945         VALIDATE_STATE(s);
1946         file->private_data = s;
1947         /* wait for device to become free */
1948         down(&s->open_sem);
1949         while (s->open_mode & file->f_mode) {
1950                 if (file->f_flags & O_NONBLOCK) {
1951                         up(&s->open_sem);
1952                         return -EBUSY;
1953                 }
1954                 add_wait_queue(&s->open_wait, &wait);
1955                 __set_current_state(TASK_INTERRUPTIBLE);
1956                 up(&s->open_sem);
1957                 schedule();
1958                 remove_wait_queue(&s->open_wait, &wait);
1959                 set_current_state(TASK_RUNNING);
1960                 if (signal_pending(current))
1961                         return -ERESTARTSYS;
1962                 down(&s->open_sem);
1963         }
1964         if (file->f_mode & FMODE_READ) {
1965                 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
1966                 s->dma_adc.enabled = 1;
1967                 set_adc_rate(s, 8000);
1968         }
1969         if (file->f_mode & FMODE_WRITE) {
1970                 s->dma_dac2.ossfragshift = s->dma_dac2.ossmaxfrags = s->dma_dac2.subdivision = 0;
1971                 s->dma_dac2.enabled = 1;
1972                 set_dac2_rate(s, 8000);
1973         }
1974         spin_lock_irqsave(&s->lock, flags);
1975         if (file->f_mode & FMODE_READ) {
1976                 s->sctrl &= ~SCTRL_R1FMT;
1977                 if ((minor & 0xf) == SND_DEV_DSP16)
1978                         s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_R1FMT;
1979                 else
1980                         s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_R1FMT;
1981         }
1982         if (file->f_mode & FMODE_WRITE) {
1983                 s->sctrl &= ~SCTRL_P2FMT;
1984                 if ((minor & 0xf) == SND_DEV_DSP16)
1985                         s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P2FMT;
1986                 else
1987                         s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P2FMT;
1988         }
1989         outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1990         spin_unlock_irqrestore(&s->lock, flags);
1991         s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1992         up(&s->open_sem);
1993         init_MUTEX(&s->sem);
1994         return 0;
1995 }
1996
1997 static int es1371_release(struct inode *inode, struct file *file)
1998 {
1999         struct es1371_state *s = (struct es1371_state *)file->private_data;
2000
2001         VALIDATE_STATE(s);
2002         lock_kernel();
2003         if (file->f_mode & FMODE_WRITE)
2004                 drain_dac2(s, file->f_flags & O_NONBLOCK);
2005         down(&s->open_sem);
2006         if (file->f_mode & FMODE_WRITE) {
2007                 stop_dac2(s);
2008                 dealloc_dmabuf(s, &s->dma_dac2);
2009         }
2010         if (file->f_mode & FMODE_READ) {
2011                 stop_adc(s);
2012                 dealloc_dmabuf(s, &s->dma_adc);
2013         }
2014         s->open_mode &= (~file->f_mode) & (FMODE_READ|FMODE_WRITE);
2015         up(&s->open_sem);
2016         wake_up(&s->open_wait);
2017         unlock_kernel();
2018         return 0;
2019 }
2020
2021 static /*const*/ struct file_operations es1371_audio_fops = {
2022         owner:          THIS_MODULE,
2023         llseek:         no_llseek,
2024         read:           es1371_read,
2025         write:          es1371_write,
2026         poll:           es1371_poll,
2027         ioctl:          es1371_ioctl,
2028         mmap:           es1371_mmap,
2029         open:           es1371_open,
2030         release:        es1371_release,
2031 };
2032
2033 /* --------------------------------------------------------------------- */
2034
2035 static ssize_t es1371_write_dac(struct file *file, const char *buffer, size_t count, loff_t *ppos)
2036 {
2037         struct es1371_state *s = (struct es1371_state *)file->private_data;
2038         DECLARE_WAITQUEUE(wait, current);
2039         ssize_t ret = 0;
2040         unsigned long flags;
2041         unsigned swptr;
2042         int cnt;
2043
2044         VALIDATE_STATE(s);
2045         if (ppos != &file->f_pos)
2046                 return -ESPIPE;
2047         if (s->dma_dac1.mapped)
2048                 return -ENXIO;
2049         if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
2050                 return ret;
2051         if (!access_ok(VERIFY_READ, buffer, count))
2052                 return -EFAULT;
2053         add_wait_queue(&s->dma_dac1.wait, &wait);
2054         while (count > 0) {
2055                 spin_lock_irqsave(&s->lock, flags);
2056                 if (s->dma_dac1.count < 0) {
2057                         s->dma_dac1.count = 0;
2058                         s->dma_dac1.swptr = s->dma_dac1.hwptr;
2059                 }
2060                 swptr = s->dma_dac1.swptr;
2061                 cnt = s->dma_dac1.dmasize-swptr;
2062                 if (s->dma_dac1.count + cnt > s->dma_dac1.dmasize)
2063                         cnt = s->dma_dac1.dmasize - s->dma_dac1.count;
2064                 if (cnt <= 0)
2065                         __set_current_state(TASK_INTERRUPTIBLE);
2066                 spin_unlock_irqrestore(&s->lock, flags);
2067                 if (cnt > count)
2068                         cnt = count;
2069                 if (cnt <= 0) {
2070                         if (s->dma_dac1.enabled)
2071                                 start_dac1(s);
2072                         if (file->f_flags & O_NONBLOCK) {
2073                                 if (!ret)
2074                                         ret = -EAGAIN;
2075                                 break;
2076                         }
2077                         schedule();
2078                         if (signal_pending(current)) {
2079                                 if (!ret)
2080                                         ret = -ERESTARTSYS;
2081                                 break;
2082                         }
2083                         continue;
2084                 }
2085                 if (copy_from_user(s->dma_dac1.rawbuf + swptr, buffer, cnt)) {
2086                         if (!ret)
2087                                 ret = -EFAULT;
2088                         break;
2089                 }
2090                 swptr = (swptr + cnt) % s->dma_dac1.dmasize;
2091                 spin_lock_irqsave(&s->lock, flags);
2092                 s->dma_dac1.swptr = swptr;
2093                 s->dma_dac1.count += cnt;
2094                 s->dma_dac1.endcleared = 0;
2095                 spin_unlock_irqrestore(&s->lock, flags);
2096                 count -= cnt;
2097                 buffer += cnt;
2098                 ret += cnt;
2099                 if (s->dma_dac1.enabled)
2100                         start_dac1(s);
2101         }
2102         remove_wait_queue(&s->dma_dac1.wait, &wait);
2103         set_current_state(TASK_RUNNING);
2104         return ret;
2105 }
2106
2107 /* No kernel lock - we have our own spinlock */
2108 static unsigned int es1371_poll_dac(struct file *file, struct poll_table_struct *wait)
2109 {
2110         struct es1371_state *s = (struct es1371_state *)file->private_data;
2111         unsigned long flags;
2112         unsigned int mask = 0;
2113
2114         VALIDATE_STATE(s);
2115         if (!s->dma_dac1.ready && prog_dmabuf_dac1(s))
2116                 return 0;
2117         poll_wait(file, &s->dma_dac1.wait, wait);
2118         spin_lock_irqsave(&s->lock, flags);
2119         es1371_update_ptr(s);
2120         if (s->dma_dac1.mapped) {
2121                 if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize)
2122                         mask |= POLLOUT | POLLWRNORM;
2123         } else {
2124                 if ((signed)s->dma_dac1.dmasize >= s->dma_dac1.count + (signed)s->dma_dac1.fragsize)
2125                         mask |= POLLOUT | POLLWRNORM;
2126         }
2127         spin_unlock_irqrestore(&s->lock, flags);
2128         return mask;
2129 }
2130
2131 static int es1371_mmap_dac(struct file *file, struct vm_area_struct *vma)
2132 {
2133         struct es1371_state *s = (struct es1371_state *)file->private_data;
2134         int ret;
2135         unsigned long size;
2136
2137         VALIDATE_STATE(s);
2138         if (!(vma->vm_flags & VM_WRITE))
2139                 return -EINVAL;
2140         lock_kernel();
2141         if ((ret = prog_dmabuf_dac1(s)) != 0)
2142                 goto out;
2143         ret = -EINVAL;
2144         if (vma->vm_pgoff != 0)
2145                 goto out;
2146         size = vma->vm_end - vma->vm_start;
2147         if (size > (PAGE_SIZE << s->dma_dac1.buforder))
2148                 goto out;
2149         ret = -EAGAIN;
2150         if (remap_page_range(vma->vm_start, virt_to_phys(s->dma_dac1.rawbuf), size, vma->vm_page_prot))
2151                 goto out;
2152         s->dma_dac1.mapped = 1;
2153         ret = 0;
2154 out:
2155         unlock_kernel();
2156         return ret;
2157 }
2158
2159 static int es1371_ioctl_dac(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
2160 {
2161         struct es1371_state *s = (struct es1371_state *)file->private_data;
2162         unsigned long flags;
2163         audio_buf_info abinfo;
2164         count_info cinfo;
2165         int count;
2166         int val, ret;
2167
2168         VALIDATE_STATE(s);
2169         switch (cmd) {
2170         case OSS_GETVERSION:
2171                 return put_user(SOUND_VERSION, (int *)arg);
2172
2173         case SNDCTL_DSP_SYNC:
2174                 return drain_dac1(s, 0/*file->f_flags & O_NONBLOCK*/);
2175                 
2176         case SNDCTL_DSP_SETDUPLEX:
2177                 return -EINVAL;
2178
2179         case SNDCTL_DSP_GETCAPS:
2180                 return put_user(DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
2181                 
2182         case SNDCTL_DSP_RESET:
2183                 stop_dac1(s);
2184                 synchronize_irq();
2185                 s->dma_dac1.swptr = s->dma_dac1.hwptr = s->dma_dac1.count = s->dma_dac1.total_bytes = 0;
2186                 return 0;
2187
2188         case SNDCTL_DSP_SPEED:
2189                 if (get_user(val, (int *)arg))
2190                         return -EFAULT;
2191                 if (val >= 0) {
2192                         stop_dac1(s);
2193                         s->dma_dac1.ready = 0;
2194                         set_dac1_rate(s, val);
2195                 }
2196                 return put_user(s->dac1rate, (int *)arg);
2197
2198         case SNDCTL_DSP_STEREO:
2199                 if (get_user(val, (int *)arg))
2200                         return -EFAULT;
2201                 stop_dac1(s);
2202                 s->dma_dac1.ready = 0;
2203                 spin_lock_irqsave(&s->lock, flags);
2204                 if (val)
2205                         s->sctrl |= SCTRL_P1SMB;
2206                 else
2207                         s->sctrl &= ~SCTRL_P1SMB;
2208                 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2209                 spin_unlock_irqrestore(&s->lock, flags);
2210                 return 0;
2211
2212         case SNDCTL_DSP_CHANNELS:
2213                 if (get_user(val, (int *)arg))
2214                         return -EFAULT;
2215                 if (val != 0) {
2216                         stop_dac1(s);
2217                         s->dma_dac1.ready = 0;
2218                         spin_lock_irqsave(&s->lock, flags);
2219                         if (val >= 2)
2220                                 s->sctrl |= SCTRL_P1SMB;
2221                         else
2222                                 s->sctrl &= ~SCTRL_P1SMB;
2223                         outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2224                         spin_unlock_irqrestore(&s->lock, flags);
2225                 }
2226                 return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, (int *)arg);
2227                 
2228         case SNDCTL_DSP_GETFMTS: /* Returns a mask */
2229                 return put_user(AFMT_S16_LE|AFMT_U8, (int *)arg);
2230                 
2231         case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
2232                 if (get_user(val, (int *)arg))
2233                         return -EFAULT;
2234                 if (val != AFMT_QUERY) {
2235                         stop_dac1(s);
2236                         s->dma_dac1.ready = 0;
2237                         spin_lock_irqsave(&s->lock, flags);
2238                         if (val == AFMT_S16_LE)
2239                                 s->sctrl |= SCTRL_P1SEB;
2240                         else
2241                                 s->sctrl &= ~SCTRL_P1SEB;
2242                         outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2243                         spin_unlock_irqrestore(&s->lock, flags);
2244                 }
2245                 return put_user((s->sctrl & SCTRL_P1SEB) ? AFMT_S16_LE : AFMT_U8, (int *)arg);
2246
2247         case SNDCTL_DSP_POST:
2248                 return 0;
2249
2250         case SNDCTL_DSP_GETTRIGGER:
2251                 return put_user((s->ctrl & CTRL_DAC1_EN) ? PCM_ENABLE_OUTPUT : 0, (int *)arg);
2252                                                 
2253         case SNDCTL_DSP_SETTRIGGER:
2254                 if (get_user(val, (int *)arg))
2255                         return -EFAULT;
2256                 if (val & PCM_ENABLE_OUTPUT) {
2257                         if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
2258                                 return ret;
2259                         s->dma_dac1.enabled = 1;
2260                         start_dac1(s);
2261                 } else {
2262                         s->dma_dac1.enabled = 0;
2263                         stop_dac1(s);
2264                 }
2265                 return 0;
2266
2267         case SNDCTL_DSP_GETOSPACE:
2268                 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
2269                         return val;
2270                 spin_lock_irqsave(&s->lock, flags);
2271                 es1371_update_ptr(s);
2272                 abinfo.fragsize = s->dma_dac1.fragsize;
2273                 count = s->dma_dac1.count;
2274                 if (count < 0)
2275                         count = 0;
2276                 abinfo.bytes = s->dma_dac1.dmasize - count;
2277                 abinfo.fragstotal = s->dma_dac1.numfrag;
2278                 abinfo.fragments = abinfo.bytes >> s->dma_dac1.fragshift;      
2279                 spin_unlock_irqrestore(&s->lock, flags);
2280                 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2281
2282         case SNDCTL_DSP_NONBLOCK:
2283                 file->f_flags |= O_NONBLOCK;
2284                 return 0;
2285
2286         case SNDCTL_DSP_GETODELAY:
2287                 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
2288                         return val;
2289                 spin_lock_irqsave(&s->lock, flags);
2290                 es1371_update_ptr(s);
2291                 count = s->dma_dac1.count;
2292                 spin_unlock_irqrestore(&s->lock, flags);
2293                 if (count < 0)
2294                         count = 0;
2295                 return put_user(count, (int *)arg);
2296
2297         case SNDCTL_DSP_GETOPTR:
2298                 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
2299                         return val;
2300                 spin_lock_irqsave(&s->lock, flags);
2301                 es1371_update_ptr(s);
2302                 cinfo.bytes = s->dma_dac1.total_bytes;
2303                 count = s->dma_dac1.count;
2304                 if (count < 0)
2305                         count = 0;
2306                 cinfo.blocks = count >> s->dma_dac1.fragshift;
2307                 cinfo.ptr = s->dma_dac1.hwptr;
2308                 if (s->dma_dac1.mapped)
2309                         s->dma_dac1.count &= s->dma_dac1.fragsize-1;
2310                 spin_unlock_irqrestore(&s->lock, flags);
2311                 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
2312
2313         case SNDCTL_DSP_GETBLKSIZE:
2314                 if ((val = prog_dmabuf_dac1(s)))
2315                         return val;
2316                 return put_user(s->dma_dac1.fragsize, (int *)arg);
2317
2318         case SNDCTL_DSP_SETFRAGMENT:
2319                 if (get_user(val, (int *)arg))
2320                         return -EFAULT;
2321                 s->dma_dac1.ossfragshift = val & 0xffff;
2322                 s->dma_dac1.ossmaxfrags = (val >> 16) & 0xffff;
2323                 if (s->dma_dac1.ossfragshift < 4)
2324                         s->dma_dac1.ossfragshift = 4;
2325                 if (s->dma_dac1.ossfragshift > 15)
2326                         s->dma_dac1.ossfragshift = 15;
2327                 if (s->dma_dac1.ossmaxfrags < 4)
2328                         s->dma_dac1.ossmaxfrags = 4;
2329                 return 0;
2330
2331         case SNDCTL_DSP_SUBDIVIDE:
2332                 if (s->dma_dac1.subdivision)
2333                         return -EINVAL;
2334                 if (get_user(val, (int *)arg))
2335                         return -EFAULT;
2336                 if (val != 1 && val != 2 && val != 4)
2337                         return -EINVAL;
2338                 s->dma_dac1.subdivision = val;
2339                 return 0;
2340
2341         case SOUND_PCM_READ_RATE:
2342                 return put_user(s->dac1rate, (int *)arg);
2343
2344         case SOUND_PCM_READ_CHANNELS:
2345                 return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, (int *)arg);
2346
2347         case SOUND_PCM_READ_BITS:
2348                 return put_user((s->sctrl & SCTRL_P1SEB) ? 16 : 8, (int *)arg);
2349
2350         case SOUND_PCM_WRITE_FILTER:
2351         case SNDCTL_DSP_SETSYNCRO:
2352         case SOUND_PCM_READ_FILTER:
2353                 return -EINVAL;
2354                 
2355         }
2356         return mixdev_ioctl(&s->codec, cmd, arg);
2357 }
2358
2359 static int es1371_open_dac(struct inode *inode, struct file *file)
2360 {
2361         int minor = MINOR(inode->i_rdev);
2362         DECLARE_WAITQUEUE(wait, current);
2363         unsigned long flags;
2364         struct list_head *list;
2365         struct es1371_state *s;
2366
2367         for (list = devs.next; ; list = list->next) {
2368                 if (list == &devs)
2369                         return -ENODEV;
2370                 s = list_entry(list, struct es1371_state, devs);
2371                 if (!((s->dev_dac ^ minor) & ~0xf))
2372                         break;
2373         }
2374         VALIDATE_STATE(s);
2375         /* we allow opening with O_RDWR, most programs do it although they will only write */
2376 #if 0
2377         if (file->f_mode & FMODE_READ)
2378                 return -EPERM;
2379 #endif
2380         if (!(file->f_mode & FMODE_WRITE))
2381                 return -EINVAL;
2382         file->private_data = s;
2383         /* wait for device to become free */
2384         down(&s->open_sem);
2385         while (s->open_mode & FMODE_DAC) {
2386                 if (file->f_flags & O_NONBLOCK) {
2387                         up(&s->open_sem);
2388                         return -EBUSY;
2389                 }
2390                 add_wait_queue(&s->open_wait, &wait);
2391                 __set_current_state(TASK_INTERRUPTIBLE);
2392                 up(&s->open_sem);
2393                 schedule();
2394                 remove_wait_queue(&s->open_wait, &wait);
2395                 set_current_state(TASK_RUNNING);
2396                 if (signal_pending(current))
2397                         return -ERESTARTSYS;
2398                 down(&s->open_sem);
2399         }
2400         s->dma_dac1.ossfragshift = s->dma_dac1.ossmaxfrags = s->dma_dac1.subdivision = 0;
2401         s->dma_dac1.enabled = 1;
2402         set_dac1_rate(s, 8000);
2403         spin_lock_irqsave(&s->lock, flags);
2404         s->sctrl &= ~SCTRL_P1FMT;
2405         if ((minor & 0xf) == SND_DEV_DSP16)
2406                 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P1FMT;
2407         else
2408                 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P1FMT;
2409         outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2410         spin_unlock_irqrestore(&s->lock, flags);
2411         s->open_mode |= FMODE_DAC;
2412         up(&s->open_sem);
2413         return 0;
2414 }
2415
2416 static int es1371_release_dac(struct inode *inode, struct file *file)
2417 {
2418         struct es1371_state *s = (struct es1371_state *)file->private_data;
2419
2420         VALIDATE_STATE(s);
2421         lock_kernel();
2422         drain_dac1(s, file->f_flags & O_NONBLOCK);
2423         down(&s->open_sem);
2424         stop_dac1(s);
2425         dealloc_dmabuf(s, &s->dma_dac1);
2426         s->open_mode &= ~FMODE_DAC;
2427         up(&s->open_sem);
2428         wake_up(&s->open_wait);
2429         unlock_kernel();
2430         return 0;
2431 }
2432
2433 static /*const*/ struct file_operations es1371_dac_fops = {
2434         owner:          THIS_MODULE,
2435         llseek:         no_llseek,
2436         write:          es1371_write_dac,
2437         poll:           es1371_poll_dac,
2438         ioctl:          es1371_ioctl_dac,
2439         mmap:           es1371_mmap_dac,
2440         open:           es1371_open_dac,
2441         release:        es1371_release_dac,
2442 };
2443
2444 /* --------------------------------------------------------------------- */
2445
2446 static ssize_t es1371_midi_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
2447 {
2448         struct es1371_state *s = (struct es1371_state *)file->private_data;
2449         DECLARE_WAITQUEUE(wait, current);
2450         ssize_t ret;
2451         unsigned long flags;
2452         unsigned ptr;
2453         int cnt;
2454
2455         VALIDATE_STATE(s);
2456         if (ppos != &file->f_pos)
2457                 return -ESPIPE;
2458         if (!access_ok(VERIFY_WRITE, buffer, count))
2459                 return -EFAULT;
2460         if (count == 0)
2461                 return 0;
2462         ret = 0;
2463         add_wait_queue(&s->midi.iwait, &wait);
2464         while (count > 0) {
2465                 spin_lock_irqsave(&s->lock, flags);
2466                 ptr = s->midi.ird;
2467                 cnt = MIDIINBUF - ptr;
2468                 if (s->midi.icnt < cnt)
2469                         cnt = s->midi.icnt;
2470                 if (cnt <= 0)
2471                         __set_current_state(TASK_INTERRUPTIBLE);
2472                 spin_unlock_irqrestore(&s->lock, flags);
2473                 if (cnt > count)
2474                         cnt = count;
2475                 if (cnt <= 0) {
2476                         if (file->f_flags & O_NONBLOCK) {
2477                                 if (!ret)
2478                                         ret = -EAGAIN;
2479                                 break;
2480                         }
2481                         schedule();
2482                         if (signal_pending(current)) {
2483                                 if (!ret)
2484                                         ret = -ERESTARTSYS;
2485                                 break;
2486                         }
2487                         continue;
2488                 }
2489                 if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) {
2490                         if (!ret)
2491                                 ret = -EFAULT;
2492                         break;
2493                 }
2494                 ptr = (ptr + cnt) % MIDIINBUF;
2495                 spin_lock_irqsave(&s->lock, flags);
2496                 s->midi.ird = ptr;
2497                 s->midi.icnt -= cnt;
2498                 spin_unlock_irqrestore(&s->lock, flags);
2499                 count -= cnt;
2500                 buffer += cnt;
2501                 ret += cnt;
2502                 break;
2503         }
2504         __set_current_state(TASK_RUNNING);
2505         remove_wait_queue(&s->midi.iwait, &wait);
2506         return ret;
2507 }
2508
2509 static ssize_t es1371_midi_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
2510 {
2511         struct es1371_state *s = (struct es1371_state *)file->private_data;
2512         DECLARE_WAITQUEUE(wait, current);
2513         ssize_t ret;
2514         unsigned long flags;
2515         unsigned ptr;
2516         int cnt;
2517
2518         VALIDATE_STATE(s);
2519         if (ppos != &file->f_pos)
2520                 return -ESPIPE;
2521         if (!access_ok(VERIFY_READ, buffer, count))
2522                 return -EFAULT;
2523         if (count == 0)
2524                 return 0;
2525         ret = 0;
2526         add_wait_queue(&s->midi.owait, &wait);
2527         while (count > 0) {
2528                 spin_lock_irqsave(&s->lock, flags);
2529                 ptr = s->midi.owr;
2530                 cnt = MIDIOUTBUF - ptr;
2531                 if (s->midi.ocnt + cnt > MIDIOUTBUF)
2532                         cnt = MIDIOUTBUF - s->midi.ocnt;
2533                 if (cnt <= 0) {
2534                         __set_current_state(TASK_INTERRUPTIBLE);
2535                         es1371_handle_midi(s);
2536                 }
2537                 spin_unlock_irqrestore(&s->lock, flags);
2538                 if (cnt > count)
2539                         cnt = count;
2540                 if (cnt <= 0) {
2541                         if (file->f_flags & O_NONBLOCK) {
2542                                 if (!ret)
2543                                         ret = -EAGAIN;
2544                                 break;
2545                         }
2546                         schedule();
2547                         if (signal_pending(current)) {
2548                                 if (!ret)
2549                                         ret = -ERESTARTSYS;
2550                                 break;
2551                         }
2552                         continue;
2553                 }
2554                 if (copy_from_user(s->midi.obuf + ptr, buffer, cnt)) {
2555                         if (!ret)
2556                                 ret = -EFAULT;
2557                         break;
2558                 }
2559                 ptr = (ptr + cnt) % MIDIOUTBUF;
2560                 spin_lock_irqsave(&s->lock, flags);
2561                 s->midi.owr = ptr;
2562                 s->midi.ocnt += cnt;
2563                 spin_unlock_irqrestore(&s->lock, flags);
2564                 count -= cnt;
2565                 buffer += cnt;
2566                 ret += cnt;
2567                 spin_lock_irqsave(&s->lock, flags);
2568                 es1371_handle_midi(s);
2569                 spin_unlock_irqrestore(&s->lock, flags);
2570         }
2571         __set_current_state(TASK_RUNNING);
2572         remove_wait_queue(&s->midi.owait, &wait);
2573         return ret;
2574 }
2575
2576 /* No kernel lock - we have our own spinlock */
2577 static unsigned int es1371_midi_poll(struct file *file, struct poll_table_struct *wait)
2578 {
2579         struct es1371_state *s = (struct es1371_state *)file->private_data;
2580         unsigned long flags;
2581         unsigned int mask = 0;
2582
2583         VALIDATE_STATE(s);
2584         if (file->f_mode & FMODE_WRITE)
2585                 poll_wait(file, &s->midi.owait, wait);
2586         if (file->f_mode & FMODE_READ)
2587                 poll_wait(file, &s->midi.iwait, wait);
2588         spin_lock_irqsave(&s->lock, flags);
2589         if (file->f_mode & FMODE_READ) {
2590                 if (s->midi.icnt > 0)
2591                         mask |= POLLIN | POLLRDNORM;
2592         }
2593         if (file->f_mode & FMODE_WRITE) {
2594                 if (s->midi.ocnt < MIDIOUTBUF)
2595                         mask |= POLLOUT | POLLWRNORM;
2596         }
2597         spin_unlock_irqrestore(&s->lock, flags);
2598         return mask;
2599 }
2600
2601 static int es1371_midi_open(struct inode *inode, struct file *file)
2602 {
2603         int minor = MINOR(inode->i_rdev);
2604         DECLARE_WAITQUEUE(wait, current);
2605         unsigned long flags;
2606         struct list_head *list;
2607         struct es1371_state *s;
2608
2609         for (list = devs.next; ; list = list->next) {
2610                 if (list == &devs)
2611                         return -ENODEV;
2612                 s = list_entry(list, struct es1371_state, devs);
2613                 if (s->dev_midi == minor)
2614                         break;
2615         }
2616         VALIDATE_STATE(s);
2617         file->private_data = s;
2618         /* wait for device to become free */
2619         down(&s->open_sem);
2620         while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
2621                 if (file->f_flags & O_NONBLOCK) {
2622                         up(&s->open_sem);
2623                         return -EBUSY;
2624                 }
2625                 add_wait_queue(&s->open_wait, &wait);
2626                 __set_current_state(TASK_INTERRUPTIBLE);
2627                 up(&s->open_sem);
2628                 schedule();
2629                 remove_wait_queue(&s->open_wait, &wait);
2630                 set_current_state(TASK_RUNNING);
2631                 if (signal_pending(current))
2632                         return -ERESTARTSYS;
2633                 down(&s->open_sem);
2634         }
2635         spin_lock_irqsave(&s->lock, flags);
2636         if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
2637                 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2638                 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
2639                 outb(UCTRL_CNTRL_SWR, s->io+ES1371_REG_UART_CONTROL);
2640                 outb(0, s->io+ES1371_REG_UART_CONTROL);
2641                 outb(0, s->io+ES1371_REG_UART_TEST);
2642         }
2643         if (file->f_mode & FMODE_READ) {
2644                 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2645         }
2646         if (file->f_mode & FMODE_WRITE) {
2647                 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
2648  &n