v2.4.8 -> v2.4.8.1
[opensuse:kernel.git] / drivers / scsi / aic7xxx / aic7xxx.c
1 /*
2  * Core routines and tables shareable across OS platforms.
3  *
4  * Copyright (c) 1994-2001 Justin T. Gibbs.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions, and the following disclaimer,
12  *    without modification.
13  * 2. The name of the author may not be used to endorse or promote products
14  *    derived from this software without specific prior written permission.
15  *
16  * Alternatively, this software may be distributed under the terms of the
17  * GNU Public License ("GPL").
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
23  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29  * SUCH DAMAGE.
30  *
31  * $Id: //depot/src/aic7xxx/aic7xxx.c#44 $
32  *
33  * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.61 2000/11/13 03:35:43 gibbs Exp $
34  */
35
36 #include "aic7xxx_osm.h"
37 #include "aic7xxx_inline.h"
38 #include "aicasm/aicasm_insformat.h"
39
40 /****************************** Softc Data ************************************/
41 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq);
42
43 /***************************** Lookup Tables **********************************/
44 char *ahc_chip_names[] =
45 {
46         "NONE",
47         "aic7770",
48         "aic7850",
49         "aic7855",
50         "aic7859",
51         "aic7860",
52         "aic7870",
53         "aic7880",
54         "aic7895",
55         "aic7895C",
56         "aic7890/91",
57         "aic7896/97",
58         "aic7892",
59         "aic7899"
60 };
61 static const u_int num_chip_names = NUM_ELEMENTS(ahc_chip_names);
62
63 /*
64  * Hardware error codes.
65  */
66 struct ahc_hard_error_entry {
67         uint8_t errno;
68         char *errmesg;
69 };
70
71 static struct ahc_hard_error_entry ahc_hard_errors[] = {
72         { ILLHADDR,     "Illegal Host Access" },
73         { ILLSADDR,     "Illegal Sequencer Address referrenced" },
74         { ILLOPCODE,    "Illegal Opcode in sequencer program" },
75         { SQPARERR,     "Sequencer Parity Error" },
76         { DPARERR,      "Data-path Parity Error" },
77         { MPARERR,      "Scratch or SCB Memory Parity Error" },
78         { PCIERRSTAT,   "PCI Error detected" },
79         { CIOPARERR,    "CIOBUS Parity Error" },
80 };
81 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors);
82
83 static struct ahc_phase_table_entry ahc_phase_table[] =
84 {
85         { P_DATAOUT,    MSG_NOOP,               "in Data-out phase"     },
86         { P_DATAIN,     MSG_INITIATOR_DET_ERR,  "in Data-in phase"      },
87         { P_DATAOUT_DT, MSG_NOOP,               "in DT Data-out phase"  },
88         { P_DATAIN_DT,  MSG_INITIATOR_DET_ERR,  "in DT Data-in phase"   },
89         { P_COMMAND,    MSG_NOOP,               "in Command phase"      },
90         { P_MESGOUT,    MSG_NOOP,               "in Message-out phase"  },
91         { P_STATUS,     MSG_INITIATOR_DET_ERR,  "in Status phase"       },
92         { P_MESGIN,     MSG_PARITY_ERROR,       "in Message-in phase"   },
93         { P_BUSFREE,    MSG_NOOP,               "while idle"            },
94         { 0,            MSG_NOOP,               "in unknown phase"      }
95 };
96
97 /*
98  * In most cases we only wish to itterate over real phases, so
99  * exclude the last element from the count.
100  */
101 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1;
102
103 /*
104  * Valid SCSIRATE values.  (p. 3-17)
105  * Provides a mapping of tranfer periods in ns to the proper value to
106  * stick in the scsixfer reg.
107  */
108 static struct ahc_syncrate ahc_syncrates[] =
109 {
110       /* ultra2    fast/ultra  period     rate */
111         { 0x42,      0x000,      9,      "80.0" },
112         { 0x03,      0x000,     10,      "40.0" },
113         { 0x04,      0x000,     11,      "33.0" },
114         { 0x05,      0x100,     12,      "20.0" },
115         { 0x06,      0x110,     15,      "16.0" },
116         { 0x07,      0x120,     18,      "13.4" },
117         { 0x08,      0x000,     25,      "10.0" },
118         { 0x19,      0x010,     31,      "8.0"  },
119         { 0x1a,      0x020,     37,      "6.67" },
120         { 0x1b,      0x030,     43,      "5.7"  },
121         { 0x1c,      0x040,     50,      "5.0"  },
122         { 0x00,      0x050,     56,      "4.4"  },
123         { 0x00,      0x060,     62,      "4.0"  },
124         { 0x00,      0x070,     68,      "3.6"  },
125         { 0x00,      0x000,      0,      NULL   }
126 };
127
128 /* Our Sequencer Program */
129 #include "aic7xxx_seq.h"
130
131 /**************************** Function Declarations ***************************/
132 static struct ahc_tmode_tstate*
133                         ahc_alloc_tstate(struct ahc_softc *ahc,
134                                          u_int scsi_id, char channel);
135 #ifdef AHC_TARGET_MODE
136 static void             ahc_free_tstate(struct ahc_softc *ahc,
137                                         u_int scsi_id, char channel, int force);
138 #endif
139 static struct ahc_syncrate*
140                         ahc_devlimited_syncrate(struct ahc_softc *ahc,
141                                                 struct ahc_initiator_tinfo *,
142                                                 u_int *period,
143                                                 u_int *ppr_options,
144                                                 role_t role);
145 static void             ahc_update_pending_scbs(struct ahc_softc *ahc);
146 static void             ahc_fetch_devinfo(struct ahc_softc *ahc,
147                                           struct ahc_devinfo *devinfo);
148 static void             ahc_scb_devinfo(struct ahc_softc *ahc,
149                                         struct ahc_devinfo *devinfo,
150                                         struct scb *scb);
151 static void             ahc_assert_atn(struct ahc_softc *ahc);
152 static void             ahc_setup_initiator_msgout(struct ahc_softc *ahc,
153                                                    struct ahc_devinfo *devinfo,
154                                                    struct scb *scb);
155 static void             ahc_build_transfer_msg(struct ahc_softc *ahc,
156                                                struct ahc_devinfo *devinfo);
157 static void             ahc_construct_sdtr(struct ahc_softc *ahc,
158                                            struct ahc_devinfo *devinfo,
159                                            u_int period, u_int offset);
160 static void             ahc_construct_wdtr(struct ahc_softc *ahc,
161                                            struct ahc_devinfo *devinfo,
162                                            u_int bus_width);
163 static void             ahc_construct_ppr(struct ahc_softc *ahc,
164                                           struct ahc_devinfo *devinfo,
165                                           u_int period, u_int offset,
166                                           u_int bus_width, u_int ppr_options);
167 static void             ahc_clear_msg_state(struct ahc_softc *ahc);
168 static void             ahc_handle_message_phase(struct ahc_softc *ahc);
169 typedef enum {
170         AHCMSG_1B,
171         AHCMSG_2B,
172         AHCMSG_EXT
173 } ahc_msgtype;
174 static int              ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
175                                      u_int msgval, int full);
176 static int              ahc_parse_msg(struct ahc_softc *ahc,
177                                       struct ahc_devinfo *devinfo);
178 static int              ahc_handle_msg_reject(struct ahc_softc *ahc,
179                                               struct ahc_devinfo *devinfo);
180 static void             ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
181                                                 struct ahc_devinfo *devinfo);
182 static void             ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
183 static void             ahc_handle_devreset(struct ahc_softc *ahc,
184                                             struct ahc_devinfo *devinfo,
185                                             cam_status status, char *message,
186                                             int verbose_level);
187 #if AHC_TARGET_MODE
188 static void             ahc_setup_target_msgin(struct ahc_softc *ahc,
189                                                struct ahc_devinfo *devinfo,
190                                                struct scb *scb);
191 #endif
192
193 static bus_dmamap_callback_t    ahc_dmamap_cb; 
194 static void                     ahc_build_free_scb_list(struct ahc_softc *ahc);
195 static int                      ahc_init_scbdata(struct ahc_softc *ahc);
196 static void                     ahc_fini_scbdata(struct ahc_softc *ahc);
197 static void             ahc_qinfifo_requeue(struct ahc_softc *ahc,
198                                             struct scb *prev_scb,
199                                             struct scb *scb);
200 static int              ahc_qinfifo_count(struct ahc_softc *ahc);
201 static u_int            ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
202                                                    u_int prev, u_int scbptr);
203 static void             ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
204 static u_int            ahc_rem_wscb(struct ahc_softc *ahc,
205                                      u_int scbpos, u_int prev);
206 static int              ahc_abort_scbs(struct ahc_softc *ahc, int target,
207                                        char channel, int lun, u_int tag,
208                                        role_t role, uint32_t status);
209 static void             ahc_reset_current_bus(struct ahc_softc *ahc);
210 #ifdef AHC_DUMP_SEQ
211 static void             ahc_dumpseq(struct ahc_softc *ahc);
212 #endif
213 static void             ahc_loadseq(struct ahc_softc *ahc);
214 static int              ahc_check_patch(struct ahc_softc *ahc,
215                                         struct patch **start_patch,
216                                         u_int start_instr, u_int *skip_addr);
217 static void             ahc_download_instr(struct ahc_softc *ahc,
218                                            u_int instrptr, uint8_t *dconsts);
219 #ifdef AHC_TARGET_MODE
220 static void             ahc_queue_lstate_event(struct ahc_softc *ahc,
221                                                struct ahc_tmode_lstate *lstate,
222                                                u_int initiator_id,
223                                                u_int event_type,
224                                                u_int event_arg);
225 static void             ahc_update_scsiid(struct ahc_softc *ahc,
226                                           u_int targid_mask);
227 static int              ahc_handle_target_cmd(struct ahc_softc *ahc,
228                                               struct target_cmd *cmd);
229 #endif
230 /************************* Sequencer Execution Control ************************/
231 /*
232  * Restart the sequencer program from address zero
233  */
234 void
235 ahc_restart(struct ahc_softc *ahc)
236 {
237
238         ahc_pause(ahc);
239
240         ahc_outb(ahc, SCSISIGO, 0);             /* De-assert BSY */
241         ahc_outb(ahc, MSG_OUT, MSG_NOOP);       /* No message to send */
242         ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
243
244         /*
245          * Ensure that the sequencer's idea of TQINPOS
246          * matches our own.  The sequencer increments TQINPOS
247          * only after it sees a DMA complete and a reset could
248          * occur before the increment leaving the kernel to believe
249          * the command arrived but the sequencer to not.
250          */
251         ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
252
253         /* Always allow reselection */
254         ahc_outb(ahc, SCSISEQ,
255                  ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
256         if ((ahc->features & AHC_CMD_CHAN) != 0) {
257                 /* Ensure that no DMA operations are in progress */
258                 ahc_outb(ahc, CCSCBCNT, 0);
259                 ahc_outb(ahc, CCSGCTL, 0);
260                 ahc_outb(ahc, CCSCBCTL, 0);
261         }
262         /*
263          * If we were in the process of DMA'ing SCB data into
264          * an SCB, replace that SCB on the free list.  This prevents
265          * an SCB leak.
266          */
267         if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
268                 ahc_add_curscb_to_free_list(ahc);
269                 ahc_outb(ahc, SEQ_FLAGS2,
270                          ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
271         }
272         ahc_outb(ahc, MWI_RESIDUAL, 0);
273         ahc_outb(ahc, SEQCTL, FASTMODE);
274         ahc_outb(ahc, SEQADDR0, 0);
275         ahc_outb(ahc, SEQADDR1, 0);
276         ahc_unpause(ahc);
277 }
278
279 /************************* Input/Output Queues ********************************/
280 void
281 ahc_run_qoutfifo(struct ahc_softc *ahc)
282 {
283         struct scb *scb;
284         u_int  scb_index;
285
286         ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
287         while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
288
289                 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
290                 if ((ahc->qoutfifonext & 0x03) == 0x03) {
291                         u_int modnext;
292
293                         /*
294                          * Clear 32bits of QOUTFIFO at a time
295                          * so that we don't clobber an incoming
296                          * byte DMA to the array on architectures
297                          * that only support 32bit load and store
298                          * operations.
299                          */
300                         modnext = ahc->qoutfifonext & ~0x3;
301                         *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
302                         ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
303                                         ahc->shared_data_dmamap,
304                                         /*offset*/modnext, /*len*/4,
305                                         BUS_DMASYNC_PREREAD);
306                 }
307                 ahc->qoutfifonext++;
308
309                 scb = ahc_lookup_scb(ahc, scb_index);
310                 if (scb == NULL) {
311                         printf("%s: WARNING no command for scb %d "
312                                "(cmdcmplt)\nQOUTPOS = %d\n",
313                                ahc_name(ahc), scb_index,
314                                ahc->qoutfifonext - 1);
315                         continue;
316                 }
317
318                 /*
319                  * Save off the residual
320                  * if there is one.
321                  */
322                 ahc_update_residual(scb);
323                 ahc_done(ahc, scb);
324         }
325 }
326
327 void
328 ahc_run_untagged_queues(struct ahc_softc *ahc)
329 {
330         int i;
331
332         for (i = 0; i < 16; i++)
333                 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
334 }
335
336 void
337 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
338 {
339         struct scb *scb;
340
341         if (ahc->untagged_queue_lock != 0)
342                 return;
343
344         if ((scb = TAILQ_FIRST(queue)) != NULL
345          && (scb->flags & SCB_ACTIVE) == 0) {
346                 scb->flags |= SCB_ACTIVE;
347                 ahc_queue_scb(ahc, scb);
348         }
349 }
350
351 /************************* Interrupt Handling *********************************/
352 void
353 ahc_handle_brkadrint(struct ahc_softc *ahc)
354 {
355         /*
356          * We upset the sequencer :-(
357          * Lookup the error message
358          */
359         int i;
360         int error;
361
362         error = ahc_inb(ahc, ERROR);
363         for (i = 0; error != 1 && i < num_errors; i++)
364                 error >>= 1;
365         printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
366                ahc_name(ahc), ahc_hard_errors[i].errmesg,
367                ahc_inb(ahc, SEQADDR0) |
368                (ahc_inb(ahc, SEQADDR1) << 8));
369
370         ahc_dump_card_state(ahc);
371
372         /* Tell everyone that this HBA is no longer availible */
373         ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
374                        CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
375                        CAM_NO_HBA);
376
377         /* Disable all interrupt sources by resetting the controller */
378         ahc_shutdown(ahc);
379 }
380
381 void
382 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
383 {
384         struct scb *scb;
385         struct ahc_devinfo devinfo;
386         
387         ahc_fetch_devinfo(ahc, &devinfo);
388
389         /*
390          * Clear the upper byte that holds SEQINT status
391          * codes and clear the SEQINT bit. We will unpause
392          * the sequencer, if appropriate, after servicing
393          * the request.
394          */
395         ahc_outb(ahc, CLRINT, CLRSEQINT);
396         switch (intstat & SEQINT_MASK) {
397         case BAD_STATUS:
398         {
399                 u_int  scb_index;
400                 struct hardware_scb *hscb;
401
402                 /*
403                  * Set the default return value to 0 (don't
404                  * send sense).  The sense code will change
405                  * this if needed.
406                  */
407                 ahc_outb(ahc, RETURN_1, 0);
408
409                 /*
410                  * The sequencer will notify us when a command
411                  * has an error that would be of interest to
412                  * the kernel.  This allows us to leave the sequencer
413                  * running in the common case of command completes
414                  * without error.  The sequencer will already have
415                  * dma'd the SCB back up to us, so we can reference
416                  * the in kernel copy directly.
417                  */
418                 scb_index = ahc_inb(ahc, SCB_TAG);
419                 scb = ahc_lookup_scb(ahc, scb_index);
420                 if (scb == NULL) {
421                         printf("%s:%c:%d: ahc_intr - referenced scb "
422                                "not valid during seqint 0x%x scb(%d)\n",
423                                ahc_name(ahc), devinfo.channel,
424                                devinfo.target, intstat, scb_index);
425                         ahc_dump_card_state(ahc);
426                         panic("for safety");
427                         goto unpause;
428                 }
429
430                 hscb = scb->hscb; 
431
432                 /* Don't want to clobber the original sense code */
433                 if ((scb->flags & SCB_SENSE) != 0) {
434                         /*
435                          * Clear the SCB_SENSE Flag and have
436                          * the sequencer do a normal command
437                          * complete.
438                          */
439                         scb->flags &= ~SCB_SENSE;
440                         ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
441                         break;
442                 }
443                 ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
444                 /* Freeze the queue until the client sees the error. */
445                 ahc_freeze_devq(ahc, scb);
446                 ahc_freeze_scb(scb);
447                 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
448                 switch (hscb->shared_data.status.scsi_status) {
449                 case SCSI_STATUS_OK:
450                         printf("%s: Interrupted for staus of 0???\n",
451                                ahc_name(ahc));
452                         break;
453                 case SCSI_STATUS_CMD_TERMINATED:
454                 case SCSI_STATUS_CHECK_COND:
455                 {
456                         struct ahc_dma_seg *sg;
457                         struct scsi_sense *sc;
458                         struct ahc_initiator_tinfo *targ_info;
459                         struct ahc_tmode_tstate *tstate;
460                         struct ahc_transinfo *tinfo;
461 #ifdef AHC_DEBUG
462                         if (ahc_debug & AHC_SHOWSENSE) {
463                                 ahc_print_path(ahc, scb);
464                                 printf("SCB %d: requests Check Status\n",
465                                        scb->hscb->tag);
466                         }
467 #endif
468
469                         if (ahc_perform_autosense(scb) == 0)
470                                 break;
471
472                         targ_info = ahc_fetch_transinfo(ahc,
473                                                         devinfo.channel,
474                                                         devinfo.our_scsiid,
475                                                         devinfo.target,
476                                                         &tstate);
477                         tinfo = &targ_info->curr;
478                         sg = scb->sg_list;
479                         sc = (struct scsi_sense *)(&hscb->shared_data.cdb); 
480                         /*
481                          * Save off the residual if there is one.
482                          */
483                         ahc_update_residual(scb);
484 #ifdef AHC_DEBUG
485                         if (ahc_debug & AHC_SHOWSENSE) {
486                                 ahc_print_path(ahc, scb);
487                                 printf("Sending Sense\n");
488                         }
489 #endif
490                         sg->addr = ahc_get_sense_bufaddr(ahc, scb);
491                         sg->len = ahc_get_sense_bufsize(ahc, scb);
492                         sg->len |= AHC_DMA_LAST_SEG;
493
494                         /* Fixup byte order */
495                         sg->addr = ahc_htole32(sg->addr);
496                         sg->len = ahc_htole32(sg->len);
497
498                         sc->opcode = REQUEST_SENSE;
499                         sc->byte2 = 0;
500                         if (tinfo->protocol_version <= SCSI_REV_2
501                          && SCB_GET_LUN(scb) < 8)
502                                 sc->byte2 = SCB_GET_LUN(scb) << 5;
503                         sc->unused[0] = 0;
504                         sc->unused[1] = 0;
505                         sc->length = sg->len;
506                         sc->control = 0;
507
508                         /*
509                          * We can't allow the target to disconnect.
510                          * This will be an untagged transaction and
511                          * having the target disconnect will make this
512                          * transaction indestinguishable from outstanding
513                          * tagged transactions.
514                          */
515                         hscb->control = 0;
516
517                         /*
518                          * This request sense could be because the
519                          * the device lost power or in some other
520                          * way has lost our transfer negotiations.
521                          * Renegotiate if appropriate.  Unit attention
522                          * errors will be reported before any data
523                          * phases occur.
524                          */
525                         if (ahc_get_residual(scb) 
526                          == ahc_get_transfer_length(scb)) {
527                                 ahc_update_neg_request(ahc, &devinfo,
528                                                        tstate, targ_info,
529                                                        /*force*/TRUE);
530                         }
531                         if (tstate->auto_negotiate & devinfo.target_mask) {
532                                 hscb->control |= MK_MESSAGE;
533                                 scb->flags &= ~SCB_NEGOTIATE;
534                                 scb->flags |= SCB_AUTO_NEGOTIATE;
535                         }
536                         hscb->cdb_len = sizeof(*sc);
537                         hscb->dataptr = sg->addr; 
538                         hscb->datacnt = sg->len;
539                         hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
540                         hscb->sgptr = ahc_htole32(hscb->sgptr);
541                         scb->sg_count = 1;
542                         scb->flags |= SCB_SENSE;
543                         ahc_qinfifo_requeue_tail(ahc, scb);
544                         ahc_outb(ahc, RETURN_1, SEND_SENSE);
545 #ifdef __FreeBSD__
546                         /*
547                          * Ensure we have enough time to actually
548                          * retrieve the sense.
549                          */
550                         untimeout(ahc_timeout, (caddr_t)scb,
551                                   scb->io_ctx->ccb_h.timeout_ch);
552                         scb->io_ctx->ccb_h.timeout_ch =
553                             timeout(ahc_timeout, (caddr_t)scb, 5 * hz);
554 #endif
555                         break;
556                 }
557                 default:
558                         break;
559                 }
560                 break;
561         }
562         case NO_MATCH:
563         {
564                 /* Ensure we don't leave the selection hardware on */
565                 ahc_outb(ahc, SCSISEQ,
566                          ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
567
568                 printf("%s:%c:%d: no active SCB for reconnecting "
569                        "target - issuing BUS DEVICE RESET\n",
570                        ahc_name(ahc), devinfo.channel, devinfo.target);
571                 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
572                        "ARG_1 == 0x%x ACCUM = 0x%x\n",
573                        ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
574                        ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
575                 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
576                        "SINDEX == 0x%x\n",
577                        ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
578                        ahc_index_busy_tcl(ahc,
579                             BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
580                                       ahc_inb(ahc, SAVED_LUN))),
581                        ahc_inb(ahc, SINDEX));
582                 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
583                        "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
584                        ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
585                        ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
586                        ahc_inb(ahc, SCB_CONTROL));
587                 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
588                        ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
589                 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
590                 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
591                 ahc_dump_card_state(ahc);
592                 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
593                 ahc->msgout_len = 1;
594                 ahc->msgout_index = 0;
595                 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
596                 ahc_outb(ahc, MSG_OUT, HOST_MSG);
597                 ahc_assert_atn(ahc);
598                 break;
599         }
600         case SEND_REJECT: 
601         {
602                 u_int rejbyte = ahc_inb(ahc, ACCUM);
603                 printf("%s:%c:%d: Warning - unknown message received from "
604                        "target (0x%x).  Rejecting\n", 
605                        ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
606                 break; 
607         }
608         case NO_IDENT: 
609         {
610                 /*
611                  * The reconnecting target either did not send an identify
612                  * message, or did, but we didn't find an SCB to match and
613                  * before it could respond to our ATN/abort, it hit a dataphase.
614                  * The only safe thing to do is to blow it away with a bus
615                  * reset.
616                  */
617                 int found;
618
619                 printf("%s:%c:%d: Target did not send an IDENTIFY message. "
620                        "LASTPHASE = 0x%x, SAVED_SCSIID == 0x%x\n",
621                        ahc_name(ahc), devinfo.channel, devinfo.target,
622                        ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_SCSIID));
623                 found = ahc_reset_channel(ahc, devinfo.channel, 
624                                           /*initiate reset*/TRUE);
625                 printf("%s: Issued Channel %c Bus Reset. "
626                        "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel,
627                        found);
628                 return;
629         }
630         case IGN_WIDE_RES:
631                 ahc_handle_ign_wide_residue(ahc, &devinfo);
632                 break;
633         case PDATA_REINIT:
634                 ahc_reinitialize_dataptrs(ahc);
635                 break;
636         case BAD_PHASE:
637         {
638                 u_int lastphase;
639
640                 lastphase = ahc_inb(ahc, LASTPHASE);
641                 printf("%s:%c:%d: unknown scsi bus phase %x, "
642                        "lastphase = 0x%x.  Attempting to continue\n",
643                        ahc_name(ahc), devinfo.channel, devinfo.target,
644                        lastphase, ahc_inb(ahc, SCSISIGI));
645                 break;
646         }
647         case MISSED_BUSFREE:
648         {
649                 u_int lastphase;
650
651                 lastphase = ahc_inb(ahc, LASTPHASE);
652                 printf("%s:%c:%d: Missed busfree. "
653                        "Lastphase = 0x%x, Curphase = 0x%x\n",
654                        ahc_name(ahc), devinfo.channel, devinfo.target,
655                        lastphase, ahc_inb(ahc, SCSISIGI));
656                 ahc_restart(ahc);
657                 return;
658         }
659         case HOST_MSG_LOOP:
660         {
661                 /*
662                  * The sequencer has encountered a message phase
663                  * that requires host assistance for completion.
664                  * While handling the message phase(s), we will be
665                  * notified by the sequencer after each byte is
666                  * transfered so we can track bus phase changes.
667                  *
668                  * If this is the first time we've seen a HOST_MSG_LOOP
669                  * interrupt, initialize the state of the host message
670                  * loop.
671                  */
672                 if (ahc->msg_type == MSG_TYPE_NONE) {
673                         struct scb *scb;
674                         u_int scb_index;
675                         u_int bus_phase;
676
677                         bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
678                         if (bus_phase != P_MESGIN
679                          && bus_phase != P_MESGOUT) {
680                                 printf("ahc_intr: HOST_MSG_LOOP bad "
681                                        "phase 0x%x\n",
682                                       bus_phase);
683                                 /*
684                                  * Probably transitioned to bus free before
685                                  * we got here.  Just punt the message.
686                                  */
687                                 ahc_clear_intstat(ahc);
688                                 ahc_restart(ahc);
689                                 return;
690                         }
691
692                         scb_index = ahc_inb(ahc, SCB_TAG);
693                         scb = ahc_lookup_scb(ahc, scb_index);
694                         if (devinfo.role == ROLE_INITIATOR) {
695                                 if (scb == NULL)
696                                         panic("HOST_MSG_LOOP with "
697                                               "invalid SCB %x\n", scb_index);
698
699                                 if (bus_phase == P_MESGOUT)
700                                         ahc_setup_initiator_msgout(ahc,
701                                                                    &devinfo,
702                                                                    scb);
703                                 else {
704                                         ahc->msg_type =
705                                             MSG_TYPE_INITIATOR_MSGIN;
706                                         ahc->msgin_index = 0;
707                                 }
708                         } else {
709                                 if (bus_phase == P_MESGOUT) {
710                                         ahc->msg_type =
711                                             MSG_TYPE_TARGET_MSGOUT;
712                                         ahc->msgin_index = 0;
713                                 }
714 #if AHC_TARGET_MODE
715                                 else 
716                                         ahc_setup_target_msgin(ahc,
717                                                                &devinfo,
718                                                                scb);
719 #endif
720                         }
721                 }
722
723                 ahc_handle_message_phase(ahc);
724                 break;
725         }
726         case PERR_DETECTED:
727         {
728                 /*
729                  * If we've cleared the parity error interrupt
730                  * but the sequencer still believes that SCSIPERR
731                  * is true, it must be that the parity error is
732                  * for the currently presented byte on the bus,
733                  * and we are not in a phase (data-in) where we will
734                  * eventually ack this byte.  Ack the byte and
735                  * throw it away in the hope that the target will
736                  * take us to message out to deliver the appropriate
737                  * error message.
738                  */
739                 if ((intstat & SCSIINT) == 0
740                  && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
741
742                         if ((ahc->features & AHC_DT) == 0) {
743                                 u_int curphase;
744
745                                 /*
746                                  * The hardware will only let you ack bytes
747                                  * if the expected phase in SCSISIGO matches
748                                  * the current phase.  Make sure this is
749                                  * currently the case.
750                                  */
751                                 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
752                                 ahc_outb(ahc, LASTPHASE, curphase);
753                                 ahc_outb(ahc, SCSISIGO, curphase);
754                         }
755                         ahc_inb(ahc, SCSIDATL);
756                 }
757                 break;
758         }
759         case DATA_OVERRUN:
760         {
761                 /*
762                  * When the sequencer detects an overrun, it
763                  * places the controller in "BITBUCKET" mode
764                  * and allows the target to complete its transfer.
765                  * Unfortunately, none of the counters get updated
766                  * when the controller is in this mode, so we have
767                  * no way of knowing how large the overrun was.
768                  */
769                 u_int scbindex = ahc_inb(ahc, SCB_TAG);
770                 u_int lastphase = ahc_inb(ahc, LASTPHASE);
771                 u_int i;
772
773                 scb = ahc_lookup_scb(ahc, scbindex);
774                 for (i = 0; i < num_phases; i++) {
775                         if (lastphase == ahc_phase_table[i].phase)
776                                 break;
777                 }
778                 ahc_print_path(ahc, scb);
779                 printf("data overrun detected %s."
780                        "  Tag == 0x%x.\n",
781                        ahc_phase_table[i].phasemsg,
782                        scb->hscb->tag);
783                 ahc_print_path(ahc, scb);
784                 printf("%s seen Data Phase.  Length = %ld.  NumSGs = %d.\n",
785                        ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
786                        ahc_get_transfer_length(scb), scb->sg_count);
787                 if (scb->sg_count > 0) {
788                         for (i = 0; i < scb->sg_count; i++) {
789
790                                 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
791                                        i,
792                                        (ahc_le32toh(scb->sg_list[i].len) >> 24
793                                         & SG_HIGH_ADDR_BITS),
794                                        ahc_le32toh(scb->sg_list[i].addr),
795                                        ahc_le32toh(scb->sg_list[i].len)
796                                        & AHC_SG_LEN_MASK);
797                         }
798                 }
799                 /*
800                  * Set this and it will take effect when the
801                  * target does a command complete.
802                  */
803                 ahc_freeze_devq(ahc, scb);
804                 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR);
805                 ahc_freeze_scb(scb);
806
807                 if ((ahc->features & AHC_ULTRA2) != 0) {
808                         /*
809                          * Clear the channel in case we return
810                          * to data phase later.
811                          */
812                         ahc_outb(ahc, SXFRCTL0,
813                                  ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
814                         ahc_outb(ahc, SXFRCTL0,
815                                  ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
816                 }
817                 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
818                         u_int dscommand1;
819
820                         /* Ensure HHADDR is 0 for future DMA operations. */
821                         dscommand1 = ahc_inb(ahc, DSCOMMAND1);
822                         ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
823                         ahc_outb(ahc, HADDR, 0);
824                         ahc_outb(ahc, DSCOMMAND1, dscommand1);
825                 }
826                 break;
827         }
828         case MKMSG_FAILED:
829         {
830                 u_int scbindex;
831
832                 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
833                        ahc_name(ahc), devinfo.channel, devinfo.target,
834                        devinfo.lun);
835                 scbindex = ahc_inb(ahc, SCB_TAG);
836                 scb = ahc_lookup_scb(ahc, scbindex);
837                 if (scb != NULL
838                  && (scb->flags & SCB_RECOVERY_SCB) != 0)
839                         /*
840                          * Ensure that we didn't put a second instance of this
841                          * SCB into the QINFIFO.
842                          */
843                         ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
844                                            SCB_GET_CHANNEL(ahc, scb),
845                                            SCB_GET_LUN(scb), scb->hscb->tag,
846                                            ROLE_INITIATOR, /*status*/0,
847                                            SEARCH_REMOVE);
848                 break;
849         }
850         case NO_FREE_SCB:
851         {
852                 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
853                 ahc_dump_card_state(ahc);
854                 panic("for safety");
855                 break;
856         }
857         case SCB_MISMATCH:
858         {
859                 u_int scbptr;
860
861                 scbptr = ahc_inb(ahc, SCBPTR);
862                 printf("Bogus TAG after DMA.  SCBPTR %d, tag %d, our tag %d\n",
863                        scbptr, ahc_inb(ahc, ARG_1),
864                        ahc->scb_data->hscbs[scbptr].tag);
865                 ahc_dump_card_state(ahc);
866                 panic("for saftey");
867                 break;
868         }
869         case OUT_OF_RANGE:
870         {
871                 printf("%s: BTT calculation out of range\n", ahc_name(ahc));
872                 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
873                        "ARG_1 == 0x%x ACCUM = 0x%x\n",
874                        ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
875                        ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
876                 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
877                        "SINDEX == 0x%x\n, A == 0x%x\n",
878                        ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
879                        ahc_index_busy_tcl(ahc,
880                             BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
881                                       ahc_inb(ahc, SAVED_LUN))),
882                        ahc_inb(ahc, SINDEX),
883                        ahc_inb(ahc, ACCUM));
884                 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
885                        "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
886                        ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
887                        ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
888                        ahc_inb(ahc, SCB_CONTROL));
889                 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
890                        ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
891                 ahc_dump_card_state(ahc);
892                 panic("for safety");
893                 break;
894         }
895         default:
896                 printf("ahc_intr: seqint, "
897                        "intstat == 0x%x, scsisigi = 0x%x\n",
898                        intstat, ahc_inb(ahc, SCSISIGI));
899                 break;
900         }
901 unpause:
902         /*
903          *  The sequencer is paused immediately on
904          *  a SEQINT, so we should restart it when
905          *  we're done.
906          */
907         ahc_unpause(ahc);
908 }
909
910 void
911 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
912 {
913         u_int   scb_index;
914         u_int   status0;
915         u_int   status;
916         struct  scb *scb;
917         char    cur_channel;
918         char    intr_channel;
919
920         /* Make sure the sequencer is in a safe location. */
921         ahc_clear_critical_section(ahc);
922
923         if ((ahc->features & AHC_TWIN) != 0
924          && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
925                 cur_channel = 'B';
926         else
927                 cur_channel = 'A';
928         intr_channel = cur_channel;
929
930         if ((ahc->features & AHC_ULTRA2) != 0)
931                 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
932         else
933                 status0 = 0;
934         status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
935         if (status == 0 && status0 == 0) {
936                 if ((ahc->features & AHC_TWIN) != 0) {
937                         /* Try the other channel */
938                         ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
939                         status = ahc_inb(ahc, SSTAT1)
940                                & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
941                         intr_channel = (cur_channel == 'A') ? 'B' : 'A';
942                 }
943                 if (status == 0) {
944                         printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
945                         ahc_outb(ahc, CLRINT, CLRSCSIINT);
946                         ahc_unpause(ahc);
947                         return;
948                 }
949         }
950
951         scb_index = ahc_inb(ahc, SCB_TAG);
952         scb = ahc_lookup_scb(ahc, scb_index);
953         if (scb != NULL
954          && (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0)
955                 scb = NULL;
956
957         if ((ahc->features & AHC_ULTRA2) != 0
958          && (status0 & IOERR) != 0) {
959                 int now_lvd;
960
961                 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
962                 printf("%s: Transceiver State Has Changed to %s mode\n",
963                        ahc_name(ahc), now_lvd ? "LVD" : "SE");
964                 ahc_outb(ahc, CLRSINT0, CLRIOERR);
965                 /*
966                  * When transitioning to SE mode, the reset line
967                  * glitches, triggering an arbitration bug in some
968                  * Ultra2 controllers.  This bug is cleared when we
969                  * assert the reset line.  Since a reset glitch has
970                  * already occurred with this transition and a
971                  * transceiver state change is handled just like
972                  * a bus reset anyway, asserting the reset line
973                  * ourselves is safe.
974                  */
975                 ahc_reset_channel(ahc, intr_channel,
976                                  /*Initiate Reset*/now_lvd == 0);
977         } else if ((status & SCSIRSTI) != 0) {
978                 printf("%s: Someone reset channel %c\n",
979                         ahc_name(ahc), intr_channel);
980                 if (intr_channel != cur_channel)
981                         ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
982                 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
983         } else if ((status & SCSIPERR) != 0) {
984                 /*
985                  * Determine the bus phase and queue an appropriate message.
986                  * SCSIPERR is latched true as soon as a parity error
987                  * occurs.  If the sequencer acked the transfer that
988                  * caused the parity error and the currently presented
989                  * transfer on the bus has correct parity, SCSIPERR will
990                  * be cleared by CLRSCSIPERR.  Use this to determine if
991                  * we should look at the last phase the sequencer recorded,
992                  * or the current phase presented on the bus.
993                  */
994                 u_int mesg_out;
995                 u_int curphase;
996                 u_int errorphase;
997                 u_int lastphase;
998                 u_int scsirate;
999                 u_int i;
1000                 u_int sstat2;
1001
1002                 lastphase = ahc_inb(ahc, LASTPHASE);
1003                 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1004                 sstat2 = ahc_inb(ahc, SSTAT2);
1005                 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1006                 /*
1007                  * For all phases save DATA, the sequencer won't
1008                  * automatically ack a byte that has a parity error
1009                  * in it.  So the only way that the current phase
1010                  * could be 'data-in' is if the parity error is for
1011                  * an already acked byte in the data phase.  During
1012                  * synchronous data-in transfers, we may actually
1013                  * ack bytes before latching the current phase in
1014                  * LASTPHASE, leading to the discrepancy between
1015                  * curphase and lastphase.
1016                  */
1017                 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1018                  || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1019                         errorphase = curphase;
1020                 else
1021                         errorphase = lastphase;
1022
1023                 for (i = 0; i < num_phases; i++) {
1024                         if (errorphase == ahc_phase_table[i].phase)
1025                                 break;
1026                 }
1027                 mesg_out = ahc_phase_table[i].mesg_out;
1028                 if (scb != NULL)
1029                         ahc_print_path(ahc, scb);
1030                 else
1031                         printf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1032                                SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1033                 scsirate = ahc_inb(ahc, SCSIRATE);
1034                 printf("parity error detected %s. "
1035                        "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1036                        ahc_phase_table[i].phasemsg,
1037                        ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8),
1038                        scsirate);
1039
1040                 if ((ahc->features & AHC_DT) != 0) {
1041
1042                         if ((sstat2 & CRCVALERR) != 0)
1043                                 printf("\tCRC Value Mismatch\n");
1044                         if ((sstat2 & CRCENDERR) != 0)
1045                                 printf("\tNo terminal CRC packet recevied\n");
1046                         if ((sstat2 & CRCREQERR) != 0)
1047                                 printf("\tIllegal CRC packet request\n");
1048                         if ((sstat2 & DUAL_EDGE_ERR) != 0)
1049                                 printf("\tUnexpected %sDT Data Phase\n",
1050                                        (scsirate & SINGLE_EDGE) ? "" : "non-");
1051                 }
1052
1053                 /*
1054                  * We've set the hardware to assert ATN if we   
1055                  * get a parity error on "in" phases, so all we  
1056                  * need to do is stuff the message buffer with
1057                  * the appropriate message.  "In" phases have set
1058                  * mesg_out to something other than MSG_NOP.
1059                  */
1060                 if (mesg_out != MSG_NOOP) {
1061                         if (ahc->msg_type != MSG_TYPE_NONE)
1062                                 ahc->send_msg_perror = TRUE;
1063                         else
1064                                 ahc_outb(ahc, MSG_OUT, mesg_out);
1065                 }
1066                 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1067                 ahc_unpause(ahc);
1068         } else if ((status & SELTO) != 0) {
1069                 u_int scbptr;
1070
1071                 /* Stop the selection */
1072                 ahc_outb(ahc, SCSISEQ, 0);
1073
1074                 /* No more pending messages */
1075                 ahc_clear_msg_state(ahc);
1076
1077                 /* Clear interrupt state */
1078                 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1079                 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1080
1081                 /*
1082                  * Although the driver does not care about the
1083                  * 'Selection in Progress' status bit, the busy
1084                  * LED does.  SELINGO is only cleared by a sucessfull
1085                  * selection, so we must manually clear it to insure
1086                  * the LED turns off just incase no future successful
1087                  * selections occur (e.g. no devices on the bus).
1088                  */
1089                 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1090
1091                 scbptr = ahc_inb(ahc, WAITING_SCBH);
1092                 ahc_outb(ahc, SCBPTR, scbptr);
1093                 scb_index = ahc_inb(ahc, SCB_TAG);
1094
1095                 scb = ahc_lookup_scb(ahc, scb_index);
1096                 if (scb == NULL) {
1097                         printf("%s: ahc_intr - referenced scb not "
1098                                "valid during SELTO scb(%d, %d)\n",
1099                                ahc_name(ahc), scbptr, scb_index);
1100                 } else {
1101                         ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1102                         ahc_freeze_devq(ahc, scb);
1103                 }
1104                 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1105                 ahc_restart(ahc);
1106         } else if ((status & BUSFREE) != 0
1107                 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1108                 u_int lastphase;
1109                 u_int saved_scsiid;
1110                 u_int saved_lun;
1111                 u_int target;
1112                 u_int initiator_role_id;
1113                 char channel;
1114                 int printerror;
1115
1116                 /*
1117                  * Clear our selection hardware as soon as possible.
1118                  * We may have an entry in the waiting Q for this target,
1119                  * that is affected by this busfree and we don't want to
1120                  * go about selecting the target while we handle the event.
1121                  */
1122                 ahc_outb(ahc, SCSISEQ,
1123                          ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1124
1125                 /*
1126                  * Disable busfree interrupts and clear the busfree
1127                  * interrupt status.  We do this here so that several
1128                  * bus transactions occur prior to clearing the SCSIINT
1129                  * latch.  It can take a bit for the clearing to take effect.
1130                  */
1131                 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1132                 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1133
1134                 /*
1135                  * Look at what phase we were last in.
1136                  * If its message out, chances are pretty good
1137                  * that the busfree was in response to one of
1138                  * our abort requests.
1139                  */
1140                 lastphase = ahc_inb(ahc, LASTPHASE);
1141                 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1142                 saved_lun = ahc_inb(ahc, SAVED_LUN);
1143                 target = SCSIID_TARGET(ahc, saved_scsiid);
1144                 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1145                 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1146                 printerror = 1;
1147
1148                 if (lastphase == P_MESGOUT) {
1149                         struct ahc_devinfo devinfo;
1150                         u_int tag;
1151
1152                         ahc_fetch_devinfo(ahc, &devinfo);
1153                         tag = SCB_LIST_NULL;
1154                         if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1155                          || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1156                                 if (ahc->msgout_buf[ahc->msgout_index - 1]
1157                                  == MSG_ABORT_TAG)
1158                                         tag = scb->hscb->tag;
1159                                 ahc_print_path(ahc, scb);
1160                                 printf("SCB %d - Abort%s Completed.\n",
1161                                        scb->hscb->tag, tag == SCB_LIST_NULL ?
1162                                        "" : " Tag");
1163                                 ahc_abort_scbs(ahc, target, channel,
1164                                                saved_lun, tag,
1165                                                ROLE_INITIATOR,
1166                                                CAM_REQ_ABORTED);
1167                                 printerror = 0;
1168                         } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1169                                                 MSG_BUS_DEV_RESET, TRUE)) {
1170                                 struct ahc_devinfo devinfo;
1171 #ifdef __FreeBSD__
1172                                 /*
1173                                  * Don't mark the user's request for this BDR
1174                                  * as completing with CAM_BDR_SENT.  CAM3
1175                                  * specifies CAM_REQ_CMP.
1176                                  */
1177                                 if (scb != NULL
1178                                  && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1179                                  && ahc_match_scb(ahc, scb, target, channel,
1180                                                   CAM_LUN_WILDCARD,
1181                                                   SCB_LIST_NULL,
1182                                                   ROLE_INITIATOR)) {
1183                                         ahc_set_transaction_status(scb, CAM_REQ_CMP);
1184                                 }
1185 #endif
1186                                 ahc_compile_devinfo(&devinfo,
1187                                                     initiator_role_id,
1188                                                     target,
1189                                                     CAM_LUN_WILDCARD,
1190                                                     channel,
1191                                                     ROLE_INITIATOR);
1192                                 ahc_handle_devreset(ahc, &devinfo,
1193                                                     CAM_BDR_SENT,
1194                                                     "Bus Device Reset",
1195                                                     /*verbose_level*/0);
1196                                 printerror = 0;
1197                         } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1198                                                 MSG_EXT_PPR, FALSE)) {
1199                                 struct ahc_initiator_tinfo *tinfo;
1200                                 struct ahc_tmode_tstate *tstate;
1201
1202                                 /*
1203                                  * PPR Rejected.  Try non-ppr negotiation
1204                                  * and retry command.
1205                                  */
1206                                 tinfo = ahc_fetch_transinfo(ahc,
1207                                                             devinfo.channel,
1208                                                             devinfo.our_scsiid,
1209                                                             devinfo.target,
1210                                                             &tstate);
1211                                 tinfo->curr.transport_version = 2;
1212                                 tinfo->goal.transport_version = 2;
1213                                 tinfo->goal.ppr_options = 0;
1214                                 ahc_qinfifo_requeue_tail(ahc, scb);
1215                                 printerror = 0;
1216                         } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1217                                                 MSG_EXT_WDTR, FALSE)
1218                                 || ahc_sent_msg(ahc, AHCMSG_EXT,
1219                                                 MSG_EXT_SDTR, FALSE)) {
1220                                 /*
1221                                  * Negotiation Rejected.  Go-async and
1222                                  * retry command.
1223                                  */
1224                                 ahc_set_width(ahc, &devinfo,
1225                                               MSG_EXT_WDTR_BUS_8_BIT,
1226                                               AHC_TRANS_CUR|AHC_TRANS_GOAL,
1227                                               /*paused*/TRUE);
1228                                 ahc_set_syncrate(ahc, &devinfo,
1229                                                 /*syncrate*/NULL,
1230                                                 /*period*/0, /*offset*/0,
1231                                                 /*ppr_options*/0,
1232                                                 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1233                                                 /*paused*/TRUE);
1234                                 ahc_qinfifo_requeue_tail(ahc, scb);
1235                                 printerror = 0;
1236                         }
1237                 }
1238                 if (printerror != 0) {
1239                         u_int i;
1240
1241                         if (scb != NULL) {
1242                                 u_int tag;
1243
1244                                 if ((scb->hscb->control & TAG_ENB) != 0)
1245                                         tag = scb->hscb->tag;
1246                                 else
1247                                         tag = SCB_LIST_NULL;
1248                                 ahc_print_path(ahc, scb);
1249                                 ahc_abort_scbs(ahc, target, channel,
1250                                                SCB_GET_LUN(scb), tag,
1251                                                ROLE_INITIATOR,
1252                                                CAM_UNEXP_BUSFREE);
1253                         } else {
1254                                 /*
1255                                  * We had not fully identified this connection,
1256                                  * so we cannot abort anything.
1257                                  */
1258                                 printf("%s: ", ahc_name(ahc));
1259                         }
1260                         for (i = 0; i < num_phases; i++) {
1261                                 if (lastphase == ahc_phase_table[i].phase)
1262                                         break;
1263                         }
1264                         printf("Unexpected busfree %s\n"
1265                                "SEQADDR == 0x%x\n",
1266                                ahc_phase_table[i].phasemsg,
1267                                ahc_inb(ahc, SEQADDR0)
1268                                 | (ahc_inb(ahc, SEQADDR1) << 8));
1269                 }
1270                 ahc_clear_msg_state(ahc);
1271                 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1272                 ahc_restart(ahc);
1273         } else {
1274                 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1275                        ahc_name(ahc), status);
1276                 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1277         }
1278 }
1279
1280 #define AHC_MAX_STEPS 2000
1281 void
1282 ahc_clear_critical_section(struct ahc_softc *ahc)
1283 {
1284         int     stepping;
1285         int     steps;
1286         u_int   simode0;
1287         u_int   simode1;
1288
1289         if (ahc->num_critical_sections == 0)
1290                 return;
1291
1292         stepping = FALSE;
1293         steps = 0;
1294         simode0 = 0;
1295         simode1 = 0;
1296         for (;;) {
1297                 struct  cs *cs;
1298                 u_int   seqaddr;
1299                 u_int   i;
1300
1301                 seqaddr = ahc_inb(ahc, SEQADDR0)
1302                         | (ahc_inb(ahc, SEQADDR1) << 8);
1303
1304                 /*
1305                  * Seqaddr represents the next instruction to execute, 
1306                  * so we are really executing the instruction just
1307                  * before it.
1308                  */
1309                 if (seqaddr != 0)
1310                         seqaddr -= 1;
1311                 cs = ahc->critical_sections;
1312                 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
1313                         
1314                         if (cs->begin < seqaddr && cs->end >= seqaddr)
1315                                 break;
1316                 }
1317
1318                 if (i == ahc->num_critical_sections)
1319                         break;
1320
1321                 if (steps > AHC_MAX_STEPS) {
1322                         printf("%s: Infinite loop in critical section\n",
1323                                ahc_name(ahc));
1324                         ahc_dump_card_state(ahc);
1325                         panic("critical section loop");
1326                 }
1327
1328                 steps++;
1329                 if (stepping == FALSE) {
1330
1331                         /*
1332                          * Disable all interrupt sources so that the
1333                          * sequencer will not be stuck by a pausing
1334                          * interrupt condition while we attempt to
1335                          * leave a critical section.
1336                          */
1337                         simode0 = ahc_inb(ahc, SIMODE0);
1338                         ahc_outb(ahc, SIMODE0, 0);
1339                         simode1 = ahc_inb(ahc, SIMODE1);
1340                         ahc_outb(ahc, SIMODE1, 0);
1341                         ahc_outb(ahc, CLRINT, CLRSCSIINT);
1342                         ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) | STEP);
1343                         stepping = TRUE;
1344                 }
1345                 ahc_outb(ahc, HCNTRL, ahc->unpause);
1346                 do {
1347                         ahc_delay(200);
1348                 } while (!ahc_is_paused(ahc));
1349         }
1350         if (stepping) {
1351                 ahc_outb(ahc, SIMODE0, simode0);
1352                 ahc_outb(ahc, SIMODE1, simode1);
1353                 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) & ~STEP);
1354         }
1355 }
1356
1357 /*
1358  * Clear any pending interrupt status.
1359  */
1360 void
1361 ahc_clear_intstat(struct ahc_softc *ahc)
1362 {
1363         /* Clear any interrupt conditions this may have caused */
1364         ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
1365                                 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
1366                                 CLRREQINIT);
1367         ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
1368         ahc_outb(ahc, CLRINT, CLRSCSIINT);
1369 }
1370
1371 /**************************** Debugging Routines ******************************/
1372 void
1373 ahc_print_scb(struct scb *scb)
1374 {
1375         int i;
1376
1377         struct hardware_scb *hscb = scb->hscb;
1378
1379         printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1380                (void *)scb,
1381                hscb->control,
1382                hscb->scsiid,
1383                hscb->lun,
1384                hscb->cdb_len);
1385         printf("Shared Data: %#02x %#02x %#02x %#02x\n",
1386                hscb->shared_data.cdb[0],
1387                hscb->shared_data.cdb[1],
1388                hscb->shared_data.cdb[2],
1389                hscb->shared_data.cdb[3]);
1390         printf("             %#02x %#02x %#02x %#02x\n",
1391                hscb->shared_data.cdb[4],
1392                hscb->shared_data.cdb[5],
1393                hscb->shared_data.cdb[6],
1394                hscb->shared_data.cdb[7]);
1395         printf("             %#02x %#02x %#02x %#02x\n",
1396                hscb->shared_data.cdb[8],
1397                hscb->shared_data.cdb[9],
1398                hscb->shared_data.cdb[10],
1399                hscb->shared_data.cdb[11]);
1400         printf("        dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1401                 ahc_le32toh(hscb->dataptr),
1402                 ahc_le32toh(hscb->datacnt),
1403                 ahc_le32toh(hscb->sgptr),
1404                 hscb->tag);
1405         if (scb->sg_count > 0) {
1406                 for (i = 0; i < scb->sg_count; i++) {
1407                         printf("sg[%d] - Addr 0x%x%x : Length %d\n",
1408                                i,
1409                                (ahc_le32toh(scb->sg_list[i].len) >> 24
1410                                 & SG_HIGH_ADDR_BITS),
1411                                ahc_le32toh(scb->sg_list[i].addr),
1412                                ahc_le32toh(scb->sg_list[i].len));
1413                 }
1414         }
1415 }
1416
1417 /************************* Transfer Negotiation *******************************/
1418 /*
1419  * Allocate per target mode instance (ID we respond to as a target)
1420  * transfer negotiation data structures.
1421  */
1422 static struct ahc_tmode_tstate *
1423 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
1424 {
1425         struct ahc_tmode_tstate *master_tstate;
1426         struct ahc_tmode_tstate *tstate;
1427         int i;
1428
1429         master_tstate = ahc->enabled_targets[ahc->our_id];
1430         if (channel == 'B') {
1431                 scsi_id += 8;
1432                 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
1433         }
1434         if (ahc->enabled_targets[scsi_id] != NULL
1435          && ahc->enabled_targets[scsi_id] != master_tstate)
1436                 panic("%s: ahc_alloc_tstate - Target already allocated",
1437                       ahc_name(ahc));
1438         tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT);
1439         if (tstate == NULL)
1440                 return (NULL);
1441
1442         /*
1443          * If we have allocated a master tstate, copy user settings from
1444          * the master tstate (taken from SRAM or the EEPROM) for this
1445          * channel, but reset our current and goal settings to async/narrow
1446          * until an initiator talks to us.
1447          */
1448         if (master_tstate != NULL) {
1449                 memcpy(tstate, master_tstate, sizeof(*tstate));
1450                 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
1451                 tstate->ultraenb = 0;
1452                 for (i = 0; i < 16; i++) {
1453                         memset(&tstate->transinfo[i].curr, 0,
1454                               sizeof(tstate->transinfo[i].curr));
1455                         memset(&tstate->transinfo[i].goal, 0,
1456                               sizeof(tstate->transinfo[i].goal));
1457                 }
1458         } else
1459                 memset(tstate, 0, sizeof(*tstate));
1460         ahc->enabled_targets[scsi_id] = tstate;
1461         return (tstate);
1462 }
1463
1464 #ifdef AHC_TARGET_MODE
1465 /*
1466  * Free per target mode instance (ID we respond to as a target)
1467  * transfer negotiation data structures.
1468  */
1469 static void
1470 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
1471 {
1472         struct ahc_tmode_tstate *tstate;
1473
1474         /*
1475          * Don't clean up our "master" tstate.
1476          * It has our default user settings.
1477          */
1478         if (((channel == 'B' && scsi_id == ahc->our_id_b)
1479           || (channel == 'A' && scsi_id == ahc->our_id))
1480          && force == FALSE)
1481                 return;
1482
1483         if (channel == 'B')
1484                 scsi_id += 8;
1485         tstate = ahc->enabled_targets[scsi_id];
1486         if (tstate != NULL)
1487                 free(tstate, M_DEVBUF);
1488         ahc->enabled_targets[scsi_id] = NULL;
1489 }
1490 #endif
1491
1492 /*
1493  * Called when we have an active connection to a target on the bus,
1494  * this function finds the nearest syncrate to the input period limited
1495  * by the capabilities of the bus connectivity of and sync settings for
1496  * the target.
1497  */
1498 struct ahc_syncrate *
1499 ahc_devlimited_syncrate(struct ahc_softc *ahc,
1500                         struct ahc_initiator_tinfo *tinfo,
1501                         u_int *period, u_int *ppr_options, role_t role) {
1502         struct  ahc_transinfo *transinfo;
1503         u_int   maxsync;
1504
1505         if ((ahc->features & AHC_ULTRA2) != 0) {
1506                 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
1507                  && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
1508                         maxsync = AHC_SYNCRATE_DT;
1509                 } else {
1510                         maxsync = AHC_SYNCRATE_ULTRA;
1511                         /* Can't do DT on an SE bus */
1512                         *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1513                 }
1514         } else if ((ahc->features & AHC_ULTRA) != 0) {
1515                 maxsync = AHC_SYNCRATE_ULTRA;
1516         } else {
1517                 maxsync = AHC_SYNCRATE_FAST;
1518         }
1519         /*
1520          * Never allow a value higher than our current goal
1521          * period otherwise we may allow a target initiated
1522          * negotiation to go above the limit as set by the
1523          * user.  In the case of an initiator initiated
1524          * sync negotiation, we limit based on the user
1525          * setting.  This allows the system to still accept
1526          * incoming negotiations even if target initiated
1527          * negotiation is not performed.
1528          */
1529         if (role == ROLE_TARGET)
1530                 transinfo = &tinfo->user;
1531         else 
1532                 transinfo = &tinfo->goal;
1533         *ppr_options &= transinfo->ppr_options;
1534         if (transinfo->period == 0) {
1535                 *period = 0;
1536                 *ppr_options = 0;
1537                 return (NULL);
1538         }
1539         *period = MAX(*period, transinfo->period);
1540         return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
1541 }
1542
1543 /*
1544  * Look up the valid period to SCSIRATE conversion in our table.
1545  * Return the period and offset that should be sent to the target
1546  * if this was the beginning of an SDTR.
1547  */
1548 struct ahc_syncrate *
1549 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1550                   u_int *ppr_options, u_int maxsync)
1551 {
1552         struct ahc_syncrate *syncrate;
1553
1554         if ((ahc->features & AHC_DT) == 0)
1555                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1556
1557         /* Skip all DT only entries if DT is not available */
1558         if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
1559          && maxsync < AHC_SYNCRATE_ULTRA2)
1560                 maxsync = AHC_SYNCRATE_ULTRA2;
1561         
1562         for (syncrate = &ahc_syncrates[maxsync];
1563              syncrate->rate != NULL;
1564              syncrate++) {
1565
1566                 /*
1567                  * The Ultra2 table doesn't go as low
1568                  * as for the Fast/Ultra cards.
1569                  */
1570                 if ((ahc->features & AHC_ULTRA2) != 0
1571                  && (syncrate->sxfr_u2 == 0))
1572                         break;
1573
1574                 if (*period <= syncrate->period) {
1575                         /*
1576                          * When responding to a target that requests
1577                          * sync, the requested rate may fall between
1578                          * two rates that we can output, but still be
1579                          * a rate that we can receive.  Because of this,
1580                          * we want to respond to the target with
1581                          * the same rate that it sent to us even
1582                          * if the period we use to send data to it
1583                          * is lower.  Only lower the response period
1584                          * if we must.
1585                          */
1586                         if (syncrate == &ahc_syncrates[maxsync])
1587                                 *period = syncrate->period;
1588
1589                         /*
1590                          * At some speeds, we only support
1591                          * ST transfers.
1592                          */
1593                         if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
1594                                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1595                         break;
1596                 }
1597         }
1598
1599         if ((*period == 0)
1600          || (syncrate->rate == NULL)
1601          || ((ahc->features & AHC_ULTRA2) != 0
1602           && (syncrate->sxfr_u2 == 0))) {
1603                 /* Use asynchronous transfers. */
1604                 *period = 0;
1605                 syncrate = NULL;
1606                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1607         }
1608         return (syncrate);
1609 }
1610
1611 /*
1612  * Convert from an entry in our syncrate table to the SCSI equivalent
1613  * sync "period" factor.
1614  */
1615 u_int
1616 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1617 {
1618         struct ahc_syncrate *syncrate;
1619
1620         if ((ahc->features & AHC_ULTRA2) != 0)
1621                 scsirate &= SXFR_ULTRA2;
1622         else
1623                 scsirate &= SXFR;
1624
1625         syncrate = &ahc_syncrates[maxsync];
1626         while (syncrate->rate != NULL) {
1627
1628                 if ((ahc->features & AHC_ULTRA2) != 0) {
1629                         if (syncrate->sxfr_u2 == 0)
1630                                 break;
1631                         else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
1632                                 return (syncrate->period);
1633                 } else if (scsirate == (syncrate->sxfr & SXFR)) {
1634                                 return (syncrate->period);
1635                 }
1636                 syncrate++;
1637         }
1638         return (0); /* async */
1639 }
1640
1641 /*
1642  * Truncate the given synchronous offset to a value the
1643  * current adapter type and syncrate are capable of.
1644  */
1645 void
1646 ahc_validate_offset(struct ahc_softc *ahc,
1647                     struct ahc_initiator_tinfo *tinfo,
1648                     struct ahc_syncrate *syncrate,
1649                     u_int *offset, int wide, role_t role)
1650 {
1651         u_int maxoffset;
1652
1653         /* Limit offset to what we can do */
1654         if (syncrate == NULL) {
1655                 maxoffset = 0;
1656         } else if ((ahc->features & AHC_ULTRA2) != 0) {
1657                 maxoffset = MAX_OFFSET_ULTRA2;
1658         } else {
1659                 if (wide)
1660                         maxoffset = MAX_OFFSET_16BIT;
1661                 else
1662                         maxoffset = MAX_OFFSET_8BIT;
1663         }
1664         *offset = MIN(*offset, maxoffset);
1665         if (tinfo != NULL) {
1666                 if (role == ROLE_TARGET)
1667                         *offset = MIN(*offset, tinfo->user.offset);
1668                 else
1669                         *offset = MIN(*offset, tinfo->goal.offset);
1670         }
1671 }
1672
1673 /*
1674  * Truncate the given transfer width parameter to a value the
1675  * current adapter type is capable of.
1676  */
1677 void
1678 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
1679                    u_int *bus_width, role_t role)
1680 {
1681         switch (*bus_width) {
1682         default:
1683                 if (ahc->features & AHC_WIDE) {
1684                         /* Respond Wide */
1685                         *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
1686                         break;
1687                 }
1688                 /* FALLTHROUGH */
1689         case MSG_EXT_WDTR_BUS_8_BIT:
1690                 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
1691                 break;
1692         }
1693         if (tinfo != NULL) {
1694                 if (role == ROLE_TARGET)
1695                         *bus_width = MIN(tinfo->user.width, *bus_width);
1696                 else
1697                         *bus_width = MIN(tinfo->goal.width, *bus_width);
1698         }
1699 }
1700
1701 /*
1702  * Update the bitmask of targets for which the controller should
1703  * negotiate with at the next convenient oportunity.  This currently
1704  * means the next time we send the initial identify messages for
1705  * a new transaction.
1706  */
1707 int
1708 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1709                        struct ahc_tmode_tstate *tstate,
1710                        struct ahc_initiator_tinfo *tinfo, int force)
1711 {
1712         u_int auto_negotiate_orig;
1713
1714         auto_negotiate_orig = tstate->auto_negotiate;
1715         if (tinfo->curr.period != tinfo->goal.period
1716          || tinfo->curr.width != tinfo->goal.width
1717          || tinfo->curr.offset != tinfo->goal.offset
1718          || tinfo->curr.ppr_options != tinfo->goal.ppr_options
1719          || (force
1720           && (tinfo->goal.period != 0
1721            || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
1722            || tinfo->goal.ppr_options != 0)))
1723                 tstate->auto_negotiate |= devinfo->target_mask;
1724         else
1725                 tstate->auto_negotiate &= ~devinfo->target_mask;
1726
1727         return (auto_negotiate_orig != tstate->auto_negotiate);
1728 }
1729
1730 /*
1731  * Update the user/goal/curr tables of synchronous negotiation
1732  * parameters as well as, in the case of a current or active update,
1733  * any data structures on the host controller.  In the case of an
1734  * active update, the specified target is currently talking to us on
1735  * the bus, so the transfer parameter update must take effect
1736  * immediately.
1737  */
1738 void
1739 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1740                  struct ahc_syncrate *syncrate, u_int period,
1741                  u_int offset, u_int ppr_options, u_int type, int paused)
1742 {
1743         struct  ahc_initiator_tinfo *tinfo;
1744         struct  ahc_tmode_tstate *tstate;
1745         u_int   old_period;
1746         u_int   old_offset;
1747         u_int   old_ppr;
1748         int     active;
1749         int     update_needed;
1750
1751         active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1752         update_needed = 0;
1753
1754         if (syncrate == NULL) {
1755                 period = 0;
1756                 offset = 0;
1757         }
1758
1759         tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1760                                     devinfo->target, &tstate);
1761
1762         if ((type & AHC_TRANS_USER) != 0) {
1763                 tinfo->user.period = period;
1764                 tinfo->user.offset = offset;
1765                 tinfo->user.ppr_options = ppr_options;
1766         }
1767
1768         if ((type & AHC_TRANS_GOAL) != 0) {
1769                 tinfo->goal.period = period;
1770                 tinfo->goal.offset = offset;
1771                 tinfo->goal.ppr_options = ppr_options;
1772         }
1773
1774         old_period = tinfo->curr.period;
1775         old_offset = tinfo->curr.offset;
1776         old_ppr    = tinfo->curr.ppr_options;
1777
1778         if ((type & AHC_TRANS_CUR) != 0
1779          && (old_period != period
1780           || old_offset != offset
1781           || old_ppr != ppr_options)) {
1782                 u_int   scsirate;
1783
1784                 update_needed++;
1785                 scsirate = tinfo->scsirate;
1786                 if ((ahc->features & AHC_ULTRA2) != 0) {
1787
1788                         scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
1789                         if (syncrate != NULL) {
1790                                 scsirate |= syncrate->sxfr_u2;
1791                                 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
1792                                         scsirate |= ENABLE_CRC;
1793                                 else
1794                                         scsirate |= SINGLE_EDGE;
1795                         }
1796                 } else {
1797
1798                         scsirate &= ~(SXFR|SOFS);
1799                         /*
1800                          * Ensure Ultra mode is set properly for
1801                          * this target.
1802                          */
1803                         tstate->ultraenb &= ~devinfo->target_mask;
1804                         if (syncrate != NULL) {
1805                                 if (syncrate->sxfr & ULTRA_SXFR) {
1806                                         tstate->ultraenb |=
1807                                                 devinfo->target_mask;
1808                                 }
1809                                 scsirate |= syncrate->sxfr & SXFR;
1810                                 scsirate |= offset & SOFS;
1811                         }
1812                         if (active) {
1813                                 u_int sxfrctl0;
1814
1815                                 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
1816                                 sxfrctl0 &= ~FAST20;
1817                                 if (tstate->ultraenb & devinfo->target_mask)
1818                                         sxfrctl0 |= FAST20;
1819                                 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
1820                         }
1821                 }
1822                 if (active) {
1823                         ahc_outb(ahc, SCSIRATE, scsirate);
1824                         if ((ahc->features & AHC_ULTRA2) != 0)
1825                                 ahc_outb(ahc, SCSIOFFSET, offset);
1826                 }
1827
1828                 tinfo->scsirate = scsirate;
1829                 tinfo->curr.period = period;
1830                 tinfo->curr.offset = offset;
1831                 tinfo->curr.ppr_options = ppr_options;
1832
1833                 ahc_send_async(ahc, devinfo->channel, devinfo->target,
1834                                CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
1835                 if (bootverbose) {
1836                         if (offset != 0) {
1837                                 printf("%s: target %d synchronous at %sMHz%s, "
1838                                        "offset = 0x%x\n", ahc_name(ahc),
1839                                        devinfo->target, syncrate->rate,
1840                                        (ppr_options & MSG_EXT_PPR_DT_REQ)
1841                                        ? " DT" : "", offset);
1842                         } else {
1843                                 printf("%s: target %d using "
1844                                        "asynchronous transfers\n",
1845                                        ahc_name(ahc), devinfo->target);
1846                         }
1847                 }
1848         }
1849
1850         update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
1851                                                 tinfo, /*force*/FALSE);
1852
1853         if (update_needed)
1854                 ahc_update_pending_scbs(ahc);
1855 }
1856
1857 /*
1858  * Update the user/goal/curr tables of wide negotiation
1859  * parameters as well as, in the case of a current or active update,
1860  * any data structures on the host controller.  In the case of an
1861  * active update, the specified target is currently talking to us on
1862  * the bus, so the transfer parameter update must take effect
1863  * immediately.
1864  */
1865 void
1866 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1867               u_int width, u_int type, int paused)
1868 {
1869         struct  ahc_initiator_tinfo *tinfo;
1870         struct  ahc_tmode_tstate *tstate;
1871         u_int   oldwidth;
1872         int     active;
1873         int     update_needed;
1874
1875         active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1876         update_needed = 0;
1877         tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1878                                     devinfo->target, &tstate);
1879
1880         if ((type & AHC_TRANS_USER) != 0)
1881                 tinfo->user.width = width;
1882
1883         if ((type & AHC_TRANS_GOAL) != 0)
1884                 tinfo->goal.width = width;
1885
1886         oldwidth = tinfo->curr.width;
1887         if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
1888                 u_int   scsirate;
1889
1890                 update_needed++;
1891                 scsirate =  tinfo->scsirate;
1892                 scsirate &= ~WIDEXFER;
1893                 if (width == MSG_EXT_WDTR_BUS_16_BIT)
1894                         scsirate |= WIDEXFER;
1895
1896                 tinfo->scsirate = scsirate;
1897
1898                 if (active)
1899                         ahc_outb(ahc, SCSIRATE, scsirate);
1900
1901                 tinfo->curr.width = width;
1902
1903                 ahc_send_async(ahc, devinfo->channel, devinfo->target,
1904                                CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
1905                 if (bootverbose) {
1906                         printf("%s: target %d using %dbit transfers\n",
1907                                ahc_name(ahc), devinfo->target,
1908                                8 * (0x01 << width));
1909                 }
1910         }
1911
1912         update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
1913                                                 tinfo, /*force*/FALSE);
1914         if (update_needed)
1915                 ahc_update_pending_scbs(ahc);
1916 }
1917
1918 /*
1919  * Update the current state of tagged queuing for a given target.
1920  */
1921 void
1922 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1923              ahc_queue_alg alg)
1924 {
1925         ahc_platform_set_tags(ahc, devinfo, alg);
1926         ahc_send_async(ahc, devinfo->channel, devinfo->target,
1927                        devinfo->lun, AC_TRANSFER_NEG, &alg);
1928 }
1929
1930 /*
1931  * When the transfer settings for a connection change, update any
1932  * in-transit SCBs to contain the new data so the hardware will
1933  * be set correctly during future (re)selections.
1934  */
1935 static void
1936 ahc_update_pending_scbs(struct ahc_softc *ahc)
1937 {
1938         struct  scb *pending_scb;
1939         int     pending_scb_count;
1940         int     i;
1941         int     paused;
1942         u_int   saved_scbptr;
1943
1944         /*
1945          * Traverse the pending SCB list and ensure that all of the
1946          * SCBs there have the proper settings.
1947          */
1948         pending_scb_count = 0;
1949         LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
1950                 struct ahc_devinfo devinfo;
1951                 struct hardware_scb *pending_hscb;
1952                 struct ahc_initiator_tinfo *tinfo;
1953                 struct ahc_tmode_tstate *tstate;
1954
1955                 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
1956                 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
1957                                             devinfo.our_scsiid,
1958                                             devinfo.target, &tstate);
1959                 pending_hscb = pending_scb->hscb;
1960                 pending_hscb->control &= ~ULTRAENB;
1961                 if ((tstate->ultraenb & devinfo.target_mask) != 0)
1962                         pending_hscb->control |= ULTRAENB;
1963                 pending_hscb->scsirate = tinfo->scsirate;
1964                 pending_hscb->scsioffset = tinfo->curr.offset;
1965                 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
1966                  && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
1967                         pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
1968                         pending_hscb->control &= ~MK_MESSAGE;
1969                 }
1970                 ahc_sync_scb(ahc, pending_scb,
1971                              BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1972                 pending_scb_count++;
1973         }
1974
1975         if (pending_scb_count == 0)
1976                 return;
1977
1978         if (ahc_is_paused(ahc)) {
1979                 paused = 1;
1980         } else {
1981                 paused = 0;
1982                 ahc_pause(ahc);
1983         }
1984
1985         saved_scbptr = ahc_inb(ahc, SCBPTR);
1986         /* Ensure that the hscbs down on the card match the new information */
1987         for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
1988                 struct  hardware_scb *pending_hscb;
1989                 u_int   control;
1990                 u_int   scb_tag;
1991
1992                 ahc_outb(ahc, SCBPTR, i);
1993                 scb_tag = ahc_inb(ahc, SCB_TAG);
1994                 pending_scb = ahc_lookup_scb(ahc, scb_tag);
1995                 if (pending_scb == NULL)
1996                         continue;
1997
1998                 pending_hscb = pending_scb->hscb;
1999                 control = ahc_inb(ahc, SCB_CONTROL);
2000                 control &= ~(ULTRAENB|MK_MESSAGE);
2001                 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2002                 ahc_outb(ahc, SCB_CONTROL, control);
2003                 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2004                 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2005         }
2006         ahc_outb(ahc, SCBPTR, saved_scbptr);
2007
2008         if (paused == 0)
2009                 ahc_unpause(ahc);
2010 }
2011
2012 /**************************** Pathing Information *****************************/
2013 static void
2014 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2015 {
2016         u_int   saved_scsiid;
2017         role_t  role;
2018         int     our_id;
2019
2020         if (ahc_inb(ahc, SSTAT0) & TARGET)
2021                 role = ROLE_TARGET;
2022         else
2023                 role = ROLE_INITIATOR;
2024
2025         if (role == ROLE_TARGET
2026          && (ahc->features & AHC_MULTI_TID) != 0
2027          && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) {
2028                 /* We were selected, so pull our id from TARGIDIN */
2029                 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2030         } else if ((ahc->features & AHC_ULTRA2) != 0)
2031                 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2032         else
2033                 our_id = ahc_inb(ahc, SCSIID) & OID;
2034
2035         saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2036         ahc_compile_devinfo(devinfo,
2037                             our_id,
2038                             SCSIID_TARGET(ahc, saved_scsiid),
2039                             ahc_inb(ahc, SAVED_LUN),
2040                             SCSIID_CHANNEL(ahc, saved_scsiid),
2041                             role);
2042 }
2043
2044 struct ahc_phase_table_entry*
2045 ahc_lookup_phase_entry(int phase)
2046 {
2047         struct ahc_phase_table_entry *entry;
2048         struct ahc_phase_table_entry *last_entry;
2049
2050         /*
2051          * num_phases doesn't include the default entry which
2052          * will be returned if the phase doesn't match.
2053          */
2054         last_entry = &ahc_phase_table[num_phases];
2055         for (entry = ahc_phase_table; entry < last_entry; entry++) {
2056                 if (phase == entry->phase)
2057                         break;
2058         }
2059         return (entry);
2060 }
2061
2062 void
2063 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2064                     u_int lun, char channel, role_t role)
2065 {
2066         devinfo->our_scsiid = our_id;
2067         devinfo->target = target;
2068         devinfo->lun = lun;
2069         devinfo->target_offset = target;
2070         devinfo->channel = channel;
2071         devinfo->role = role;
2072         if (channel == 'B')
2073                 devinfo->target_offset += 8;
2074         devinfo->target_mask = (0x01 << devinfo->target_offset);
2075 }
2076
2077 static void
2078 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2079                 struct scb *scb)
2080 {
2081         role_t  role;
2082         int     our_id;
2083
2084         our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2085         role = ROLE_INITIATOR;
2086         if ((scb->hscb->control & TARGET_SCB) != 0)
2087                 role = ROLE_TARGET;
2088         ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2089                             SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2090 }
2091
2092
2093 /************************ Message Phase Processing ****************************/
2094 static void
2095 ahc_assert_atn(struct ahc_softc *ahc)
2096 {
2097         u_int scsisigo;
2098
2099         scsisigo = ATNO;
2100         if ((ahc->features & AHC_DT) == 0)
2101                 scsisigo |= ahc_inb(ahc, SCSISIGI);
2102         ahc_outb(ahc, SCSISIGO, scsisigo);
2103 }
2104
2105 /*
2106  * When an initiator transaction with the MK_MESSAGE flag either reconnects
2107  * or enters the initial message out phase, we are interrupted.  Fill our
2108  * outgoing message buffer with the appropriate message and beging handing
2109  * the message phase(s) manually.
2110  */
2111 static void
2112 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2113                            struct scb *scb)
2114 {
2115         /*
2116          * To facilitate adding multiple messages together,
2117          * each routine should increment the index and len
2118          * variables instead of setting them explicitly.
2119          */
2120         ahc->msgout_index = 0;
2121         ahc->msgout_len = 0;
2122
2123         if ((scb->flags & SCB_DEVICE_RESET) == 0
2124          && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2125                 u_int identify_msg;
2126
2127                 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2128                 if ((scb->hscb->control & DISCENB) != 0)
2129                         identify_msg |= MSG_IDENTIFY_DISCFLAG;
2130                 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2131                 ahc->msgout_len++;
2132
2133                 if ((scb->hscb->control & TAG_ENB) != 0) {
2134                         ahc->msgout_buf[ahc->msgout_index++] =
2135                             scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2136                         ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2137                         ahc->msgout_len += 2;
2138                 }
2139         }
2140
2141         if (scb->flags & SCB_DEVICE_RESET) {
2142                 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2143                 ahc->msgout_len++;
2144                 ahc_print_path(ahc, scb);
2145                 printf("Bus Device Reset Message Sent\n");
2146                 /*
2147                  * Clear our selection hardware in advance of
2148                  * the busfree.  We may have an entry in the waiting
2149                  * Q for this target, and we don't want to go about
2150                  * selecting while we handle the busfree and blow it
2151                  * away.
2152                  */
2153                 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2154         } else if ((scb->flags & SCB_ABORT) != 0) {
2155                 if ((scb->hscb->control & TAG_ENB) != 0)
2156                         ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2157                 else
2158                         ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2159                 ahc->msgout_len++;
2160                 ahc_print_path(ahc, scb);
2161                 printf("Abort%s Message Sent\n",
2162                        (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2163                 /*
2164                  * Clear our selection hardware in advance of
2165                  * the busfree.  We may have an entry in the waiting
2166                  * Q for this target, and we don't want to go about
2167                  * selecting while we handle the busfree and blow it
2168                  * away.
2169                  */
2170                 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2171         } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2172                 ahc_build_transfer_msg(ahc, devinfo);
2173         } else {
2174                 printf("ahc_intr: AWAITING_MSG for an SCB that "
2175                        "does not have a waiting message\n");
2176                 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2177                        devinfo->target_mask);
2178                 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2179                       "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2180                       ahc_inb(ahc, MSG_OUT), scb->flags);
2181         }
2182
2183         /*
2184          * Clear the MK_MESSAGE flag from the SCB so we aren't
2185          * asked to send this message again.
2186          */
2187         ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2188         scb->hscb->control &= ~MK_MESSAGE;
2189         ahc->msgout_index = 0;
2190         ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2191 }
2192
2193 /*
2194  * Build an appropriate transfer negotiation message for the
2195  * currently active target.
2196  */
2197 static void
2198 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2199 {
2200         /*
2201          * We need to initiate transfer negotiations.
2202          * If our current and goal settings are identical,
2203          * we want to renegotiate due to a check condition.
2204          */
2205         struct  ahc_initiator_tinfo *tinfo;
2206         struct  ahc_tmode_tstate *tstate;
2207         struct  ahc_syncrate *rate;
2208         int     dowide;
2209         int     dosync;
2210         int     doppr;
2211         int     use_ppr;
2212         u_int   period;
2213         u_int   ppr_options;
2214         u_int   offset;
2215
2216         tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2217                                     devinfo->target, &tstate);
2218         /*
2219          * Filter our period based on the current connection.
2220          * If we can't perform DT transfers on this segment (not in LVD
2221          * mode for instance), then our decision to issue a PPR message
2222          * may change.
2223          */
2224         period = tinfo->goal.period;
2225         ppr_options = tinfo->goal.ppr_options;
2226         /* Target initiated PPR is not allowed in the SCSI spec */
2227         if (devinfo->role == ROLE_TARGET)
2228                 ppr_options = 0;
2229         rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2230                                        &ppr_options, devinfo->role);
2231         dowide = tinfo->curr.width != tinfo->goal.width;
2232         dosync = tinfo->curr.period != period;
2233         doppr = tinfo->curr.ppr_options != ppr_options;
2234
2235         if (!dowide && !dosync && !doppr) {
2236                 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2237                 dosync = tinfo->goal.period != 0;
2238                 doppr = tinfo->goal.ppr_options != 0;
2239         }
2240
2241         if (!dowide && !dosync && !doppr) {
2242                 panic("ahc_intr: AWAITING_MSG for negotiation, "
2243                       "but no negotiation needed\n");   
2244         }
2245
2246         use_ppr = (tinfo->curr.transport_version >= 3) || doppr;
2247         /* Target initiated PPR is not allowed in the SCSI spec */
2248         if (devinfo->role == ROLE_TARGET)
2249                 use_ppr = 0;
2250
2251         /*
2252          * Both the PPR message and SDTR message require the
2253          * goal syncrate to be limited to what the target device
2254          * is capable of handling (based on whether an LVD->SE
2255          * expander is on the bus), so combine these two cases.
2256          * Regardless, guarantee that if we are using WDTR and SDTR
2257          * messages that WDTR comes first.
2258          */
2259         if (use_ppr || (dosync && !dowide)) {
2260
2261                 offset = tinfo->goal.offset;
2262                 ahc_validate_offset(ahc, tinfo, rate, &offset,
2263                                     use_ppr ? tinfo->goal.width
2264                                             : tinfo->curr.width,
2265                                     devinfo->role);
2266                 if (use_ppr) {
2267                         ahc_construct_ppr(ahc, devinfo, period, offset,
2268                                           tinfo->goal.width, ppr_options);
2269                 } else {
2270                         ahc_construct_sdtr(ahc, devinfo, period, offset);
2271                 }
2272         } else {
2273                 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
2274         }
2275 }
2276
2277 /*
2278  * Build a synchronous negotiation message in our message
2279  * buffer based on the input parameters.
2280  */
2281 static void
2282 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2283                    u_int period, u_int offset)
2284 {
2285         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2286         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN;
2287         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR;
2288         ahc->msgout_buf[ahc->msgout_index++] = period;
2289         ahc->msgout_buf[ahc->msgout_index++] = offset;
2290         ahc->msgout_len += 5;
2291         if (bootverbose) {
2292                 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
2293                        ahc_name(ahc), devinfo->channel, devinfo->target,
2294                        devinfo->lun, period, offset);
2295         }
2296 }
2297
2298 /*
2299  * Build a wide negotiateion message in our message
2300  * buffer based on the input parameters.
2301  */
2302 static void
2303 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2304                    u_int bus_width)
2305 {
2306         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2307         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN;
2308         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR;
2309         ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2310         ahc->msgout_len += 4;
2311         if (bootverbose) {
2312                 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
2313                        ahc_name(ahc), devinfo->channel, devinfo->target,
2314                        devinfo->lun, bus_width);
2315         }
2316 }
2317
2318 /*
2319  * Build a parallel protocol request message in our message
2320  * buffer based on the input parameters.
2321  */
2322 static void
2323 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2324                   u_int period, u_int offset, u_int bus_width,
2325                   u_int ppr_options)
2326 {
2327         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2328         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN;
2329         ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR;
2330         ahc->msgout_buf[ahc->msgout_index++] = period;
2331         ahc->msgout_buf[ahc->msgout_index++] = 0;
2332         ahc->msgout_buf[ahc->msgout_index++] = offset;
2333         ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2334         ahc->msgout_buf[ahc->msgout_index++] = ppr_options;
2335         ahc->msgout_len += 8;
2336         if (bootverbose) {
2337                 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
2338                        "offset %x, ppr_options %x\n", ahc_name(ahc),
2339                        devinfo->channel, devinfo->target, devinfo->lun,
2340                        bus_width, period, offset, ppr_options);
2341         }
2342 }
2343
2344 /*
2345  * Clear any active message state.
2346  */
2347 static void
2348 ahc_clear_msg_state(struct ahc_softc *ahc)
2349 {
2350         ahc->msgout_len = 0;
2351         ahc->msgin_index = 0;
2352         ahc->msg_type = MSG_TYPE_NONE;
2353         if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
2354                 /*
2355                  * The target didn't care to respond to our
2356                  * message request, so clear ATN.
2357                  */
2358                 ahc_outb(ahc, CLRSINT1, CLRATNO);
2359         }
2360         ahc_outb(ahc, MSG_OUT, MSG_NOOP);
2361 }
2362
2363 /*
2364  * Manual message loop handler.
2365  */
2366 static void
2367 ahc_handle_message_phase(struct ahc_softc *ahc)
2368
2369         struct  ahc_devinfo devinfo;
2370         u_int   bus_phase;
2371         int     end_session;
2372
2373         ahc_fetch_devinfo(ahc, &devinfo);
2374         end_session = FALSE;
2375         bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2376
2377 reswitch:
2378         switch (ahc->msg_type) {
2379         case MSG_TYPE_INITIATOR_MSGOUT:
2380         {
2381                 int lastbyte;
2382                 int phasemis;
2383                 int msgdone;
2384
2385                 if (ahc->msgout_len == 0)
2386                         panic("HOST_MSG_LOOP interrupt with no active message");
2387
2388                 phasemis = bus_phase != P_MESGOUT;
2389                 if (phasemis) {
2390                         if (bus_phase == P_MESGIN) {
2391                                 /*
2392                                  * Change gears and see if
2393                                  * this messages is of interest to
2394                                  * us or should be passed back to
2395                                  * the sequencer.
2396                                  */
2397                                 ahc_outb(ahc, CLRSINT1, CLRATNO);
2398                                 ahc->send_msg_perror = FALSE;
2399                                 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
2400                                 ahc->msgin_index = 0;
2401                                 goto reswitch;
2402                         }
2403                         end_session = TRUE;
2404                         break;
2405                 }
2406
2407                 if (ahc->send_msg_perror) {
2408                         ahc_outb(ahc, CLRSINT1, CLRATNO);
2409                         ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2410                         ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
2411                         break;
2412                 }
2413
2414                 msgdone = ahc->msgout_index == ahc->msgout_len;
2415                 if (msgdone) {
2416                         /*
2417                          * The target has requested a retry.
2418                          * Re-assert ATN, reset our message index to
2419                          * 0, and try again.
2420                          */
2421                         ahc->msgout_index = 0;
2422                         ahc_assert_atn(ahc);
2423                 }
2424
2425                 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
2426                 if (lastbyte) {
2427                         /* Last byte is signified by dropping ATN */
2428                         ahc_outb(ahc, CLRSINT1, CLRATNO);
2429                 }
2430
2431                 /*
2432                  * Clear our interrupt status and present
2433                  * the next byte on the bus.
2434                  */
2435                 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2436                 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2437                 break;
2438         }
2439         case MSG_TYPE_INITIATOR_MSGIN:
2440         {
2441                 int phasemis;
2442                 int message_done;
2443
2444                 phasemis = bus_phase != P_MESGIN;
2445
2446                 if (phasemis) {
2447                         ahc->msgin_index = 0;
2448                         if (bus_phase == P_MESGOUT
2449                          && (ahc->send_msg_perror == TRUE
2450                           || (ahc->msgout_len != 0
2451                            && ahc->msgout_index == 0))) {
2452                                 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2453                                 goto reswitch;
2454                         }
2455                         end_session = TRUE;
2456                         break;
2457                 }
2458
2459                 /* Pull the byte in without acking it */
2460                 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
2461
2462                 message_done = ahc_parse_msg(ahc, &devinfo);
2463
2464                 if (message_done) {
2465                         /*
2466                          * Clear our incoming message buffer in case there
2467                          * is another message following this one.
2468                          */
2469                         ahc->msgin_index = 0;
2470
2471                         /*
2472                          * If this message illicited a response,
2473                          * assert ATN so the target takes us to the
2474                          * message out phase.
2475                          */
2476                         if (ahc->msgout_len != 0)