v2.4.8 -> v2.4.8.1
[opensuse:kernel.git] / drivers / ieee1394 / ohci1394.h
1 /*
2  * ohci1394.h - driver for OHCI 1394 boards
3  * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
4  *                        Gord Peters <GordPeters@smarttech.com>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software Foundation,
18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 #ifndef _OHCI1394_H
22 #define _OHCI1394_H
23
24 #include "ieee1394_types.h"
25
26 #define OHCI1394_DRIVER_NAME      "ohci1394"
27
28 #define OHCI1394_MAX_AT_REQ_RETRIES     0x2
29 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
30 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
31 #define OHCI1394_MAX_SELF_ID_ERRORS     16
32
33 #define AR_REQ_NUM_DESC         4               /* number of AR req descriptors */
34 #define AR_REQ_BUF_SIZE         PAGE_SIZE       /* size of AR req buffers */
35 #define AR_REQ_SPLIT_BUF_SIZE   PAGE_SIZE       /* split packet buffer */
36
37 #define AR_RESP_NUM_DESC        4               /* number of AR resp descriptors */
38 #define AR_RESP_BUF_SIZE        PAGE_SIZE       /* size of AR resp buffers */
39 #define AR_RESP_SPLIT_BUF_SIZE  PAGE_SIZE       /* split packet buffer */
40
41 #define IR_NUM_DESC             16              /* number of IR descriptors */
42 #define IR_BUF_SIZE             PAGE_SIZE       /* 4096 bytes/buffer */
43 #define IR_SPLIT_BUF_SIZE       PAGE_SIZE       /* split packet buffer */
44
45 #define IT_NUM_DESC             16      /* number of IT descriptors */
46
47 #define AT_REQ_NUM_DESC         32      /* number of AT req descriptors */
48 #define AT_RESP_NUM_DESC        32      /* number of AT resp descriptors */
49
50 #define OHCI_LOOP_COUNT         100     /* Number of loops for reg read waits */
51
52 #define OHCI_CONFIG_ROM_LEN     1024    /* Length of the mapped configrom space */
53
54 #define OHCI1394_SI_DMA_BUF_SIZE        8192 /* length of the selfid buffer */
55
56 /* PCI configuration space addresses */
57 #define OHCI1394_PCI_HCI_Control 0x40
58
59 struct dma_cmd {
60         u32 control;
61         u32 address;
62         u32 branchAddress;
63         u32 status;
64 };
65
66 /*
67  * FIXME:
68  * It is important that a single at_dma_prg does not cross a page boundary
69  * The proper way to do it would be to do the check dynamically as the
70  * programs are inserted into the AT fifo.
71  */
72 struct at_dma_prg {
73         struct dma_cmd begin;
74         quadlet_t data[4];
75         struct dma_cmd end;
76         quadlet_t pad[4]; /* FIXME: quick hack for memory alignment */
77 };
78
79 /* DMA receive context */
80 struct dma_rcv_ctx {
81         void *ohci;
82         int ctx;
83         unsigned int num_desc;
84
85         unsigned int buf_size;
86         unsigned int split_buf_size;
87
88         /* dma block descriptors */
89         struct dma_cmd **prg_cpu;
90         dma_addr_t *prg_bus;
91
92         /* dma buffers */
93         quadlet_t **buf_cpu;
94         dma_addr_t *buf_bus;
95
96         unsigned int buf_ind;
97         unsigned int buf_offset;
98         quadlet_t *spb;
99         spinlock_t lock;
100         struct tasklet_struct task;
101         int ctrlClear;
102         int ctrlSet;
103         int cmdPtr;
104 };
105
106 /* DMA transmit context */      
107 struct dma_trm_ctx {
108         void *ohci;
109         int ctx;
110         unsigned int num_desc;
111
112         /* dma block descriptors */
113         struct at_dma_prg **prg_cpu;
114         dma_addr_t *prg_bus;
115
116         unsigned int prg_ind;
117         unsigned int sent_ind;
118         int free_prgs;
119         quadlet_t *branchAddrPtr;
120
121         /* list of packets inserted in the AT FIFO */
122         struct hpsb_packet *fifo_first;
123         struct hpsb_packet *fifo_last;
124
125         /* list of pending packets to be inserted in the AT FIFO */
126         struct hpsb_packet *pending_first;
127         struct hpsb_packet *pending_last;
128
129         spinlock_t lock;
130         struct tasklet_struct task;
131         int ctrlClear;
132         int ctrlSet;
133         int cmdPtr;
134 };
135
136 /* video device template */
137 struct video_template {
138         void (*irq_handler) (int card, quadlet_t isoRecvEvent, 
139                              quadlet_t isoXmitEvent);
140 };
141
142
143 struct ti_ohci {
144         int id; /* sequential card number */
145
146         struct list_head list;
147
148         struct pci_dev *dev;
149
150         u32 state;
151         
152         /* remapped memory spaces */
153         void *registers; 
154
155         /* dma buffer for self-id packets */
156         quadlet_t *selfid_buf_cpu;
157         dma_addr_t selfid_buf_bus;
158         
159         /* buffer for csr config rom */
160         quadlet_t *csr_config_rom_cpu; 
161         dma_addr_t csr_config_rom_bus; 
162         int csr_config_rom_length;
163
164         unsigned int max_packet_size;
165
166         /* async receive */
167         struct dma_rcv_ctx *ar_resp_context;
168         struct dma_rcv_ctx *ar_req_context;
169
170         /* async transmit */
171         struct dma_trm_ctx *at_resp_context;
172         struct dma_trm_ctx *at_req_context;
173
174         /* iso receive */
175         struct dma_rcv_ctx *ir_context;
176         spinlock_t IR_channel_lock;
177         int nb_iso_rcv_ctx;
178
179         /* iso transmit */
180         struct dma_trm_ctx *it_context;
181         int nb_iso_xmit_ctx;
182
183         u64 ISO_channel_usage;
184
185         /* IEEE-1394 part follows */
186         struct hpsb_host *host;
187
188         int phyid, isroot;
189
190         spinlock_t phy_reg_lock;
191         spinlock_t event_lock;
192
193         int self_id_errors;
194         int NumBusResets;
195
196         /* video device */
197         struct video_template *video_tmpl;
198
199         /* Swap the selfid buffer? */
200         unsigned int selfid_swap:1;
201         /* Swap the payload? */
202         unsigned int payload_swap:1;
203 };
204
205 static inline int cross_bound(unsigned long addr, unsigned int size)
206 {
207         int cross=0;
208         if (size>PAGE_SIZE) {
209                 cross = size/PAGE_SIZE;
210                 size -= cross*PAGE_SIZE;
211         }
212         if ((PAGE_SIZE-addr%PAGE_SIZE)<size)
213                 cross++;
214         return cross;
215 }
216
217 /*
218  * Register read and write helper functions.
219  */
220 static inline void reg_write(const struct ti_ohci *ohci, int offset, u32 data)
221 {
222         writel(data, ohci->registers + offset);
223 }
224
225 static inline u32 reg_read(const struct ti_ohci *ohci, int offset)
226 {
227         return readl(ohci->registers + offset);
228 }
229
230
231 /* 2 KiloBytes of register space */
232 #define OHCI1394_REGISTER_SIZE                0x800       
233
234 /* register map */
235 #define OHCI1394_Version                      0x000
236 #define OHCI1394_GUID_ROM                     0x004
237 #define OHCI1394_ATRetries                    0x008
238 #define OHCI1394_CSRData                      0x00C
239 #define OHCI1394_CSRCompareData               0x010
240 #define OHCI1394_CSRControl                   0x014
241 #define OHCI1394_ConfigROMhdr                 0x018
242 #define OHCI1394_BusID                        0x01C
243 #define OHCI1394_BusOptions                   0x020
244 #define OHCI1394_GUIDHi                       0x024
245 #define OHCI1394_GUIDLo                       0x028
246 #define OHCI1394_ConfigROMmap                 0x034
247 #define OHCI1394_PostedWriteAddressLo         0x038
248 #define OHCI1394_PostedWriteAddressHi         0x03C
249 #define OHCI1394_VendorID                     0x040
250 #define OHCI1394_HCControlSet                 0x050
251 #define OHCI1394_HCControlClear               0x054
252 #define OHCI1394_SelfIDBuffer                 0x064
253 #define OHCI1394_SelfIDCount                  0x068
254 #define OHCI1394_IRMultiChanMaskHiSet         0x070
255 #define OHCI1394_IRMultiChanMaskHiClear       0x074
256 #define OHCI1394_IRMultiChanMaskLoSet         0x078
257 #define OHCI1394_IRMultiChanMaskLoClear       0x07C
258 #define OHCI1394_IntEventSet                  0x080
259 #define OHCI1394_IntEventClear                0x084
260 #define OHCI1394_IntMaskSet                   0x088
261 #define OHCI1394_IntMaskClear                 0x08C
262 #define OHCI1394_IsoXmitIntEventSet           0x090
263 #define OHCI1394_IsoXmitIntEventClear         0x094
264 #define OHCI1394_IsoXmitIntMaskSet            0x098
265 #define OHCI1394_IsoXmitIntMaskClear          0x09C
266 #define OHCI1394_IsoRecvIntEventSet           0x0A0
267 #define OHCI1394_IsoRecvIntEventClear         0x0A4
268 #define OHCI1394_IsoRecvIntMaskSet            0x0A8
269 #define OHCI1394_IsoRecvIntMaskClear          0x0AC
270 #define OHCI1394_FairnessControl              0x0DC
271 #define OHCI1394_LinkControlSet               0x0E0
272 #define OHCI1394_LinkControlClear             0x0E4
273 #define OHCI1394_NodeID                       0x0E8
274 #define OHCI1394_PhyControl                   0x0EC
275 #define OHCI1394_IsochronousCycleTimer        0x0F0
276 #define OHCI1394_AsReqFilterHiSet             0x100
277 #define OHCI1394_AsReqFilterHiClear           0x104
278 #define OHCI1394_AsReqFilterLoSet             0x108
279 #define OHCI1394_AsReqFilterLoClear           0x10C
280 #define OHCI1394_PhyReqFilterHiSet            0x110
281 #define OHCI1394_PhyReqFilterHiClear          0x114
282 #define OHCI1394_PhyReqFilterLoSet            0x118
283 #define OHCI1394_PhyReqFilterLoClear          0x11C
284 #define OHCI1394_PhyUpperBound                0x120
285 #define OHCI1394_AsReqTrContextControlSet     0x180
286 #define OHCI1394_AsReqTrContextControlClear   0x184
287 #define OHCI1394_AsReqTrCommandPtr            0x18C
288 #define OHCI1394_AsRspTrContextControlSet     0x1A0
289 #define OHCI1394_AsRspTrContextControlClear   0x1A4
290 #define OHCI1394_AsRspTrCommandPtr            0x1AC
291 #define OHCI1394_AsReqRcvContextControlSet    0x1C0
292 #define OHCI1394_AsReqRcvContextControlClear  0x1C4
293 #define OHCI1394_AsReqRcvCommandPtr           0x1CC
294 #define OHCI1394_AsRspRcvContextControlSet    0x1E0
295 #define OHCI1394_AsRspRcvContextControlClear  0x1E4
296 #define OHCI1394_AsRspRcvCommandPtr           0x1EC
297
298 /* Isochronous transmit registers */
299 /* Add (32 * n) for context n */
300 #define OHCI1394_IsoXmitContextControlSet     0x200
301 #define OHCI1394_IsoXmitContextControlClear   0x204
302 #define OHCI1394_IsoXmitCommandPtr            0x20C
303
304 /* Isochronous receive registers */
305 /* Add (32 * n) for context n */
306 #define OHCI1394_IsoRcvContextControlSet      0x400
307 #define OHCI1394_IsoRcvContextControlClear    0x404
308 #define OHCI1394_IsoRcvCommandPtr             0x40C
309 #define OHCI1394_IsoRcvContextMatch           0x410
310
311 /* Interrupts Mask/Events */
312
313 #define OHCI1394_reqTxComplete           0x00000001
314 #define OHCI1394_respTxComplete          0x00000002
315 #define OHCI1394_ARRQ                    0x00000004
316 #define OHCI1394_ARRS                    0x00000008
317 #define OHCI1394_RQPkt                   0x00000010
318 #define OHCI1394_RSPkt                   0x00000020
319 #define OHCI1394_isochTx                 0x00000040
320 #define OHCI1394_isochRx                 0x00000080
321 #define OHCI1394_postedWriteErr          0x00000100
322 #define OHCI1394_lockRespErr             0x00000200
323 #define OHCI1394_selfIDComplete          0x00010000
324 #define OHCI1394_busReset                0x00020000
325 #define OHCI1394_phy                     0x00080000
326 #define OHCI1394_cycleSynch              0x00100000
327 #define OHCI1394_cycle64Seconds          0x00200000
328 #define OHCI1394_cycleLost               0x00400000
329 #define OHCI1394_cycleInconsistent       0x00800000
330 #define OHCI1394_unrecoverableError      0x01000000
331 #define OHCI1394_cycleTooLong            0x02000000
332 #define OHCI1394_phyRegRcvd              0x04000000
333 #define OHCI1394_masterIntEnable         0x80000000
334
335 #define OUTPUT_MORE                      0x00000000
336 #define OUTPUT_MORE_IMMEDIATE            0x02000000
337 #define OUTPUT_LAST                      0x103c0000
338 #define OUTPUT_LAST_IMMEDIATE            0x123c0000
339
340 #define DMA_SPEED_100                    0x0
341 #define DMA_SPEED_200                    0x1
342 #define DMA_SPEED_400                    0x2
343
344 #define OHCI1394_TCODE_PHY               0xE
345
346 void ohci1394_stop_context(struct ti_ohci *ohci, int reg, char *msg);
347 struct ti_ohci *ohci1394_get_struct(int card_num);
348 int ohci1394_register_video(struct ti_ohci *ohci,
349                             struct video_template *tmpl);
350 void ohci1394_unregister_video(struct ti_ohci *ohci,
351                                struct video_template *tmpl);
352
353 #endif
354