v2.4.8 -> v2.4.8.1
[opensuse:kernel.git] / drivers / ieee1394 / ohci1394.c
1 /*
2  * ohci1394.c - driver for OHCI 1394 boards
3  * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
4  *                        Gord Peters <GordPeters@smarttech.com>
5  *              2001      Ben Collins <bcollins@debian.org>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software Foundation,
19  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20  */
21
22 /*
23  * Things known to be working:
24  * . Async Request Transmit
25  * . Async Response Receive
26  * . Async Request Receive
27  * . Async Response Transmit
28  * . Iso Receive
29  * . DMA mmap for iso receive
30  * . Config ROM generation
31  *
32  * Things implemented, but still in test phase:
33  * . Iso Transmit
34  * 
35  * Things not implemented:
36  * . Async Stream Packets
37  * . DMA error recovery
38  *
39  * Known bugs:
40  * . Apple PowerBook detected but not working yet (still true?)
41  */
42
43 /* 
44  * Acknowledgments:
45  *
46  * Adam J Richter <adam@yggdrasil.com>
47  *  . Use of pci_class to find device
48  *
49  * Andreas Tobler <toa@pop.agri.ch>
50  *  . Updated proc_fs calls
51  *
52  * Emilie Chung <emilie.chung@axis.com>
53  *  . Tip on Async Request Filter
54  *
55  * Pascal Drolet <pascal.drolet@informission.ca>
56  *  . Various tips for optimization and functionnalities
57  *
58  * Robert Ficklin <rficklin@westengineering.com>
59  *  . Loop in irq_handler
60  *
61  * James Goodwin <jamesg@Filanet.com>
62  *  . Various tips on initialization, self-id reception, etc.
63  *
64  * Albrecht Dress <ad@mpifr-bonn.mpg.de>
65  *  . Apple PowerBook detection
66  *
67  * Daniel Kobras <daniel.kobras@student.uni-tuebingen.de>
68  *  . Reset the board properly before leaving + misc cleanups
69  *
70  * Leon van Stuivenberg <leonvs@iae.nl>
71  *  . Bug fixes
72  *
73  * Ben Collins <bcollins@debian.org>
74  *  . Working big-endian support
75  *  . Updated to 2.4.x module scheme (PCI aswell)
76  *  . Removed procfs support since it trashes random mem
77  *  . Config ROM generation
78  */
79
80 #include <linux/config.h>
81 #include <linux/kernel.h>
82 #include <linux/list.h>
83 #include <linux/slab.h>
84 #include <linux/interrupt.h>
85 #include <linux/wait.h>
86 #include <linux/errno.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/fs.h>
90 #include <linux/poll.h>
91 #include <asm/byteorder.h>
92 #include <asm/atomic.h>
93 #include <asm/io.h>
94 #include <asm/uaccess.h>
95 #include <linux/tqueue.h>
96 #include <linux/delay.h>
97 #include <linux/spinlock.h>
98
99 #include <asm/pgtable.h>
100 #include <asm/page.h>
101 #include <linux/sched.h>
102 #include <asm/segment.h>
103 #include <linux/types.h>
104 #include <linux/wrapper.h>
105 #include <linux/vmalloc.h>
106 #include <linux/init.h>
107
108 #include "ieee1394.h"
109 #include "ieee1394_types.h"
110 #include "hosts.h"
111 #include "ieee1394_core.h"
112 #include "highlevel.h"
113 #include "ohci1394.h"
114
115
116 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
117 #define OHCI1394_DEBUG
118 #endif
119
120 #ifdef DBGMSG
121 #undef DBGMSG
122 #endif
123
124 #ifdef OHCI1394_DEBUG
125 #define DBGMSG(card, fmt, args...) \
126 printk(KERN_INFO "ohci1394_%d: " fmt "\n" , card , ## args)
127 #else
128 #define DBGMSG(card, fmt, args...)
129 #endif
130
131 #ifdef CONFIG_IEEE1394_OHCI_DMA_DEBUG
132 #define OHCI_DMA_ALLOC(fmt, args...) \
133         HPSB_ERR("ohci1394("__FUNCTION__")alloc(%d): "fmt, \
134                 ++global_outstanding_dmas, ## args)
135 #define OHCI_DMA_FREE(fmt, args...) \
136         HPSB_ERR("ohci1394("__FUNCTION__")free(%d): "fmt, \
137                 --global_outstanding_dmas, ## args)
138 u32 global_outstanding_dmas = 0;
139 #else
140 #define OHCI_DMA_ALLOC(fmt, args...)
141 #define OHCI_DMA_FREE(fmt, args...)
142 #endif
143
144 /* print general (card independent) information */
145 #define PRINT_G(level, fmt, args...) \
146 printk(level "ohci1394: " fmt "\n" , ## args)
147
148 /* print card specific information */
149 #define PRINT(level, card, fmt, args...) \
150 printk(level "ohci1394_%d: " fmt "\n" , card , ## args)
151
152 #define FAIL(fmt, args...)                              \
153 do {                                                    \
154         PRINT_G(KERN_ERR, fmt , ## args);               \
155         remove_card(ohci);                              \
156         return 1;                                       \
157 } while(0)
158
159 #define PCI_CLASS_FIREWIRE_OHCI     ((PCI_CLASS_SERIAL_FIREWIRE << 8) | 0x10)
160
161 static struct pci_device_id ohci1394_pci_tbl[] __devinitdata = {
162         {
163                 class:          PCI_CLASS_FIREWIRE_OHCI,
164                 class_mask:     0x00ffffff,
165                 vendor:         PCI_ANY_ID,
166                 device:         PCI_ANY_ID,
167                 subvendor:      PCI_ANY_ID,
168                 subdevice:      PCI_ANY_ID,
169         },
170         { 0, },
171 };
172 MODULE_DEVICE_TABLE(pci, ohci1394_pci_tbl);
173
174 static char version[] __devinitdata =
175         "v0.51 08/08/01 Ben Collins <bcollins@debian.org>";
176
177 /* Module Parameters */
178 MODULE_PARM(attempt_root,"i");
179 MODULE_PARM_DESC(attempt_root, "Attempt to make the host root.");
180 static int attempt_root = 0;
181
182 #ifdef __LITTLE_ENDIAN
183 /* Don't waste cycles on same sex byte swaps */
184 #define packet_swab(w,x,y,z)
185 #define block_swab32(x,y)
186 #else
187 static void packet_swab(quadlet_t *data, char tcode, int len, int payload_swap);
188 static __inline__ void block_swab32(quadlet_t *data, size_t size);
189 #endif
190
191 static unsigned int card_id_counter = 0;
192
193 static void dma_trm_tasklet(unsigned long data);
194 static void remove_card(struct ti_ohci *ohci);
195 static void dma_trm_reset(struct dma_trm_ctx *d);
196
197 /***********************************
198  * IEEE-1394 functionality section *
199  ***********************************/
200
201 static u8 get_phy_reg(struct ti_ohci *ohci, u8 addr) 
202 {
203         int i, flags;
204         quadlet_t r;
205
206         spin_lock_irqsave (&ohci->phy_reg_lock, flags);
207
208         reg_write(ohci, OHCI1394_PhyControl, (((u16)addr << 8) & 0x00000f00) | 0x00008000);
209
210         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
211                 if (reg_read(ohci, OHCI1394_PhyControl) & 0x80000000)
212                         break;
213
214                 mdelay(1);
215         }
216
217         r = reg_read(ohci, OHCI1394_PhyControl);
218
219         if (i >= OHCI_LOOP_COUNT)
220                 PRINT (KERN_ERR, ohci->id, "Get PHY Reg timeout [0x%08x/0x%08x/%d]",
221                        r, r & 0x80000000, i);
222   
223         spin_unlock_irqrestore (&ohci->phy_reg_lock, flags);
224      
225         return (r & 0x00ff0000) >> 16;
226 }
227
228 static void set_phy_reg(struct ti_ohci *ohci, u8 addr, u8 data)
229 {
230         int i, flags;
231         u32 r;
232
233         spin_lock_irqsave (&ohci->phy_reg_lock, flags);
234
235         reg_write(ohci, OHCI1394_PhyControl, 0x00004000 | (((u16)addr << 8) & 0x00000f00) | data);
236
237         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
238                 r = reg_read(ohci, OHCI1394_PhyControl);
239                 if (!(r & 0x00004000))
240                         break;
241
242                 mdelay(1);
243         }
244
245         if (i == OHCI_LOOP_COUNT)
246                 PRINT (KERN_ERR, ohci->id, "Set PHY Reg timeout [0x%08x/0x%08x/%d]",
247                        r, r & 0x00004000, i);
248
249         spin_unlock_irqrestore (&ohci->phy_reg_lock, flags);
250
251         return;
252 }
253
254 /* Or's our value into the current value */
255 static void set_phy_reg_mask(struct ti_ohci *ohci, u8 addr, u8 data)
256 {
257         u8 old;
258
259         old = get_phy_reg (ohci, addr);
260         old |= data;
261         set_phy_reg (ohci, addr, old);
262
263         return;
264 }
265
266 static void handle_selfid(struct ti_ohci *ohci, struct hpsb_host *host,
267                                 int phyid, int isroot)
268 {
269         quadlet_t *q = ohci->selfid_buf_cpu;
270         quadlet_t self_id_count=reg_read(ohci, OHCI1394_SelfIDCount);
271         size_t size;
272         quadlet_t q0, q1;
273
274         mdelay(10);
275
276         /* Check status of self-id reception */
277
278         if (ohci->selfid_swap)
279                 q0 = le32_to_cpu(q[0]);
280         else
281                 q0 = q[0];
282
283         if ((self_id_count & 0x80000000) || 
284             ((self_id_count & 0x00FF0000) != (q0 & 0x00FF0000))) {
285                 PRINT(KERN_ERR, ohci->id, 
286                       "Error in reception of SelfID packets [0x%08x/0x%08x]",
287                       self_id_count, q0);
288
289                 /* Tip by James Goodwin <jamesg@Filanet.com>:
290                  * We had an error, generate another bus reset in response.  */
291                 if (ohci->self_id_errors<OHCI1394_MAX_SELF_ID_ERRORS) {
292                         set_phy_reg_mask (ohci, 1, 0x40);
293                         ohci->self_id_errors++;
294                 } else {
295                         PRINT(KERN_ERR, ohci->id, 
296                               "Too many errors on SelfID error reception, giving up!");
297                 }
298                 return;
299         }
300         
301         size = ((self_id_count & 0x00001FFC) >> 2) - 1;
302         q++;
303
304         while (size > 0) {
305                 if (ohci->selfid_swap) {
306                         q0 = le32_to_cpu(q[0]);
307                         q1 = le32_to_cpu(q[1]);
308                 } else {
309                         q0 = q[0];
310                         q1 = q[1];
311                 }
312                 
313                 if (q0 == ~q1) {
314                         DBGMSG (ohci->id, "SelfID packet 0x%x received", q0);
315                         hpsb_selfid_received(host, cpu_to_be32(q0));
316                         if (((q0 & 0x3f000000) >> 24) == phyid)
317                                 DBGMSG (ohci->id, "SelfID for this node is 0x%08x", q0);
318                 } else {
319                         PRINT(KERN_ERR, ohci->id,
320                               "SelfID is inconsistent [0x%08x/0x%08x]", q0, q1);
321                 }
322                 q += 2;
323                 size -= 2;
324         }
325
326         DBGMSG(ohci->id, "SelfID complete");
327
328         hpsb_selfid_complete(host, phyid, isroot);
329
330         return;
331 }
332
333 static int ohci_soft_reset(struct ti_ohci *ohci) {
334         int i;
335
336         reg_write(ohci, OHCI1394_HCControlSet, 0x00010000);
337   
338         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
339                 if (reg_read(ohci, OHCI1394_HCControlSet) & 0x00010000)
340                         break;
341                 mdelay(1);
342         }
343
344         DBGMSG (ohci->id, "Soft reset finished");
345
346         return 0;
347 }
348
349 static int run_context(struct ti_ohci *ohci, int reg, char *msg)
350 {
351         u32 nodeId;
352
353         /* check that the node id is valid */
354         nodeId = reg_read(ohci, OHCI1394_NodeID);
355         if (!(nodeId&0x80000000)) {
356                 PRINT(KERN_ERR, ohci->id, 
357                       "Running dma failed because Node ID is not valid");
358                 return -1;
359         }
360
361         /* check that the node number != 63 */
362         if ((nodeId&0x3f)==63) {
363                 PRINT(KERN_ERR, ohci->id, 
364                       "Running dma failed because Node ID == 63");
365                 return -1;
366         }
367         
368         /* Run the dma context */
369         reg_write(ohci, reg, 0x8000);
370         
371         if (msg) PRINT(KERN_DEBUG, ohci->id, "%s", msg);
372         
373         return 0;
374 }
375
376 /* Generate the dma receive prgs and start the context */
377 static void initialize_dma_rcv_ctx(struct dma_rcv_ctx *d)
378 {
379         struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
380         int i;
381
382         ohci1394_stop_context(ohci, d->ctrlClear, NULL);
383
384         for (i=0; i<d->num_desc; i++) {
385                 
386                 d->prg_cpu[i]->control =
387                    cpu_to_le32((0x280C << 16) | d->buf_size);
388
389                 /* End of descriptor list? */
390                 if ((i+1) < d->num_desc) {
391                         d->prg_cpu[i]->branchAddress =
392                                 cpu_to_le32((d->prg_bus[i+1] & 0xfffffff0) | 0x1);
393                 } else {
394                         d->prg_cpu[i]->branchAddress =
395                                 cpu_to_le32((d->prg_bus[0] & 0xfffffff0));
396                 }
397
398                 d->prg_cpu[i]->address = cpu_to_le32(d->buf_bus[i]);
399                 d->prg_cpu[i]->status = cpu_to_le32(d->buf_size);
400         }
401
402         d->buf_ind = 0;
403         d->buf_offset = 0;
404
405         /* Tell the controller where the first AR program is */
406         reg_write(ohci, d->cmdPtr, d->prg_bus[0] | 0x1);
407
408         /* Run AR context */
409         reg_write(ohci, d->ctrlSet, 0x00008000);
410
411         DBGMSG(ohci->id, "Receive DMA ctx=%d initialized", d->ctx);
412 }
413
414 /* Initialize the dma transmit context */
415 static void initialize_dma_trm_ctx(struct dma_trm_ctx *d)
416 {
417         struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
418
419         /* Stop the context */
420         ohci1394_stop_context(ohci, d->ctrlClear, NULL);
421
422         d->prg_ind = 0;
423         d->sent_ind = 0;
424         d->free_prgs = d->num_desc;
425         d->branchAddrPtr = NULL;
426         d->fifo_first = NULL;
427         d->fifo_last = NULL;
428         d->pending_first = NULL;
429         d->pending_last = NULL;
430
431         DBGMSG(ohci->id, "Transmit DMA ctx=%d initialized", d->ctx);
432 }
433
434 /* Count the number of available iso contexts */
435 static int get_nb_iso_ctx(struct ti_ohci *ohci, int reg)
436 {
437         int i,ctx=0;
438         u32 tmp;
439
440         reg_write(ohci, reg, 0xffffffff);
441         tmp = reg_read(ohci, reg);
442         
443         DBGMSG(ohci->id,"Iso contexts reg: %08x implemented: %08x", reg, tmp);
444
445         /* Count the number of contexts */
446         for(i=0; i<32; i++) {
447                 if(tmp & 1) ctx++;
448                 tmp >>= 1;
449         }
450         return ctx;
451 }
452
453 static void ohci_init_config_rom(struct ti_ohci *ohci);
454
455 /* Global initialization */
456 static int ohci_initialize(struct hpsb_host *host)
457 {
458         struct ti_ohci *ohci=host->hostdata;
459         int retval, i;
460         quadlet_t buf;
461
462         spin_lock_init(&ohci->phy_reg_lock);
463         spin_lock_init(&ohci->event_lock);
464   
465         /* Soft reset */
466         if ((retval = ohci_soft_reset(ohci)) < 0)
467                 return retval;
468
469         /* Put some defaults to these undefined bus options */
470         buf = reg_read(ohci, OHCI1394_BusOptions);
471         buf |=  0x60000000; /* Enable CMC and ISC */
472         buf &= ~0x00ff0000; /* XXX: Set cyc_clk_acc to zero for now */
473         buf &= ~0x98000000; /* Disable PMC, IRMC and BMC */
474         reg_write(ohci, OHCI1394_BusOptions, buf);
475
476         /* Set Link Power Status (LPS) */
477         reg_write(ohci, OHCI1394_HCControlSet, 0x00080000);
478
479         /* After enabling LPS, we need to wait for the connection
480          * between phy and link to be established.  This should be
481          * signaled by the LPS bit becoming 1, but this happens
482          * immediately.  Instead we wait for reads from LinkControl to
483          * give a valid result, i.e. not 0xffffffff. */
484         while (reg_read(ohci, OHCI1394_LinkControlSet) == 0xffffffff) {
485                 DBGMSG(ohci->id, "waiting for phy-link connection");
486                 mdelay(2);
487         }
488
489         /* Set the bus number */
490         reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0);
491
492         /* Enable posted writes */
493         reg_write(ohci, OHCI1394_HCControlSet, 0x00040000);
494
495         /* Clear link control register */
496         reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
497   
498         /* Enable cycle timer and cycle master */
499         reg_write(ohci, OHCI1394_LinkControlSet, 0x00300000);
500
501         /* Clear interrupt registers */
502         reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
503         reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
504
505         /* Set up self-id dma buffer */
506         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->selfid_buf_bus);
507
508         /* enable self-id dma */
509         reg_write(ohci, OHCI1394_LinkControlSet, 0x00000200);
510
511         /* Set the Config ROM mapping register */
512         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->csr_config_rom_bus);
513
514         /* Initialize the Config ROM */
515         ohci_init_config_rom(ohci);
516
517         /* Now get our max packet size */
518         ohci->max_packet_size = 
519                 1<<(((reg_read(ohci, OHCI1394_BusOptions)>>12)&0xf)+1);
520
521         /* Don't accept phy packets into AR request context */ 
522         reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400);
523
524         /* Initialize IR dma */
525         ohci->nb_iso_rcv_ctx = 
526                 get_nb_iso_ctx(ohci, OHCI1394_IsoRecvIntMaskSet);
527         DBGMSG(ohci->id, "%d iso receive contexts available",
528                ohci->nb_iso_rcv_ctx);
529         for (i=0;i<ohci->nb_iso_rcv_ctx;i++) {
530                 reg_write(ohci, OHCI1394_IsoRcvContextControlClear+32*i,
531                           0xffffffff);
532                 reg_write(ohci, OHCI1394_IsoRcvContextMatch+32*i, 0);
533                 reg_write(ohci, OHCI1394_IsoRcvCommandPtr+32*i, 0);
534         }
535
536         /* Set bufferFill, isochHeader, multichannel for IR context */
537         reg_write(ohci, OHCI1394_IsoRcvContextControlSet, 0xd0000000);
538                         
539         /* Set the context match register to match on all tags */
540         reg_write(ohci, OHCI1394_IsoRcvContextMatch, 0xf0000000);
541
542         /* Clear the interrupt mask */
543         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
544         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
545
546         /* Initialize IT dma */
547         ohci->nb_iso_xmit_ctx = 
548                 get_nb_iso_ctx(ohci, OHCI1394_IsoXmitIntMaskSet);
549         DBGMSG(ohci->id, "%d iso transmit contexts available",
550                ohci->nb_iso_xmit_ctx);
551         for (i=0;i<ohci->nb_iso_xmit_ctx;i++) {
552                 reg_write(ohci, OHCI1394_IsoXmitContextControlClear+32*i,
553                           0xffffffff);
554                 reg_write(ohci, OHCI1394_IsoXmitCommandPtr+32*i, 0);
555         }
556         
557         /* Clear the interrupt mask */
558         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
559         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
560
561         /* Clear the multi channel mask high and low registers */
562         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, 0xffffffff);
563         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, 0xffffffff);
564
565         /* Initialize AR dma */
566         initialize_dma_rcv_ctx(ohci->ar_req_context);
567         initialize_dma_rcv_ctx(ohci->ar_resp_context);
568
569         /* Initialize AT dma */
570         initialize_dma_trm_ctx(ohci->at_req_context);
571         initialize_dma_trm_ctx(ohci->at_resp_context);
572
573         /* Initialize IR dma */
574         initialize_dma_rcv_ctx(ohci->ir_context);
575
576         /* Initialize IT dma */
577         initialize_dma_trm_ctx(ohci->it_context);
578
579         /* Set up isoRecvIntMask to generate interrupts for context 0
580            (thanks to Michael Greger for seeing that I forgot this) */
581         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 0x00000001);
582
583         /* Set up isoXmitIntMask to generate interrupts for context 0 */
584         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 0x00000001);
585
586         /* 
587          * Accept AT requests from all nodes. This probably 
588          * will have to be controlled from the subsystem
589          * on a per node basis.
590          */
591         reg_write(ohci,OHCI1394_AsReqFilterHiSet, 0x80000000);
592
593         /* Specify AT retries */
594         reg_write(ohci, OHCI1394_ATRetries, 
595                   OHCI1394_MAX_AT_REQ_RETRIES |
596                   (OHCI1394_MAX_AT_RESP_RETRIES<<4) |
597                   (OHCI1394_MAX_PHYS_RESP_RETRIES<<8));
598
599         /* We don't want hardware swapping */
600         reg_write(ohci, OHCI1394_HCControlClear, 0x40000000);
601
602         /* Enable interrupts */
603         reg_write(ohci, OHCI1394_IntMaskSet, 
604                   OHCI1394_masterIntEnable | 
605                   OHCI1394_phyRegRcvd | 
606                   OHCI1394_busReset | 
607                   OHCI1394_selfIDComplete |
608                   OHCI1394_RSPkt |
609                   OHCI1394_RQPkt |
610                   OHCI1394_respTxComplete |
611                   OHCI1394_reqTxComplete |
612                   OHCI1394_isochRx |
613                   OHCI1394_isochTx |
614                   OHCI1394_unrecoverableError
615                 );
616
617         /* Enable link */
618         reg_write(ohci, OHCI1394_HCControlSet, 0x00020000);
619
620         buf = reg_read(ohci, OHCI1394_Version);
621         PRINT(KERN_INFO, ohci->id, "OHCI-1394 %d.%d (PCI): IRQ=[%d]  MMIO=[%lx-%lx]"
622               "  Max Packet=[%d]", ((((buf) >> 16) & 0xf) + (((buf) >> 20) & 0xf) * 10),
623               ((((buf) >> 4) & 0xf) + ((buf) & 0xf) * 10), ohci->dev->irq,
624               pci_resource_start(ohci->dev, 0),
625               pci_resource_start(ohci->dev, 0) + pci_resource_len(ohci->dev, 0),
626               ohci->max_packet_size);
627
628         return 1;
629 }
630
631 static void ohci_remove(struct hpsb_host *host)
632 {
633         struct ti_ohci *ohci;
634
635         if (host != NULL) {
636                 ohci = host->hostdata;
637                 remove_card(ohci);
638         }
639 }
640
641 /* 
642  * Insert a packet in the AT DMA fifo and generate the DMA prg
643  * FIXME: rewrite the program in order to accept packets crossing
644  *        page boundaries.
645  *        check also that a single dma descriptor doesn't cross a 
646  *        page boundary.
647  */
648 static void insert_packet(struct ti_ohci *ohci,
649                           struct dma_trm_ctx *d, struct hpsb_packet *packet)
650 {
651         u32 cycleTimer;
652         int idx = d->prg_ind;
653
654         DBGMSG(ohci->id, "Inserting packet for node %d, tlabel=%d, tcode=0x%x, speed=%d",
655                         packet->node_id, packet->tlabel, packet->tcode, packet->speed_code);
656
657         d->prg_cpu[idx]->begin.address = 0;
658         d->prg_cpu[idx]->begin.branchAddress = 0;
659
660         if (d->ctx==1) {
661                 /* 
662                  * For response packets, we need to put a timeout value in
663                  * the 16 lower bits of the status... let's try 1 sec timeout 
664                  */ 
665                 cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
666                 d->prg_cpu[idx]->begin.status = cpu_to_le32(
667                         (((((cycleTimer>>25)&0x7)+1)&0x7)<<13) | 
668                         ((cycleTimer&0x01fff000)>>12));
669
670                 DBGMSG(ohci->id, "cycleTimer: %08x timeStamp: %08x",
671                        cycleTimer, d->prg_cpu[idx]->begin.status);
672         } else 
673                 d->prg_cpu[idx]->begin.status = 0;
674
675         if ( (packet->type == async) || (packet->type == raw) ) {
676
677                 if (packet->type == raw) {
678                         d->prg_cpu[idx]->data[0] = cpu_to_le32(OHCI1394_TCODE_PHY<<4);
679                         d->prg_cpu[idx]->data[1] = packet->header[0];
680                         d->prg_cpu[idx]->data[2] = packet->header[1];
681                 } else {
682                         d->prg_cpu[idx]->data[0] = packet->speed_code<<16 |
683                                 (packet->header[0] & 0xFFFF);
684                         d->prg_cpu[idx]->data[1] =
685                                 (packet->header[1] & 0xFFFF) | 
686                                 (packet->header[0] & 0xFFFF0000);
687                         d->prg_cpu[idx]->data[2] = packet->header[2];
688                         d->prg_cpu[idx]->data[3] = packet->header[3];
689                         packet_swab(d->prg_cpu[idx]->data, packet->tcode,
690                                         packet->header_size>>2, ohci->payload_swap);
691                 }
692
693                 if (packet->data_size) { /* block transmit */
694                         d->prg_cpu[idx]->begin.control =
695                                 cpu_to_le32(OUTPUT_MORE_IMMEDIATE | 0x10);
696                         d->prg_cpu[idx]->end.control =
697                                 cpu_to_le32(OUTPUT_LAST | packet->data_size);
698                         /* 
699                          * Check that the packet data buffer
700                          * does not cross a page boundary.
701                          */
702                         if (cross_bound((unsigned long)packet->data, 
703                                         packet->data_size)>0) {
704                                 /* FIXME: do something about it */
705                                 PRINT(KERN_ERR, ohci->id, __FUNCTION__
706                                       ": packet data addr: %p size %Zd bytes "
707                                       "cross page boundary", 
708                                       packet->data, packet->data_size);
709                         }
710
711                         d->prg_cpu[idx]->end.address = cpu_to_le32(
712                                 pci_map_single(ohci->dev, packet->data,
713                                                packet->data_size,
714                                                PCI_DMA_TODEVICE));
715                         OHCI_DMA_ALLOC("single, block transmit packet");
716
717                         if (ohci->payload_swap)
718                                 block_swab32(packet->data, packet->data_size >> 2);
719
720                         d->prg_cpu[idx]->end.branchAddress = 0;
721                         d->prg_cpu[idx]->end.status = 0;
722                         if (d->branchAddrPtr) 
723                                 *(d->branchAddrPtr) =
724                                         cpu_to_le32(d->prg_bus[idx] | 0x3);
725                         d->branchAddrPtr =
726                                 &(d->prg_cpu[idx]->end.branchAddress);
727                 } else { /* quadlet transmit */
728                         if (packet->type == raw)
729                                 d->prg_cpu[idx]->begin.control = cpu_to_le32(
730                                         OUTPUT_LAST_IMMEDIATE |
731                                         (packet->header_size+4));
732                         else
733                                 d->prg_cpu[idx]->begin.control = cpu_to_le32(
734                                         OUTPUT_LAST_IMMEDIATE |
735                                         packet->header_size);
736
737                         if (d->branchAddrPtr) 
738                                 *(d->branchAddrPtr) =
739                                         cpu_to_le32(d->prg_bus[idx] | 0x2);
740                         d->branchAddrPtr =
741                                 &(d->prg_cpu[idx]->begin.branchAddress);
742                 }
743
744         } else { /* iso packet */
745                 d->prg_cpu[idx]->data[0] = packet->speed_code<<16 |
746                         (packet->header[0] & 0xFFFF);
747                 d->prg_cpu[idx]->data[1] = packet->header[0] & 0xFFFF0000;
748                 packet_swab(d->prg_cpu[idx]->data, packet->tcode, packet->header_size>>2,
749                                 ohci->payload_swap);
750   
751                 d->prg_cpu[idx]->begin.control = cpu_to_le32(OUTPUT_MORE_IMMEDIATE | 0x8);
752                 d->prg_cpu[idx]->end.control = cpu_to_le32(
753                         OUTPUT_LAST | 0x08000000 | packet->data_size);
754                 d->prg_cpu[idx]->end.address = cpu_to_le32(
755                                 pci_map_single(ohci->dev, packet->data,
756                                 packet->data_size, PCI_DMA_TODEVICE));
757                 OHCI_DMA_ALLOC("single, iso transmit packet");
758
759                 if (ohci->payload_swap)
760                         block_swab32(packet->data, packet->data_size>>2);
761
762                 d->prg_cpu[idx]->end.branchAddress = 0;
763                 d->prg_cpu[idx]->end.status = 0;
764                 DBGMSG(ohci->id, "Iso xmit context info: header[%08x %08x]\n"
765                        "                       begin=%08x %08x %08x %08x\n"
766                        "                             %08x %08x %08x %08x\n"
767                        "                       end  =%08x %08x %08x %08x",
768                        d->prg_cpu[idx]->data[0], d->prg_cpu[idx]->data[1],
769                        d->prg_cpu[idx]->begin.control,
770                        d->prg_cpu[idx]->begin.address,
771                        d->prg_cpu[idx]->begin.branchAddress,
772                        d->prg_cpu[idx]->begin.status,
773                        d->prg_cpu[idx]->data[0],
774                        d->prg_cpu[idx]->data[1],
775                        d->prg_cpu[idx]->data[2],
776                        d->prg_cpu[idx]->data[3],
777                        d->prg_cpu[idx]->end.control,
778                        d->prg_cpu[idx]->end.address,
779                        d->prg_cpu[idx]->end.branchAddress,
780                        d->prg_cpu[idx]->end.status);
781                 if (d->branchAddrPtr) 
782                         *(d->branchAddrPtr) = cpu_to_le32(d->prg_bus[idx] | 0x3);
783                 d->branchAddrPtr = &(d->prg_cpu[idx]->end.branchAddress);
784         }
785         d->free_prgs--;
786
787         /* queue the packet in the appropriate context queue */
788         if (d->fifo_last) {
789                 d->fifo_last->xnext = packet;
790                 d->fifo_last = packet;
791         } else {
792                 d->fifo_first = packet;
793                 d->fifo_last = packet;
794         }
795         d->prg_ind = (d->prg_ind+1)%d->num_desc;
796 }
797
798 /*
799  * This function fills the AT FIFO with the (eventual) pending packets
800  * and runs or wakes up the AT DMA prg if necessary.
801  *
802  * The function MUST be called with the d->lock held.
803  */ 
804 static int dma_trm_flush(struct ti_ohci *ohci, struct dma_trm_ctx *d)
805 {
806         int idx,z;
807
808         if (d->pending_first == NULL || d->free_prgs == 0) 
809                 return 0;
810
811         idx = d->prg_ind;
812         z = (d->pending_first->data_size) ? 3 : 2;
813
814         /* insert the packets into the at dma fifo */
815         while (d->free_prgs>0 && d->pending_first) {
816                 insert_packet(ohci, d, d->pending_first);
817                 d->pending_first = d->pending_first->xnext;
818         }
819         if (d->pending_first == NULL) 
820                 d->pending_last = NULL;
821         else
822                 PRINT(KERN_INFO, ohci->id, 
823                       "Transmit DMA FIFO ctx=%d is full... waiting",d->ctx);
824
825         /* Is the context running ? (should be unless it is 
826            the first packet to be sent in this context) */
827         if (!(reg_read(ohci, d->ctrlSet) & 0x8000)) {
828                 DBGMSG(ohci->id,"Starting transmit DMA ctx=%d",d->ctx);
829                 reg_write(ohci, d->cmdPtr, d->prg_bus[idx]|z);
830                 run_context(ohci, d->ctrlSet, NULL);
831         }
832         else {
833                 /* Wake up the dma context if necessary */
834                 if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
835                         DBGMSG(ohci->id,"Waking transmit DMA ctx=%d",d->ctx);
836                         reg_write(ohci, d->ctrlSet, 0x1000);
837                 }
838         }
839         return 1;
840 }
841
842 /* Transmission of an async packet */
843 static int ohci_transmit(struct hpsb_host *host, struct hpsb_packet *packet)
844 {
845         struct ti_ohci *ohci = host->hostdata;
846         struct dma_trm_ctx *d;
847         unsigned char tcode;
848         unsigned long flags;
849
850         if (packet->data_size > ohci->max_packet_size) {
851                 PRINT(KERN_ERR, ohci->id, 
852                       "Transmit packet size %Zd is too big",
853                       packet->data_size);
854                 return 0;
855         }
856         packet->xnext = NULL;
857
858         /* Decide wether we have an iso, a request, or a response packet */
859         tcode = (packet->header[0]>>4)&0xf;
860         if (tcode == TCODE_ISO_DATA) d = ohci->it_context;
861         else if (tcode & 0x02) d = ohci->at_resp_context;
862         else d = ohci->at_req_context;
863
864         spin_lock_irqsave(&d->lock,flags);
865
866         /* queue the packet for later insertion into the dma fifo */
867         if (d->pending_last) {
868                 d->pending_last->xnext = packet;
869                 d->pending_last = packet;
870         }
871         else {
872                 d->pending_first = packet;
873                 d->pending_last = packet;
874         }
875         
876         dma_trm_flush(ohci, d);
877
878         spin_unlock_irqrestore(&d->lock,flags);
879
880         return 1;
881 }
882
883 static int ohci_devctl(struct hpsb_host *host, enum devctl_cmd cmd, int arg)
884 {
885         struct ti_ohci *ohci = host->hostdata;
886         int retval = 0;
887         unsigned long flags;
888
889         switch (cmd) {
890         case RESET_BUS:
891                 DBGMSG(ohci->id, "devctl: Bus reset requested%s",
892                        ((host->attempt_root || attempt_root) ? 
893                        " and attempting to become root" : ""));
894                 set_phy_reg_mask (ohci, 1, 0x40 | ((host->attempt_root || attempt_root) ?
895                                   0x80 : 0));
896                 break;
897
898         case GET_CYCLE_COUNTER:
899                 retval = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
900                 break;
901         
902         case SET_CYCLE_COUNTER:
903                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, arg);
904                 break;
905         
906         case SET_BUS_ID:
907                 PRINT(KERN_ERR, ohci->id, "devctl command SET_BUS_ID err");
908                 break;
909
910         case ACT_CYCLE_MASTER:
911                 if (arg) {
912                         /* check if we are root and other nodes are present */
913                         u32 nodeId = reg_read(ohci, OHCI1394_NodeID);
914                         if ((nodeId & (1<<30)) && (nodeId & 0x3f)) {
915                                 /*
916                                  * enable cycleTimer, cycleMaster
917                                  */
918                                 DBGMSG(ohci->id, "Cycle master enabled");
919                                 reg_write(ohci, OHCI1394_LinkControlSet, 
920                                           0x00300000);
921                         }
922                 } else {
923                         /* disable cycleTimer, cycleMaster, cycleSource */
924                         reg_write(ohci, OHCI1394_LinkControlClear, 0x00700000);
925                 }
926                 break;
927
928         case CANCEL_REQUESTS:
929                 DBGMSG(ohci->id, "Cancel request received");
930                 dma_trm_reset(ohci->at_req_context);
931                 dma_trm_reset(ohci->at_resp_context);
932                 break;
933
934         case MODIFY_USAGE:
935                 if (arg) {
936                         MOD_INC_USE_COUNT;
937                 } else {
938                         MOD_DEC_USE_COUNT;
939                 }
940                 break;
941
942         case ISO_LISTEN_CHANNEL:
943         {
944                 u64 mask;
945
946                 if (arg<0 || arg>63) {
947                         PRINT(KERN_ERR, ohci->id, __FUNCTION__
948                               "IS0 listne channel %d is out of range", 
949                               arg);
950                         return -EFAULT;
951                 }
952
953                 mask = (u64)0x1<<arg;
954                 
955                 spin_lock_irqsave(&ohci->IR_channel_lock, flags);
956
957                 if (ohci->ISO_channel_usage & mask) {
958                         PRINT(KERN_ERR, ohci->id, __FUNCTION__
959                               "IS0 listen channel %d is already used", 
960                               arg);
961                         spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
962                         return -EFAULT;
963                 }
964                 
965                 ohci->ISO_channel_usage |= mask;
966
967                 if (arg>31) 
968                         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, 
969                                   1<<(arg-32));                 
970                 else
971                         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, 
972                                   1<<arg);                      
973
974                 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
975                 DBGMSG(ohci->id, "Listening enabled on channel %d", arg);
976                 break;
977         }
978         case ISO_UNLISTEN_CHANNEL:
979         {
980                 u64 mask;
981
982                 if (arg<0 || arg>63) {
983                         PRINT(KERN_ERR, ohci->id, __FUNCTION__
984                               "IS0 unlisten channel %d is out of range", 
985                               arg);
986                         return -EFAULT;
987                 }
988
989                 mask = (u64)0x1<<arg;
990                 
991                 spin_lock_irqsave(&ohci->IR_channel_lock, flags);
992
993                 if (!(ohci->ISO_channel_usage & mask)) {
994                         PRINT(KERN_ERR, ohci->id, __FUNCTION__
995                               "IS0 unlisten channel %d is not used", 
996                               arg);
997                         spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
998                         return -EFAULT;
999                 }
1000                 
1001                 ohci->ISO_channel_usage &= ~mask;
1002
1003                 if (arg>31) 
1004                         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, 
1005                                   1<<(arg-32));                 
1006                 else
1007                         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, 
1008                                   1<<arg);                      
1009
1010                 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
1011                 DBGMSG(ohci->id, "Listening disabled on channel %d", arg);
1012                 break;
1013         }
1014         default:
1015                 PRINT_G(KERN_ERR, "ohci_devctl cmd %d not implemented yet",
1016                         cmd);
1017                 break;
1018         }
1019         return retval;
1020 }
1021
1022 /***************************************
1023  * IEEE-1394 functionality section END *
1024  ***************************************/
1025
1026
1027 /********************************************************
1028  * Global stuff (interrupt handler, init/shutdown code) *
1029  ********************************************************/
1030
1031 static void dma_trm_reset(struct dma_trm_ctx *d)
1032 {
1033         struct ti_ohci *ohci;
1034         unsigned long flags;
1035         struct hpsb_packet *nextpacket;
1036
1037         if (d==NULL) {
1038                 PRINT_G(KERN_ERR, "dma_trm_reset called with NULL arg");
1039                 return;
1040         }
1041         ohci = (struct ti_ohci *)(d->ohci);
1042         ohci1394_stop_context(ohci, d->ctrlClear, NULL);
1043
1044         spin_lock_irqsave(&d->lock,flags);
1045
1046         /* Is there still any packet pending in the fifo ? */
1047         while(d->fifo_first) {
1048                 PRINT(KERN_INFO, ohci->id, 
1049                       "AT dma reset ctx=%d, aborting transmission", 
1050                       d->ctx);
1051                 nextpacket = d->fifo_first->xnext;
1052                 hpsb_packet_sent(ohci->host, d->fifo_first, ACKX_ABORTED);
1053                 d->fifo_first = nextpacket;
1054         }
1055         d->fifo_first = d->fifo_last = NULL;
1056
1057         /* is there still any packet pending ? */
1058         while(d->pending_first) {
1059                 PRINT(KERN_INFO, ohci->id, 
1060                       "AT dma reset ctx=%d, aborting transmission", 
1061                       d->ctx);
1062                 nextpacket = d->pending_first->xnext;
1063                 hpsb_packet_sent(ohci->host, d->pending_first, 
1064                                  ACKX_ABORTED);
1065                 d->pending_first = nextpacket;
1066         }
1067         d->pending_first = d->pending_last = NULL;
1068         
1069         d->branchAddrPtr=NULL;
1070         d->sent_ind = d->prg_ind;
1071         d->free_prgs = d->num_desc;
1072         spin_unlock_irqrestore(&d->lock,flags);
1073 }
1074
1075 static void ohci_irq_handler(int irq, void *dev_id,
1076                              struct pt_regs *regs_are_unused)
1077 {
1078         quadlet_t event, node_id;
1079         struct ti_ohci *ohci = (struct ti_ohci *)dev_id;
1080         struct hpsb_host *host = ohci->host;
1081         int phyid = -1, isroot = 0, flags;
1082
1083         /* Read the interrupt event register. We don't clear the bus reset
1084          * here. We wait till we get a selfid complete interrupt and clear
1085          * it then, and _only_ then.  */
1086         spin_lock_irqsave(&ohci->event_lock, flags);
1087         event = reg_read(ohci, OHCI1394_IntEventClear);
1088         reg_write(ohci, OHCI1394_IntEventClear,
1089                   event & ~(OHCI1394_selfIDComplete | OHCI1394_busReset));
1090         spin_unlock_irqrestore(&ohci->event_lock, flags);
1091
1092         if (!event) return;
1093
1094         DBGMSG(ohci->id, "IntEvent: %08x", event);
1095
1096         /* Die right here an now */
1097         if (event & OHCI1394_unrecoverableError) {
1098                 PRINT(KERN_ERR, ohci->id, "Unrecoverable error, shutting down card!");
1099                 remove_card(ohci);
1100                 return;
1101         }
1102
1103         /* Someone wants a bus reset. Better watch what you wish for... */
1104         if (event & OHCI1394_busReset) {
1105                 if (!host->in_bus_reset) {
1106                         DBGMSG(ohci->id, "irq_handler: Bus reset requested%s",
1107                               ((host->attempt_root || attempt_root) ?
1108                               " and attempting to become root" : ""));
1109                         
1110                         /* Wait for the AT fifo to be flushed */
1111                         dma_trm_reset(ohci->at_req_context);
1112                         dma_trm_reset(ohci->at_resp_context);
1113
1114                         /* Subsystem call */
1115                         hpsb_bus_reset(ohci->host);
1116                         
1117                         ohci->NumBusResets++;
1118                 }
1119                 /* Mask out everything except selfid */
1120                 event &= OHCI1394_selfIDComplete;
1121         }
1122
1123         /* XXX: We need a way to also queue the OHCI1394_reqTxComplete,
1124          * but for right now we simply run it upon reception, to make sure
1125          * we get sent acks before response packets. This sucks mainly
1126          * because it halts the interrupt handler.  */
1127         if (event & OHCI1394_reqTxComplete) {
1128                 struct dma_trm_ctx *d = ohci->at_req_context;
1129                 DBGMSG(ohci->id, "Got reqTxComplete interrupt "
1130                        "status=0x%08X", reg_read(ohci, d->ctrlSet));
1131                 if (reg_read(ohci, d->ctrlSet) & 0x800)
1132                         ohci1394_stop_context(ohci, d->ctrlClear,
1133                                               "reqTxComplete");
1134                 else
1135                         dma_trm_tasklet ((unsigned long)d);
1136                 event &= ~OHCI1394_reqTxComplete;
1137         }
1138         if (event & OHCI1394_respTxComplete) {
1139                 struct dma_trm_ctx *d = ohci->at_resp_context;
1140                 DBGMSG(ohci->id, "Got respTxComplete interrupt "
1141                        "status=0x%08X", reg_read(ohci, d->ctrlSet));
1142                 if (reg_read(ohci, d->ctrlSet) & 0x800)
1143                         ohci1394_stop_context(ohci, d->ctrlClear,
1144                                               "respTxComplete");
1145                 else
1146                         tasklet_schedule(&d->task);
1147                 event &= ~OHCI1394_respTxComplete;
1148         }
1149         if (event & OHCI1394_RQPkt) {
1150                 struct dma_rcv_ctx *d = ohci->ar_req_context;
1151                 DBGMSG(ohci->id, "Got RQPkt interrupt status=0x%08X",
1152                        reg_read(ohci, d->ctrlSet));
1153                 if (reg_read(ohci, d->ctrlSet) & 0x800)
1154                         ohci1394_stop_context(ohci, d->ctrlClear, "RQPkt");
1155                 else
1156                         tasklet_schedule(&d->task);
1157                 event &= ~OHCI1394_RQPkt;
1158         }
1159         if (event & OHCI1394_RSPkt) {
1160                 struct dma_rcv_ctx *d = ohci->ar_resp_context;
1161                 DBGMSG(ohci->id, "Got RSPkt interrupt status=0x%08X",
1162                        reg_read(ohci, d->ctrlSet));
1163                 if (reg_read(ohci, d->ctrlSet) & 0x800)
1164                         ohci1394_stop_context(ohci, d->ctrlClear, "RSPkt");
1165                 else
1166                         tasklet_schedule(&d->task);
1167                 event &= ~OHCI1394_RSPkt;
1168         }
1169         if (event & OHCI1394_isochRx) {
1170                 quadlet_t isoRecvIntEvent;
1171                 struct dma_rcv_ctx *d = ohci->ir_context;
1172                 isoRecvIntEvent = 
1173                         reg_read(ohci, OHCI1394_IsoRecvIntEventSet);
1174                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear,
1175                           isoRecvIntEvent);
1176                 DBGMSG(ohci->id, "Got isochRx interrupt "
1177                        "status=0x%08X isoRecvIntEvent=%08x", 
1178                        reg_read(ohci, d->ctrlSet), isoRecvIntEvent);
1179                 if (isoRecvIntEvent & 0x1) {
1180                         if (reg_read(ohci, d->ctrlSet) & 0x800)
1181                                 ohci1394_stop_context(ohci, d->ctrlClear, 
1182                                              "isochRx");
1183                         else
1184                                 tasklet_schedule(&d->task);
1185                 }
1186                 if (ohci->video_tmpl) 
1187                         ohci->video_tmpl->irq_handler(ohci->id, isoRecvIntEvent,
1188                                                       0);
1189                 event &= ~OHCI1394_isochRx;
1190         }
1191         if (event & OHCI1394_isochTx) {
1192                 quadlet_t isoXmitIntEvent;
1193                 struct dma_trm_ctx *d = ohci->it_context;
1194                 isoXmitIntEvent = 
1195                         reg_read(ohci, OHCI1394_IsoXmitIntEventSet);
1196                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear,
1197                           isoXmitIntEvent);
1198                        DBGMSG(ohci->id, "Got isochTx interrupt "
1199                                "status=0x%08x isoXmitIntEvent=%08x",
1200                               reg_read(ohci, d->ctrlSet), isoXmitIntEvent);
1201                 if (ohci->video_tmpl) 
1202                         ohci->video_tmpl->irq_handler(ohci->id, 0,
1203                                                       isoXmitIntEvent);
1204                 if (isoXmitIntEvent & 0x1) {
1205                         if (reg_read(ohci, d->ctrlSet) & 0x800)
1206                                 ohci1394_stop_context(ohci, d->ctrlClear, "isochTx");
1207                         else
1208                                 tasklet_schedule(&d->task);
1209                 }
1210                 event &= ~OHCI1394_isochTx;
1211         }
1212         if (event & OHCI1394_selfIDComplete) {
1213                 if (host->in_bus_reset) {
1214                         node_id = reg_read(ohci, OHCI1394_NodeID); 
1215
1216                         /* If our nodeid is not valid, give a msec delay
1217                          * to let it settle in and try again.  */
1218                         if (!(node_id & 0x80000000)) {
1219                                 mdelay(1);
1220                                 node_id = reg_read(ohci, OHCI1394_NodeID);
1221                         }
1222
1223                         if (node_id & 0x80000000) { /* NodeID valid */
1224                                 phyid =  node_id & 0x0000003f;
1225                                 isroot = (node_id & 0x40000000) != 0;
1226
1227                                 DBGMSG(ohci->id,
1228                                       "SelfID interrupt received "
1229                                       "(phyid %d, %s)", phyid, 
1230                                       (isroot ? "root" : "not root"));
1231
1232                                 handle_selfid(ohci, host, 
1233                                               phyid, isroot);
1234                         } else 
1235                                 PRINT(KERN_ERR, ohci->id, 
1236                                       "SelfID interrupt received, but "
1237                                       "NodeID is not valid: %08X",
1238                                       node_id);
1239
1240                         /* Accept Physical requests from all nodes. */
1241                         reg_write(ohci,OHCI1394_AsReqFilterHiSet, 
1242                                   0xffffffff);
1243                         reg_write(ohci,OHCI1394_AsReqFilterLoSet, 
1244                                   0xffffffff);
1245                         /* Turn on phys dma reception. We should
1246                          * probably manage the filtering somehow, 
1247                          * instead of blindly turning it on.  */
1248                         reg_write(ohci,OHCI1394_PhyReqFilterHiSet,
1249                                   0xffffffff);
1250                         reg_write(ohci,OHCI1394_PhyReqFilterLoSet,
1251                                   0xffffffff);
1252                         reg_write(ohci,OHCI1394_PhyUpperBound,
1253                                   0xffff0000);
1254                 } else
1255                         PRINT(KERN_ERR, ohci->id, 
1256                               "SelfID received outside of bus reset sequence");
1257
1258                 /* Clear everything, it's a new day */
1259                 spin_lock_irqsave(&ohci->event_lock, flags);
1260                 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
1261                 spin_unlock_irqrestore(&ohci->event_lock, flags);
1262
1263                 event &= ~OHCI1394_selfIDComplete;
1264         }
1265         if (event & OHCI1394_phyRegRcvd) {
1266                 if (host->in_bus_reset) {
1267                         DBGMSG (ohci->id, "PhyControl: %08X", 
1268                                 reg_read(ohci, OHCI1394_PhyControl));
1269                 } else
1270                         PRINT(KERN_ERR, ohci->id, 
1271                               "Physical register received outside of bus reset sequence");
1272                 event &= ~OHCI1394_phyRegRcvd;
1273         }
1274
1275         /* Make sure we handle everything, just in case we accidentally
1276          * enabled an interrupt that we didn't write a handler for.  */
1277         if (event)
1278                 PRINT(KERN_ERR, ohci->id, "Unhandled interrupt(s) 0x%08x",
1279                       event);
1280 }
1281
1282 /* Put the buffer back into the dma context */
1283 static void insert_dma_buffer(struct dma_rcv_ctx *d, int idx)
1284 {
1285         struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
1286         DBGMSG(ohci->id, "Inserting dma buf ctx=%d idx=%d", d->ctx, idx);
1287
1288         d->prg_cpu[idx]->status = cpu_to_le32(d->buf_size);
1289         d->prg_cpu[idx]->branchAddress &= le32_to_cpu(0xfffffff0);
1290         idx = (idx + d->num_desc - 1 ) % d->num_desc;
1291         d->prg_cpu[idx]->branchAddress |= le32_to_cpu(0x00000001);
1292
1293         /* wake up the dma context if necessary */
1294         if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
1295                 PRINT(KERN_INFO, ohci->id, 
1296                       "Waking dma ctx=%d ... processing is probably too slow",
1297                       d->ctx);
1298                 reg_write(ohci, d->ctrlSet, 0x1000);
1299         }
1300 }
1301
1302 #define cond_le32_to_cpu(data, noswap) \
1303         (noswap ? data : le32_to_cpu(data))
1304
1305 static const int TCODE_SIZE[16] = {20, 0, 16, -1, 16, 20, 20, 0, 
1306                             -1, 0, -1, 0, -1, -1, 16, -1};
1307
1308 /* 
1309  * Determine the length of a packet in the buffer
1310  * Optimization suggested by Pascal Drolet <pascal.drolet@informission.ca>
1311  */
1312 static __inline__ int packet_length(struct dma_rcv_ctx *d, int idx, quadlet_t *buf_ptr,
1313                          int offset, unsigned char tcode, int noswap)
1314 {
1315         int length = -1;
1316
1317         if (d->ctx < 2) { /* Async Receive Response/Request */
1318                 length = TCODE_SIZE[tcode];
1319                 if (length == 0) {
1320                         if (offset + 12 >= d->buf_size) {
1321                                 length = (cond_le32_to_cpu(d->buf_cpu[(idx + 1) % d->num_desc]
1322                                                 [3 - ((d->buf_size - offset) >> 2)], noswap) >> 16);
1323                         } else {
1324                                 length = (cond_le32_to_cpu(buf_ptr[3], noswap) >> 16);
1325                         }
1326                         length += 20;
1327                 }
1328         } else if (d->ctx == 2) { /* Iso receive */
1329                 /* Assumption: buffer fill mode with header/trailer */
1330                 length = (cond_le32_to_cpu(buf_ptr[0], noswap) >> 16) + 8;
1331         }
1332
1333         if (length > 0 && length % 4)
1334                 length += 4 - (length % 4);
1335
1336         return length;
1337 }
1338
1339 /* Tasklet that processes dma receive buffers */
1340 static void dma_rcv_tasklet (unsigned long data)
1341 {
1342         struct dma_rcv_ctx *d = (struct dma_rcv_ctx*)data;
1343         struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
1344         unsigned int split_left, idx, offset, rescount;
1345         unsigned char tcode;
1346         int length, bytes_left, ack, flags;
1347         quadlet_t *buf_ptr;
1348         char *split_ptr;
1349         char msg[256];
1350
1351         spin_lock_irqsave(&d->lock, flags);
1352
1353         idx = d->buf_ind;
1354         offset = d->buf_offset;
1355         buf_ptr = d->buf_cpu[idx] + offset/4;
1356
1357         dma_cache_wback_inv(&(d->prg_cpu[idx]->status), sizeof(d->prg_cpu[idx]->status));
1358         rescount = le32_to_cpu(d->prg_cpu[idx]->status) & 0xffff;
1359
1360         bytes_left = d->buf_size - rescount - offset;
1361         dma_cache_wback_inv(buf_ptr, bytes_left);
1362
1363         while (bytes_left > 0) {
1364                 tcode = (cond_le32_to_cpu(buf_ptr[0], ohci->payload_swap) >> 4) & 0xf;
1365
1366                 /* packet_length() will return < 4 for an error */
1367                 length = packet_length(d, idx, buf_ptr, offset, tcode, ohci->payload_swap);
1368
1369                 if (length < 4) { /* something is wrong */
1370                         sprintf(msg,"Unexpected tcode 0x%x(0x%08x) in AR ctx=%d, length=%d",
1371                                 tcode, cond_le32_to_cpu(buf_ptr[0], ohci->payload_swap),
1372                                 d->ctx, length);
1373                         ohci1394_stop_context(ohci, d->ctrlClear, msg);
1374                         spin_unlock_irqrestore(&d->lock, flags);
1375                         return;
1376                 }
1377
1378                 /* The first case is where we have a packet that crosses
1379                  * over more than one descriptor. The next case is where
1380                  * it's all in the first descriptor.  */
1381                 if ((offset + length) > d->buf_size) {
1382                         DBGMSG(ohci->id,"Split packet rcv'd");
1383                         if (length > d->split_buf_size) {
1384                                 ohci1394_stop_context(ohci, d->ctrlClear,
1385                                              "Split packet size exceeded");
1386                                 d->buf_ind = idx;
1387                                 d->buf_offset = offset;
1388                                 spin_unlock_irqrestore(&d->lock, flags);
1389                                 return;
1390                         }
1391
1392                         if (le32_to_cpu(d->prg_cpu[(idx+1)%d->num_desc]->status)
1393                             == d->buf_size) {
1394                                 /* Other part of packet not written yet.
1395                                  * this should never happen I think
1396                                  * anyway we'll get it on the next call.  */
1397                                 PRINT(KERN_INFO, ohci->id,
1398                                       "Got only half a packet!");
1399                                 d->buf_ind = idx;
1400                                 d->buf_offset = offset;
1401                                 spin_unlock_irqrestore(&d->lock, flags);
1402                                 return;
1403                         }
1404
1405                         split_left = length;
1406                         split_ptr = (char *)d->spb;
1407                         memcpy(split_ptr,buf_ptr,d->buf_size-offset);
1408                         split_left -= d->buf_size-offset;
1409                         split_ptr += d->buf_size-offset;
1410                         insert_dma_buffer(d, idx);
1411                         idx = (idx+1) % d->num_desc;
1412                         buf_ptr = d->buf_cpu[idx];
1413                         dma_cache_wback_inv(buf_ptr, d->buf_size);
1414                         offset=0;
1415
1416                         while (split_left >= d->buf_size) {
1417                                 memcpy(split_ptr,buf_ptr,d->buf_size);
1418                                 split_ptr += d->buf_size;
1419                                 split_left -= d->buf_size;
1420                                 insert_dma_buffer(d, idx);
1421                                 idx = (idx+1) % d->num_desc;
1422                                 buf_ptr = d->buf_cpu[idx];
1423                                 dma_cache_wback_inv(buf_ptr, d->buf_size);
1424                         }
1425
1426                         if (split_left > 0) {
1427                                 memcpy(split_ptr, buf_ptr, split_left);
1428                                 offset = split_left;
1429                                 buf_ptr += offset/4;
1430                         }
1431                 } else {
1432                         DBGMSG(ohci->id,"Single packet rcv'd");
1433                         memcpy(d->spb, buf_ptr, length);
1434                         offset += length;
1435                         buf_ptr += length/4;
1436                         if (offset==d->buf_size) {
1437                                 insert_dma_buffer(d, idx);
1438                                 idx = (idx+1) % d->num_desc;
1439                                 buf_ptr = d->buf_cpu[idx];
1440                                 offset=0;
1441                         }
1442                 }
1443                 
1444                 /* We get one phy packet to the async descriptor for each
1445                  * bus reset. We always ignore it.  */
1446                 if (tcode != OHCI1394_TCODE_PHY) {
1447                         if (!ohci->payload_swap)
1448                                 packet_swab(d->spb, tcode, (length - 4) >> 2, 0);
1449
1450                         DBGMSG(ohci->id, "Packet received from node"
1451                                 " %d ack=0x%02X spd=%d tcode=0x%X"
1452                                 " length=%d ctx=%d tlabel=%d",
1453                                 (d->spb[1]>>16)&0x3f,
1454                                 (cond_le32_to_cpu(d->spb[length/4-1], ohci->payload_swap)>>16)&0x1f,
1455                                 (cond_le32_to_cpu(d->spb[length/4-1], ohci->payload_swap)>>21)&0x3,
1456                                 tcode, length, d->ctx,
1457                                 (cond_le32_to_cpu(d->spb[length/4-1], ohci->payload_swap)>>10)&0x3f);
1458
1459                         ack = (((cond_le32_to_cpu(d->spb[length/4-1], ohci->payload_swap)>>16)&0x1f)
1460                                 == 0x11) ? 1 : 0;
1461
1462                         hpsb_packet_received(ohci->host, d->spb, 
1463                                              length-4, ack);
1464                 }
1465 #ifdef OHCI1394_DEBUG
1466                 else
1467                         PRINT (KERN_DEBUG, ohci->id, "Got phy packet ctx=%d ... discarded",
1468                                d->ctx);
1469 #endif
1470
1471                 dma_cache_wback_inv(&(d->prg_cpu[idx]->status),
1472                         sizeof(d->prg_cpu[idx]->status));
1473                 rescount = le32_to_cpu(d->prg_cpu[idx]->status) & 0xffff;
1474
1475                 bytes_left = d->buf_size - rescount - offset;
1476
1477         }
1478
1479         d->buf_ind = idx;
1480         d->buf_offset = offset;
1481
1482         spin_unlock_irqrestore(&d->lock, flags);
1483 }
1484
1485 /* Bottom half that processes sent packets */
1486 static void dma_trm_tasklet (unsigned long data)
1487 {
1488         struct dma_trm_ctx *d = (struct dma_trm_ctx*)data;
1489         struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
1490         struct hpsb_packet *packet, *nextpacket;
1491         unsigned long flags;
1492         u32 ack;
1493         size_t datasize;
1494
1495         spin_lock_irqsave(&d->lock, flags);
1496
1497         if (d->fifo_first == NULL) {
1498 #if 0
1499                 ohci1394_stop_context(ohci, d->ctrlClear, 
1500                              "Packet sent ack received but queue is empty");
1501 #endif
1502                 spin_unlock_irqrestore(&d->lock, flags);
1503                 return;
1504         }
1505
1506         while (d->fifo_first) {
1507                 packet = d->fifo_first;
1508                 datasize = d->fifo_first->data_size;
1509                 if (datasize && packet->type != raw)
1510                         ack = le32_to_cpu(
1511                                 d->prg_cpu[d->sent_ind]->end.status) >> 16;
1512                 else 
1513                         ack = le32_to_cpu(
1514                                 d->prg_cpu[d->sent_ind]->begin.status) >> 16;
1515
1516                 if (ack == 0) 
1517                         /* this packet hasn't been sent yet*/
1518                         break;
1519
1520 #ifdef OHCI1394_DEBUG
1521                 if (datasize)
1522                         DBGMSG(ohci->id,
1523                                "Packet sent to node %d tcode=0x%X tLabel="
1524                                "0x%02X ack=0x%X spd=%d dataLength=%d ctx=%d", 
1525                                 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])
1526                                         >>16)&0x3f,
1527                                 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])
1528                                         >>4)&0xf,
1529                                 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])
1530                                         >>10)&0x3f,
1531                                 ack&0x1f, (ack>>5)&0x3, 
1532                                 le32_to_cpu(d->prg_cpu[d->sent_ind]->data[3])
1533                                         >>16,
1534                                 d->ctx);
1535                 else 
1536                         DBGMSG(ohci->id,
1537                                "Packet sent to node %d tcode=0x%X tLabel="
1538                                "0x%02X ack=0x%X spd=%d data=0x%08X ctx=%d", 
1539                                 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[1])
1540                                         >>16)&0x3f,
1541                                 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])
1542                                         >>4)&0xf,
1543                                 (le32_to_cpu(d->prg_cpu[d->sent_ind]->data[0])
1544                                         >>10)&0x3f,
1545                                 ack&0x1f, (ack>>5)&0x3, 
1546                                 le32_to_cpu(d->prg_cpu[d->sent_ind]->data[3]),
1547                                 d->ctx);
1548 #endif          
1549
1550                 nextpacket = packet->xnext;
1551                 hpsb_packet_sent(ohci->host, packet, ack & 0xf);
1552
1553                 if (datasize) {
1554                         pci_unmap_single(ohci->dev, 
1555                                          cpu_to_le32(d->prg_cpu[d->sent_ind]->end.address),
1556                                          datasize, PCI_DMA_TODEVICE);
1557                         OHCI_DMA_FREE("single Xmit data packet");
1558                 }
1559
1560                 d->sent_ind = (d->sent_ind+1)%d->num_desc;
1561                 d->free_prgs++;
1562                 d->fifo_first = nextpacket;
1563         }
1564         if (d->fifo_first == NULL)
1565                 d->fifo_last = NULL;
1566
1567         dma_trm_flush(ohci, d);
1568
1569         spin_unlock_irqrestore(&d->lock, flags);
1570 }
1571
1572 static int free_dma_rcv_ctx(struct dma_rcv_ctx **d)
1573 {
1574         int i;
1575         struct ti_ohci *ohci;
1576
1577         if (*d==NULL) return -1;
1578
1579         ohci = (struct ti_ohci *)(*d)->ohci;
1580
1581         DBGMSG(ohci->id, "Freeing dma_rcv_ctx %d",(*d)->ctx);
1582         
1583         ohci1394_stop_context(ohci, (*d)->ctrlClear, NULL);
1584
1585         tasklet_kill(&(*d)->task);
1586
1587         if ((*d)->buf_cpu) {
1588                 for (i=0; i<(*d)->num_desc; i++)
1589                         if ((*d)->buf_cpu[i] && (*d)->buf_bus[i]) {
1590                                 pci_free_consistent(
1591                                         ohci->dev, (*d)->buf_size, 
1592                                         (*d)->buf_cpu[i], (*d)->buf_bus[i]);
1593                                 OHCI_DMA_FREE("consistent dma_rcv buf[%d]", i);
1594                         }
1595                 kfree((*d)->buf_cpu);
1596                 kfree((*d)->buf_bus);
1597         }
1598         if ((*d)->prg_cpu) {
1599                 for (i=0; i<(*d)->num_desc; i++) 
1600                         if ((*d)->prg_cpu[i] && (*d)->prg_bus[i]) {
1601                                 pci_free_consistent(
1602                                         ohci->dev, sizeof(struct dma_cmd), 
1603                                         (*d)->prg_cpu[i], (*d)->prg_bus[i]);
1604                                 OHCI_DMA_FREE("consistent dma_rcv prg[%d]", i);
1605                         }
1606                 kfree((*d)->prg_cpu);
1607                 kfree((*d)->prg_bus);
1608         }
1609         if ((*d)->spb) kfree((*d)->spb);
1610
1611         kfree(*d);
1612         *d = NULL;
1613
1614         return 0;
1615 }
1616
1617 static struct dma_rcv_ctx *
1618 alloc_dma_rcv_ctx(struct ti_ohci *ohci, int ctx, int num_desc,
1619                   int buf_size, int split_buf_size, 
1620                   int ctrlSet, int ctrlClear, int cmdPtr)
1621 {
1622         struct dma_rcv_ctx *d=NULL;
1623         int i;
1624
1625         d = (struct dma_rcv_ctx *)kmalloc(sizeof(struct dma_rcv_ctx), 
1626                                           GFP_KERNEL);
1627
1628         if (d == NULL) {
1629                 PRINT(KERN_ERR, ohci->id, "Failed to allocate dma_rcv_ctx");
1630                 return NULL;
1631         }
1632
1633         memset (d, 0, sizeof (struct dma_rcv_ctx));
1634
1635         d->ohci = (void *)ohci;
1636         d->ctx = ctx;
1637
1638         d->num_desc = num_desc;
1639         d->buf_size = buf_size;
1640         d->split_buf_size = split_buf_size;
1641         d->ctrlSet = ctrlSet;
1642         d->ctrlClear = ctrlClear;
1643         d->cmdPtr = cmdPtr;
1644
1645         d->buf_cpu = NULL;
1646         d->buf_bus = NULL;
1647         d->prg_cpu = NULL;
1648         d->prg_bus = NULL;
1649         d->spb = NULL;
1650
1651         d->buf_cpu = kmalloc(d->num_desc * sizeof(quadlet_t*), GFP_KERNEL);
1652         d->buf_bus = kmalloc(d->num_desc * sizeof(dma_addr_t), GFP_KERNEL);
1653
1654         if (d->buf_cpu == NULL || d->buf_bus == NULL) {
1655                 PRINT(KERN_ERR, ohci->id, "Failed to allocate dma buffer");
1656                 free_dma_rcv_ctx(&d);
1657                 return NULL;
1658         }
1659         memset(d->buf_cpu, 0, d->num_desc * sizeof(quadlet_t*));
1660         memset(d->buf_bus, 0, d->num_desc * sizeof(dma_addr_t));
1661
1662         d->prg_cpu = kmalloc(d->num_desc * sizeof(struct dma_cmd*), 
1663                              GFP_KERNEL);
1664         d->prg_bus = kmalloc(d->num_desc * sizeof(dma_addr_t), GFP_KERNEL);
1665
1666         if (d->prg_cpu == NULL || d->prg_bus == NULL) {
1667                 PRINT(KERN_ERR, ohci->id, "Failed to allocate dma prg");
1668                 free_dma_rcv_ctx(&d);
1669                 return NULL;
1670         }
1671         memset(d->prg_cpu, 0, d->num_desc * sizeof(struct dma_cmd*));
1672         memset(d->prg_bus, 0, d->num_desc * sizeof(dma_addr_t));
1673
1674         d->spb = kmalloc(d->split_buf_size, GFP_KERNEL);
1675
1676         if (d->spb == NULL) {
1677                 PRINT(KERN_ERR, ohci->id, "Failed to allocate split buffer");
1678                 free_dma_rcv_ctx(&d);
1679                 return NULL;
1680         }
1681
1682         for (i=0; i<d->num_desc; i++) {
1683                 d->buf_cpu[i] = pci_alloc_consistent(ohci->dev, 
1684                                                      d->buf_size,
1685                                                      d->buf_bus+i);
1686                 OHCI_DMA_ALLOC("consistent dma_rcv buf[%d]", i);
1687                 
1688                 if (d->buf_cpu[i] != NULL) {
1689                         memset(d->buf_cpu[i], 0, d->buf_size);
1690                 } else {
1691                         PRINT(KERN_ERR, ohci->id, 
1692                               "Failed to allocate dma buffer");
1693                         free_dma_rcv_ctx(&d);
1694                         return NULL;
1695                 }
1696
1697                 
1698                 d->prg_cpu[i] = pci_alloc_consistent(ohci->dev, 
1699                                                      sizeof(struct dma_cmd),
1700                                                      d->prg_bus+i);
1701                 OHCI_DMA_ALLOC("consistent dma_rcv prg[%d]", i);
1702
1703                 if (d->prg_cpu[i] != NULL) {
1704                         memset(d->prg_cpu[i], 0, sizeof(struct dma_cmd));
1705                 } else {
1706                         PRINT(KERN_ERR, ohci->id, 
1707                               "Failed to allocate dma prg");
1708                         free_dma_rcv_ctx(&d);
1709                         return NULL;
1710                 }
1711         }
1712
1713         spin_lock_init(&d->lock);
1714
1715         /* initialize tasklet */
1716         tasklet_init (&d->task, dma_rcv_tasklet, (unsigned long)d);
1717
1718         return d;
1719 }
1720
1721 static int free_dma_trm_ctx(struct dma_trm_ctx **d)
1722 {
1723         struct ti_ohci *ohci;
1724         int i;
1725
1726         if (*d==NULL) return -1;
1727
1728         ohci = (struct ti_ohci *)(*d)->ohci;
1729
1730         DBGMSG(ohci->id, "Freeing dma_trm_ctx %d",(*d)->ctx);
1731
1732         ohci1394_stop_context(ohci, (*d)->ctrlClear, NULL);
1733
1734         tasklet_kill(&(*d)->task);
1735
1736         if ((*d)->prg_cpu) {
1737                 for (i=0; i<(*d)->num_desc; i++) 
1738                         if ((*d)->prg_cpu[i] && (*d)->prg_bus[i]) {
1739                                 pci_free_consistent(
1740                                         ohci->dev, sizeof(struct at_dma_prg), 
1741                                         (*d)->prg_cpu[i], (*d)->prg_bus[i]);
1742                                 OHCI_DMA_FREE("consistent dma_trm prg[%d]", i);
1743                         }
1744                 kfree((*d)->prg_cpu);
1745                 kfree((*d)->prg_bus);
1746         }
1747
1748         kfree(*d);
1749         *d = NULL;
1750         return 0;
1751 }
1752
1753 static struct dma_trm_ctx *
1754 alloc_dma_trm_ctx(struct ti_ohci *ohci, int ctx, int num_desc,
1755                   int ctrlSet, int ctrlClear, int cmdPtr)
1756 {
1757         struct dma_trm_ctx *d=NULL;
1758         int i;
1759
1760         d = (struct dma_trm_ctx *)kmalloc(sizeof(struct dma_trm_ctx), 
1761                                           GFP_KERNEL);
1762
1763         if (d==NULL) {
1764                 PRINT(KERN_ERR, ohci->id, "Failed to allocate dma_trm_ctx");
1765                 return NULL;
1766         }
1767
1768         memset (d, 0, sizeof (struct dma_trm_ctx));
1769
1770         d->ohci = (void *)ohci;
1771         d->ctx = ctx;
1772         d->num_desc = num_desc;
1773         d->ctrlSet = ctrlSet;
1774         d->ctrlClear = ctrlClear;
1775         d->cmdPtr = cmdPtr;
1776         d->prg_cpu = NULL;
1777         d->prg_bus = NULL;
1778
1779         d->prg_cpu = kmalloc(d->num_desc * sizeof(struct at_dma_prg*), 
1780                              GFP_KERNEL);
1781         d->prg_bus = kmalloc(d->num_desc * sizeof(dma_addr_t), GFP_KERNEL);
1782
1783         if (d->prg_cpu == NULL || d->prg_bus == NULL) {
1784                 PRINT(KERN_ERR, ohci->id, "Failed to allocate at dma prg");
1785                 free_dma_trm_ctx(&d);
1786                 return NULL;
1787         }
1788         memset(d->prg_cpu, 0, d->num_desc * sizeof(struct at_dma_prg*));
1789         memset(d->prg_bus, 0, d->num_desc * sizeof(dma_addr_t));
1790
1791         for (i=0; i<d->num_desc; i++) {
1792                 d->prg_cpu[i] = pci_alloc_consistent(ohci->dev, 
1793                                                      sizeof(struct at_dma_prg),
1794                                                      d->prg_bus+i);
1795                 OHCI_DMA_ALLOC("consistent dma_trm prg[%d]", i);
1796
1797                 if (d->prg_cpu[i] != NULL) {
1798                         memset(d->prg_cpu[i], 0, sizeof(struct at_dma_prg));
1799                 } else {
1800                         PRINT(KERN_ERR, ohci->id, 
1801                               "Failed to allocate at dma prg");
1802                         free_dma_trm_ctx(&d);
1803                         return NULL;
1804                 }
1805         }
1806
1807         spin_lock_init(&d->lock);
1808
1809         /* initialize bottom handler */
1810         tasklet_init (&d->task, dma_trm_tasklet, (unsigned long)d);
1811
1812         return d;
1813 }
1814
1815 static u16 ohci_crc16 (u32 *ptr, int length)
1816 {
1817         int shift;
1818         u32 crc, sum, data;
1819
1820         crc = 0;
1821         for (; length > 0; length--) {
1822                 data = *ptr++;
1823                 for (shift = 28; shift >= 0; shift -= 4) {
1824                         sum = ((crc >> 12) ^ (data >> shift)) & 0x000f;
1825                         crc = (crc << 4) ^ (sum << 12) ^ (sum << 5) ^ sum;
1826                 }
1827                 crc &= 0xffff;
1828         }
1829         return crc;
1830 }
1831
1832 /* Config ROM macro implementation influenced by NetBSD OHCI driver */
1833
1834 struct config_rom_unit {
1835         u32 *start;
1836         u32 *refer;
1837         int length;
1838         int refunit;
1839 };
1840
1841 struct config_rom_ptr {
1842         u32 *data;
1843         int unitnum;
1844         struct config_rom_unit unitdir[10];
1845 };
1846
1847 #define cf_put_1quad(cr, q) (((cr)->data++)[0] = cpu_to_be32(q))
1848
1849 #define cf_put_4bytes(cr, b1, b2, b3, b4) \
1850         (((cr)->data++)[0] = cpu_to_be32(((b1) << 24) | ((b2) << 16) | ((b3) << 8) | (b4)))
1851
1852 #define cf_put_keyval(cr, key, val) (((cr)->data++)[0] = cpu_to_be32(((key) << 24) | (val)))
1853
1854 static inline void cf_put_crc16(struct config_rom_ptr *cr, int unit)
1855 {
1856         *cr->unitdir[unit].start =
1857                 cpu_to_be32((cr->unitdir[unit].length << 16) |
1858                             ohci_crc16(cr->unitdir[unit].start + 1,
1859                                        cr->unitdir[unit].length));
1860 }
1861
1862 static inline void cf_unit_begin(struct config_rom_ptr *cr, int unit)
1863 {
1864         if (cr->unitdir[unit].refer != NULL) {
1865                 *cr->unitdir[unit].refer |=
1866                         cpu_to_be32 (cr->data - cr->unitdir[unit].refer);
1867                 cf_put_crc16(cr, cr->unitdir[unit].refunit);
1868         }
1869         cr->unitnum = unit;
1870         cr->unitdir[unit].start = cr->data++;
1871 }
1872
1873 static inline void cf_put_refer(struct config_rom_ptr *cr, char key, int unit)
1874 {
1875         cr->unitdir[unit].refer = cr->data;
1876         cr->unitdir[unit].refunit = cr->unitnum;
1877         (cr->data++)[0] = cpu_to_be32(key << 24);
1878 }
1879
1880 static inline void cf_unit_end(struct config_rom_ptr *cr)
1881 {
1882         cr->unitdir[cr->unitnum].length = cr->data -
1883                 (cr->unitdir[cr->unitnum].start + 1);
1884         cf_put_crc16(cr, cr->unitnum);
1885 }
1886
1887 /* End of NetBSD derived code.  */
1888
1889 static void ohci_init_config_rom(struct ti_ohci *ohci)
1890 {
1891         struct config_rom_ptr cr;
1892
1893         memset(&cr, 0, sizeof(cr));
1894         memset(ohci->csr_config_rom_cpu, 0, sizeof (ohci->csr_config_rom_cpu));
1895
1896         cr.data = ohci->csr_config_rom_cpu;
1897
1898         /* Bus info block */
1899         cf_unit_begin(&cr, 0);
1900         cf_put_1quad(&cr, reg_read(ohci, OHCI1394_BusID));
1901         cf_put_1quad(&cr, reg_read(ohci, OHCI1394_BusOptions));
1902         cf_put_1quad(&cr, reg_read(ohci, OHCI1394_GUIDHi));
1903         cf_put_1quad(&cr, reg_read(ohci, OHCI1394_GUIDLo));
1904         cf_unit_end(&cr);
1905
1906         DBGMSG(ohci->id, "GUID: %08x:%08x", reg_read(ohci, OHCI1394_GUIDHi),
1907                 reg_read(ohci, OHCI1394_GUIDLo));
1908
1909         /* IEEE P1212 suggests the initial ROM header CRC should only
1910          * cover the header itself (and not the entire ROM). Since we do
1911          * this, then we can make our bus_info_len the same as the CRC
1912          * length.  */
1913         ohci->csr_config_rom_cpu[0] |= cpu_to_be32(
1914                 (be32_to_cpu(ohci->csr_config_rom_cpu[0]) & 0x00ff0000) << 8);
1915         reg_write(ohci, OHCI1394_ConfigROMhdr,
1916                   be32_to_cpu(ohci->csr_config_rom_cpu[0]));
1917
1918         /* Root directory */
1919         cf_unit_begin(&cr, 1);
1920         cf_put_keyval(&cr, 0x03, 0x00005e);     /* Vendor ID */
1921         cf_put_refer(&cr, 0x81, 2);             /* Textual description unit */
1922         cf_put_keyval(&cr, 0x0c, 0x0083c0);     /* Node capabilities */
1923         cf_put_refer(&cr, 0xd1, 3);             /* IPv4 unit directory */
1924         cf_put_refer(&cr, 0xd1, 4);             /* IPv6 unit directory */
1925         /* NOTE: Add other unit referers here, and append at bottom */
1926         cf_unit_end(&cr);
1927
1928         /* Textual description - "Linux 1394" */
1929         cf_unit_begin(&cr, 2);
1930         cf_put_keyval(&cr, 0, 0);
1931         cf_put_1quad(&cr, 0);
1932         cf_put_4bytes(&cr, 'L', 'i', 'n', 'u');
1933         cf_put_4bytes(&cr, 'x', ' ', '1', '3');
1934         cf_put_4bytes(&cr, '9', '4', 0x0, 0x0);
1935         cf_unit_end(&cr);
1936
1937         /* IPv4 unit directory, RFC 2734 */
1938         cf_unit_begin(&cr, 3);
1939         cf_put_keyval(&cr, 0x12, 0x00005e);     /* Unit spec ID */
1940         cf_put_refer(&cr, 0x81, 6);             /* Textual description unit */
1941         cf_put_keyval(&cr, 0x13, 0x000001);     /* Unit software version */
1942         cf_put_refer(&cr, 0x81, 7);             /* Textual description unit */
1943         cf_unit_end(&cr);
1944
1945         cf_unit_begin(&cr, 6);
1946         cf_put_keyval(&cr, 0, 0);
1947         cf_put_1quad(&cr, 0);
1948         cf_put_4bytes(&cr, 'I', 'A', 'N', 'A');
1949         cf_unit_end(&cr);
1950
1951         cf_unit_begin(&cr, 7);
1952         cf_put_keyval(&cr, 0, 0);
1953         cf_put_1quad(&cr, 0);
1954         cf_put_4bytes(&cr, 'I', 'P', 'v', '4');
1955         cf_unit_end(&cr);
1956
1957         /* IPv6 unit directory, draft-ietf-ipngwg-1394-01.txt */
1958         cf_unit_begin(&cr, 4);
1959         cf_put_keyval(&cr, 0x12, 0x00005e);     /* Unit spec ID */
1960         cf_put_refer(&cr, 0x81, 8);             /* Textual description unit */
1961         cf_put_keyval(&cr, 0x13, 0x000002);     /* (Proposed) Unit software version */
1962         cf_put_refer(&cr, 0x81, 9);             /* Textual description unit */
1963         cf_unit_end(&cr);
1964
1965         cf_unit_begin(&cr, 8);
1966         cf_put_keyval(&cr, 0, 0);
1967         cf_put_1quad(&cr, 0);
1968         cf_put_4bytes(&cr, 'I', 'A', 'N', 'A');
1969         cf_unit_end(&cr);
1970
1971         cf_unit_begin(&cr, 9);
1972         cf_put_keyval(&cr, 0, 0);
1973         cf_put_1quad(&cr, 0);
1974         cf_put_4bytes(&cr, 'I', 'P', 'v', '6');
1975         cf_unit_end(&cr);
1976
1977         ohci->csr_config_rom_length = cr.data - ohci->csr_config_rom_cpu;
1978 }
1979
1980 static size_t ohci_get_rom(struct hpsb_host *host, const quadlet_t **ptr)
1981 {
1982         struct ti_ohci *ohci=host->hostdata;
1983
1984         DBGMSG(ohci->id, "request csr_rom address: %p",
1985                 ohci->csr_config_rom_cpu);
1986
1987         *ptr = ohci->csr_config_rom_cpu;
1988
1989         return ohci->csr_config_rom_length * 4;
1990 }
1991
1992 int ohci_compare_swap(struct ti_ohci *ohci, quadlet_t *data,
1993                       quadlet_t compare, int sel)
1994 {
1995         int i;
1996         reg_write(ohci, OHCI1394_CSRData, *data);
1997         reg_write(ohci, OHCI1394_CSRCompareData, compare);
1998         reg_write(ohci, OHCI1394_CSRControl, sel & 0x3);
1999
2000         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
2001                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
2002                         break;
2003
2004                 mdelay(1);
2005         }
2006
2007         *data = reg_read(ohci, OHCI1394_CSRData);
2008         return 0;
2009 }
2010
2011 static quadlet_t ohci_hw_csr_reg(struct hpsb_host *host, int reg,
2012                                  quadlet_t data, quadlet_t compare)
2013 {
2014         struct ti_ohci *ohci=host->hostdata;
2015
2016         ohci_compare_swap (ohci, &data, compare, reg);
2017
2018         return data;
2019 }
2020
2021 static struct hpsb_host_template ohci_template = {
2022         name:                   OHCI1394_DRIVER_NAME,
2023         initialize_host:        ohci_initialize,
2024         release_host:           ohci_remove,
2025         get_rom:                ohci_get_rom,
2026         transmit_packet:        ohci_transmit,
2027         devctl:                 ohci_devctl,
2028         hw_csr_reg:             ohci_hw_csr_reg,
2029 };
2030
2031 static int __devinit ohci1394_add_one(struct pci_dev *dev, const struct pci_device_id *ent)
2032 {
2033         struct ti_ohci *ohci;   /* shortcut to currently handled device */
2034         struct hpsb_host *host;
2035         unsigned long ohci_base, ohci_len;
2036         static int version_printed = 0;
2037
2038         if (version_printed++ == 0)
2039                 PRINT_G(KERN_INFO, "%s", version);
2040
2041         if (pci_enable_device(dev)) {
2042                 /* Skip ID's that fail */
2043                 PRINT_G(KERN_NOTICE, "Failed to enable OHCI hardware %d",
2044                         card_id_counter++);
2045                 return -ENXIO;
2046         }
2047         pci_set_master(dev);
2048
2049         host = hpsb_get_host(&ohci_template, sizeof (struct ti_ohci));
2050         if (!host) {
2051                 PRINT_G(KERN_ERR, "Out of memory trying to allocate host structure");
2052                 return -ENOMEM;
2053         }
2054         ohci = host->hostdata;
2055         ohci->host = host;
2056         INIT_LIST_HEAD(&ohci->list);
2057         ohci->id = card_id_counter++;
2058         ohci->dev = dev;
2059         host->pdev = dev;
2060         ohci->host = host;
2061         pci_set_drvdata(dev, ohci);
2062
2063         /* We don't want hardware swapping */
2064         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2065
2066         /* Some oddball Apple controllers do not order the selfid
2067          * properly, so we make up for it here.  */
2068 #ifndef __LITTLE_ENDIAN
2069         /* XXX: Need a better way to check this. I'm wondering if we can
2070          * read the values of the OHCI1394_PCI_HCI_Control and the
2071          * noByteSwapData registers to see if they were not cleared to
2072          * zero. Should this work? Obviously it's not defined what these
2073          * registers will read when they aren't supported. Bleh! */
2074         if (dev->vendor == PCI_VENDOR_ID_APPLE) {
2075                 ohci->payload_swap = 1;
2076                 if (dev->device != PCI_DEVICE_ID_APPLE_UNI_N_FW)
2077                         ohci->selfid_swap = 1;
2078         } else
2079                 ohci->selfid_swap = 1;
2080 #endif
2081
2082         /* csr_config rom allocation */
2083         ohci->csr_config_rom_cpu = 
2084                 pci_alloc_consistent(ohci->dev, OHCI_CONFIG_ROM_LEN,
2085                                      &ohci->csr_config_rom_bus);
2086         OHCI_DMA_ALLOC("consistent csr_config_rom");
2087         if (ohci->csr_config_rom_cpu == NULL)
2088                 FAIL("Failed to allocate buffer config rom");
2089
2090         /* 
2091          * self-id dma buffer allocation
2092          */
2093         ohci->selfid_buf_cpu = 
2094                 pci_alloc_consistent(ohci->dev, OHCI1394_SI_DMA_BUF_SIZE,
2095                       &ohci->selfid_buf_bus);
2096         OHCI_DMA_ALLOC("consistent selfid_buf");
2097         if (ohci->selfid_buf_cpu == NULL)
2098                 FAIL("Failed to allocate DMA buffer for self-id packets");
2099
2100         if ((unsigned long)ohci->selfid_buf_cpu & 0x1fff)
2101                 PRINT(KERN_INFO, ohci->id, "SelfID buffer %p is not aligned on "
2102                       "8Kb boundary... may cause problems on some CXD3222 chip", 
2103                       ohci->selfid_buf_cpu);  
2104
2105         ohci->it_context =
2106                 alloc_dma_trm_ctx(ohci, 2, IT_NUM_DESC,
2107                                   OHCI1394_IsoXmitContextControlSet,
2108                                   OHCI1394_IsoXmitContextControlClear,
2109                                   OHCI1394_IsoXmitCommandPtr);
2110
2111         if (ohci->it_context == NULL)
2112                 FAIL("Failed to allocate IT context");
2113
2114         ohci_base = pci_resource_start(dev, 0);
2115         ohci_len = pci_resource_len(dev, 0);
2116
2117         if (!request_mem_region (ohci_base, ohci_len, host->template->name))
2118                 FAIL("MMIO resource (0x%lx@0x%lx) unavailable, aborting.",
2119                      ohci_base, ohci_len);
2120
2121         ohci->registers = ioremap(ohci_base, ohci_len);
2122
2123         if (ohci->registers == NULL)
2124                 FAIL("Failed to remap registers - card not accessible");
2125
2126         DBGMSG(ohci->id, "Remapped memory spaces reg 0x%p",
2127               ohci->registers);
2128
2129         ohci->ar_req_context = 
2130                 alloc_dma_rcv_ctx(ohci, 0, AR_REQ_NUM_DESC,
2131                                   AR_REQ_BUF_SIZE, AR_REQ_SPLIT_BUF_SIZE,
2132                                   OHCI1394_AsReqRcvContextControlSet,
2133                                   OHCI1394_AsReqRcvContextControlClear,
2134                                   OHCI1394_AsReqRcvCommandPtr);
2135
2136         if (ohci->ar_req_context == NULL)
2137                 FAIL("Failed to allocate AR Req context");
2138
2139         ohci->ar_resp_context = 
2140                 alloc_dma_rcv_ctx(ohci, 1, AR_RESP_NUM_DESC,
2141                                   AR_RESP_BUF_SIZE, AR_RESP_SPLIT_BUF_SIZE,
2142                                   OHCI1394_AsRspRcvContextControlSet,
2143                                   OHCI1394_AsRspRcvContextControlClear,
2144                                   OHCI1394_AsRspRcvCommandPtr);
2145         
2146         if (ohci->ar_resp_context == NULL)
2147                 FAIL("Failed to allocate AR Resp context");
2148
2149         ohci->at_req_context = 
2150                 alloc_dma_trm_ctx(ohci, 0, AT_REQ_NUM_DESC,
2151                                   OHCI1394_AsReqTrContextControlSet,
2152                                   OHCI1394_AsReqTrContextControlClear,
2153                                   OHCI1394_AsReqTrCommandPtr);
2154         
2155         if (ohci->at_req_context == NULL)
2156                 FAIL("Failed to allocate AT Req context");
2157
2158         ohci->at_resp_context = 
2159                 alloc_dma_trm_ctx(ohci, 1, AT_RESP_NUM_DESC,
2160                                   OHCI1394_AsRspTrContextControlSet,
2161                                   OHCI1394_AsRspTrContextControlClear,
2162                                   OHCI1394_AsRspTrCommandPtr);
2163         
2164         if (ohci->at_resp_context == NULL)
2165                 FAIL("Failed to allocate AT Resp context");
2166
2167         ohci->ir_context =
2168                 alloc_dma_rcv_ctx(ohci, 2, IR_NUM_DESC,
2169                                   IR_BUF_SIZE, IR_SPLIT_BUF_SIZE,
2170                                   OHCI1394_IsoRcvContextControlSet,
2171                                   OHCI1394_IsoRcvContextControlClear,
2172                                   OHCI1394_IsoRcvCommandPtr);
2173
2174         if (ohci->ir_context == NULL)
2175                 FAIL("Failed to allocate IR context");
2176
2177         ohci->ISO_channel_usage = 0;
2178         spin_lock_init(&ohci->IR_channel_lock);
2179
2180         if (request_irq(dev->irq, ohci_irq_handler, SA_SHIRQ,
2181                          OHCI1394_DRIVER_NAME, ohci))
2182                 FAIL("Failed to allocate shared interrupt %d", dev->irq);
2183
2184         /* Tell the highlevel this host is ready */
2185         highlevel_add_one_host (host);
2186
2187         return 0;
2188 #undef FAIL
2189 }
2190
2191 static void remove_card(struct ti_ohci *ohci)
2192 {
2193         quadlet_t buf;
2194
2195         /* Soft reset before we start */
2196         ohci_soft_reset(ohci);
2197
2198         /* Free AR dma */
2199         free_dma_rcv_ctx(&ohci->ar_req_context);
2200         free_dma_rcv_ctx(&ohci->ar_resp_context);
2201
2202         /* Free AT dma */
2203         free_dma_trm_ctx(&ohci->at_req_context);
2204         free_dma_trm_ctx(&ohci->at_resp_context);
2205
2206         /* Free IR dma */
2207         free_dma_rcv_ctx(&ohci->ir_context);
2208
2209         /* Free IT dma */
2210         free_dma_trm_ctx(&ohci->it_context);
2211
2212         /* Disable all interrupts */
2213         reg_write(ohci, OHCI1394_IntMaskClear, 0x80000000);
2214         free_irq(ohci->dev->irq, ohci);
2215
2216         /* Free self-id buffer */
2217         if (ohci->selfid_buf_cpu) {
2218                 pci_free_consistent(ohci->dev, OHCI1394_SI_DMA_BUF_SIZE, 
2219                                     ohci->selfid_buf_cpu,
2220                                     ohci->selfid_buf_bus);
2221                 OHCI_DMA_FREE("consistent selfid_buf");
2222         }
2223         
2224         /* Free config rom */
2225         if (ohci->csr_config_rom_cpu) {
2226                 pci_free_consistent(ohci->dev, OHCI_CONFIG_ROM_LEN,
2227                                     ohci->csr_config_rom_cpu, 
2228                                     ohci->csr_config_rom_bus);
2229                 OHCI_DMA_FREE("consistent csr_config_rom");
2230         }
2231
2232         /* Disable our bus options */
2233         buf = reg_read(ohci, OHCI1394_BusOptions);
2234         buf &= ~0xf8000000;
2235         buf |=  0x00ff0000;
2236         reg_write(ohci, OHCI1394_BusOptions, buf);
2237
2238         /* Clear LinkEnable and LPS */
2239         reg_write(ohci, OHCI1394_HCControlClear, 0x000a0000);
2240
2241         if (ohci->registers)
2242                 iounmap(ohci->registers);
2243
2244         release_mem_region (pci_resource_start(ohci->dev, 0),
2245                             pci_resource_len(ohci->dev, 0));
2246
2247         pci_set_drvdata(ohci->dev, NULL);
2248 }
2249
2250 void ohci1394_stop_context(struct ti_ohci *ohci, int reg, char *msg)
2251 {
2252         int i=0;
2253
2254         /* stop the channel program if it's still running */
2255         reg_write(ohci, reg, 0x8000);
2256    
2257         /* Wait until it effectively stops */
2258         while (reg_read(ohci, reg) & 0x400) {
2259                 i++;
2260                 if (i>5000) {
2261                         PRINT(KERN_ERR, ohci->id, 
2262                               "Runaway loop while stopping context...");
2263                         break;
2264                 }
2265         }
2266         if (msg) PRINT(KERN_ERR, ohci->id, "%s: dma prg stopped", msg);
2267 }
2268
2269 int ohci1394_register_video(struct ti_ohci *ohci,
2270                             struct video_template *tmpl)
2271 {
2272         if (ohci->video_tmpl)
2273                 return -ENFILE;
2274         ohci->video_tmpl = tmpl;
2275         MOD_INC_USE_COUNT;
2276         return 0;
2277 }
2278         
2279 void ohci1394_unregister_video(struct ti_ohci *ohci,
2280                                struct video_template *tmpl)
2281 {
2282         if (ohci->video_tmpl != tmpl) {
2283                 PRINT(KERN_ERR, ohci->id, 
2284                       "Trying to unregister wrong video device");
2285         } else {
2286                 ohci->video_tmpl = NULL;
2287                 MOD_DEC_USE_COUNT;
2288         }
2289 }
2290
2291 #ifndef __LITTLE_ENDIAN
2292
2293 /* Swap a series of quads inplace. */
2294 static __inline__ void block_swab32(quadlet_t *data, size_t size) {
2295         while (size--)
2296                 data[size] = swab32(data[size]);
2297 }
2298
2299 /* Swap headers and sometimes data too */
2300 static void packet_swab(quadlet_t *data, char tcode, int len, int payload_swap)
2301 {
2302         if (payload_swap) {
2303                 block_swab32(data, len);
2304                 return;
2305         }
2306
2307         switch(tcode)
2308         {
2309                 /* 4 quad header */
2310                 case TCODE_READB_RESPONSE:
2311                 case TCODE_LOCK_RESPONSE:
2312                 case TCODE_LOCK_REQUEST:
2313                 case TCODE_WRITEB:
2314                 case TCODE_READB:
2315                         block_swab32(data, 4);
2316                         break;
2317
2318                 /* 3 quad header, 1 quad payload */
2319                 case TCODE_WRITEQ:
2320                 case TCODE_READQ_RESPONSE:
2321                         block_swab32(data, 3);
2322                         break;
2323
2324                 /* 3 quad header */
2325                 case TCODE_WRITE_RESPONSE:
2326                 case TCODE_READQ:
2327                         block_swab32(data, 3);
2328                         break;
2329
2330                 /* 2 quad header */
2331                 case TCODE_ISO_DATA:
2332                         block_swab32(data, 2);
2333                         break;
2334
2335                 case OHCI1394_TCODE_PHY:
2336                         break; /* should never happen anyway */
2337
2338                 case TCODE_CYCLE_START:
2339                         PRINT_G(KERN_ERR, "Unhandled tcode in packet_swab (0x%x)", tcode);
2340                         /* Atleast swap one quad */
2341                         block_swab32(data, 1);
2342                         break;
2343                 default:
2344                         PRINT_G(KERN_ERR, "Invalid tcode in packet_swab (0x%x)", tcode);
2345                         break;
2346         }
2347         return;
2348 }
2349
2350 #endif /* !LITTLE_ENDIAN */
2351
2352
2353 #if 0
2354 int ohci1394_request_channel(struct ti_ohci *ohci, int channel)
2355 {
2356         int csrSel;
2357         quadlet_t chan, data1=0, data2=0;
2358         int timeout = 32;
2359
2360         if (channel<32) {
2361                 chan = 1<<channel;
2362                 csrSel = 2;
2363         }
2364         else {
2365                 chan = 1<<(channel-32);
2366                 csrSel = 3;
2367         }
2368         if (ohci_compare_swap(ohci, &data1, 0, csrSel)<0) {
2369                 PRINT(KERN_INFO, ohci->id, "request_channel timeout");
2370                 return -1;
2371         }
2372         while (timeout--) {
2373                 if (data1 & chan) {
2374                         PRINT(KERN_INFO, ohci->id, 
2375                               "request channel %d failed", channel);
2376                         return -1;
2377                 }
2378                 data2 = data1;
2379                 data1 |= chan;
2380                 if (ohci_compare_swap(ohci, &data1, data2, csrSel)<0) {
2381                         PRINT(KERN_INFO, ohci->id, "request_channel timeout");
2382                         return -1;
2383                 }
2384                 if (data1==data2) {
2385                         PRINT(KERN_INFO, ohci->id, 
2386                               "request channel %d succeded", channel);
2387                         return 0;
2388                 }
2389         }
2390         PRINT(KERN_INFO, ohci->id, "request channel %d failed", channel);
2391         return -1;
2392 }
2393 #endif
2394
2395 EXPORT_SYMBOL(ohci1394_stop_context);
2396 EXPORT_SYMBOL(ohci1394_register_video);
2397 EXPORT_SYMBOL(ohci1394_unregister_video);
2398
2399 MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>");
2400 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE-1394 controllers");
2401
2402 static void __devexit ohci1394_remove_one(struct pci_dev *pdev)
2403 {
2404         struct ti_ohci *ohci = pci_get_drvdata(pdev);
2405
2406         if (ohci) {
2407                 remove_card (ohci);
2408                 pci_set_drvdata(pdev, NULL);
2409         }
2410 }
2411
2412 static struct pci_driver ohci1394_driver = {
2413         name:           OHCI1394_DRIVER_NAME,
2414         id_table:       ohci1394_pci_tbl,
2415         probe:          ohci1394_add_one,
2416         remove:         ohci1394_remove_one,
2417 };
2418
2419 static void __exit ohci1394_cleanup (void)
2420 {
2421         hpsb_unregister_lowlevel(&ohci_template);
2422         pci_unregister_driver(&ohci1394_driver);
2423 }
2424
2425 static int __init ohci1394_init(void)
2426 {
2427         int ret;
2428         if (hpsb_register_lowlevel(&ohci_template)) {
2429                 PRINT_G(KERN_ERR, "Registering failed");
2430                 return -ENXIO;
2431         }
2432         if ((ret = pci_module_init(&ohci1394_driver))) {
2433                 PRINT_G(KERN_ERR, "PCI module init failed");
2434                 hpsb_unregister_lowlevel(&ohci_template);
2435                 return ret;
2436         }
2437         return ret;
2438 }
2439
2440 module_init(ohci1394_init);
2441 module_exit(ohci1394_cleanup);