v2.4.8 -> v2.4.8.1
[opensuse:kernel.git] / drivers / ide / ide-pci.c
1 /*
2  *  linux/drivers/ide/ide-pci.c         Version 1.05    June 9, 2000
3  *
4  *  Copyright (c) 1998-2000  Andre Hedrick <andre@linux-ide.org>
5  *
6  *  Copyright (c) 1995-1998  Mark Lord
7  *  May be copied or modified under the terms of the GNU General Public License
8  */
9
10 /*
11  *  This module provides support for automatic detection and
12  *  configuration of all PCI IDE interfaces present in a system.  
13  */
14
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/timer.h>
19 #include <linux/mm.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/init.h>
23 #include <linux/ide.h>
24
25 #include <asm/io.h>
26 #include <asm/irq.h>
27
28 #define DEVID_PIIXa     ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82371FB_0})
29 #define DEVID_PIIXb     ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82371FB_1})
30 #define DEVID_PIIX3     ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82371SB_1})
31 #define DEVID_PIIX4     ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82371AB})
32 #define DEVID_ICH0      ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801AB_1})
33 #define DEVID_PIIX4E2   ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82443MX_1})
34 #define DEVID_ICH       ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801AA_1})
35 #define DEVID_PIIX4U2   ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82372FB_1})
36 #define DEVID_PIIX4NX   ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82451NX})
37 #define DEVID_ICH2      ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801BA_9})
38 #define DEVID_ICH2M     ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801BA_8})
39 #define DEVID_VIA_IDE   ((ide_pci_devid_t){PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C561})
40 #define DEVID_VP_IDE    ((ide_pci_devid_t){PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_82C586_1})
41 #define DEVID_PDC20246  ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246})
42 #define DEVID_PDC20262  ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262})
43 #define DEVID_PDC20265  ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265})
44 #define DEVID_PDC20267  ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267})
45 #define DEVID_RZ1000    ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH,  PCI_DEVICE_ID_PCTECH_RZ1000})
46 #define DEVID_RZ1001    ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH,  PCI_DEVICE_ID_PCTECH_RZ1001})
47 #define DEVID_SAMURAI   ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH,  PCI_DEVICE_ID_PCTECH_SAMURAI_IDE})
48 #define DEVID_CMD640    ((ide_pci_devid_t){PCI_VENDOR_ID_CMD,     PCI_DEVICE_ID_CMD_640})
49 #define DEVID_CMD643    ((ide_pci_devid_t){PCI_VENDOR_ID_CMD,     PCI_DEVICE_ID_CMD_643})
50 #define DEVID_CMD646    ((ide_pci_devid_t){PCI_VENDOR_ID_CMD,     PCI_DEVICE_ID_CMD_646})
51 #define DEVID_CMD648    ((ide_pci_devid_t){PCI_VENDOR_ID_CMD,     PCI_DEVICE_ID_CMD_648})
52 #define DEVID_CMD649    ((ide_pci_devid_t){PCI_VENDOR_ID_CMD,     PCI_DEVICE_ID_CMD_649})
53 #define DEVID_SIS5513   ((ide_pci_devid_t){PCI_VENDOR_ID_SI,      PCI_DEVICE_ID_SI_5513})
54 #define DEVID_OPTI621   ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI,    PCI_DEVICE_ID_OPTI_82C621})
55 #define DEVID_OPTI621V  ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI,    PCI_DEVICE_ID_OPTI_82C558})
56 #define DEVID_OPTI621X  ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI,    PCI_DEVICE_ID_OPTI_82C825})
57 #define DEVID_TRM290    ((ide_pci_devid_t){PCI_VENDOR_ID_TEKRAM,  PCI_DEVICE_ID_TEKRAM_DC290})
58 #define DEVID_NS87410   ((ide_pci_devid_t){PCI_VENDOR_ID_NS,      PCI_DEVICE_ID_NS_87410})
59 #define DEVID_NS87415   ((ide_pci_devid_t){PCI_VENDOR_ID_NS,      PCI_DEVICE_ID_NS_87415})
60 #define DEVID_HT6565    ((ide_pci_devid_t){PCI_VENDOR_ID_HOLTEK,  PCI_DEVICE_ID_HOLTEK_6565})
61 #define DEVID_AEC6210   ((ide_pci_devid_t){PCI_VENDOR_ID_ARTOP,   PCI_DEVICE_ID_ARTOP_ATP850UF})
62 #define DEVID_AEC6260   ((ide_pci_devid_t){PCI_VENDOR_ID_ARTOP,   PCI_DEVICE_ID_ARTOP_ATP860})
63 #define DEVID_AEC6260R  ((ide_pci_devid_t){PCI_VENDOR_ID_ARTOP,   PCI_DEVICE_ID_ARTOP_ATP860R})
64 #define DEVID_W82C105   ((ide_pci_devid_t){PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105})
65 #define DEVID_UM8673F   ((ide_pci_devid_t){PCI_VENDOR_ID_UMC,     PCI_DEVICE_ID_UMC_UM8673F})
66 #define DEVID_UM8886A   ((ide_pci_devid_t){PCI_VENDOR_ID_UMC,     PCI_DEVICE_ID_UMC_UM8886A})
67 #define DEVID_UM8886BF  ((ide_pci_devid_t){PCI_VENDOR_ID_UMC,     PCI_DEVICE_ID_UMC_UM8886BF})
68 #define DEVID_HPT34X    ((ide_pci_devid_t){PCI_VENDOR_ID_TTI,     PCI_DEVICE_ID_TTI_HPT343})
69 #define DEVID_HPT366    ((ide_pci_devid_t){PCI_VENDOR_ID_TTI,     PCI_DEVICE_ID_TTI_HPT366})
70 #define DEVID_ALI15X3   ((ide_pci_devid_t){PCI_VENDOR_ID_AL,      PCI_DEVICE_ID_AL_M5229})
71 #define DEVID_CY82C693  ((ide_pci_devid_t){PCI_VENDOR_ID_CONTAQ,  PCI_DEVICE_ID_CONTAQ_82C693})
72 #define DEVID_HINT      ((ide_pci_devid_t){0x3388,                0x8013})
73 #define DEVID_CS5530    ((ide_pci_devid_t){PCI_VENDOR_ID_CYRIX,   PCI_DEVICE_ID_CYRIX_5530_IDE})
74 #define DEVID_AMD7403   ((ide_pci_devid_t){PCI_VENDOR_ID_AMD,     PCI_DEVICE_ID_AMD_COBRA_7403})
75 #define DEVID_AMD7409   ((ide_pci_devid_t){PCI_VENDOR_ID_AMD,     PCI_DEVICE_ID_AMD_VIPER_7409})
76 #define DEVID_SLC90E66  ((ide_pci_devid_t){PCI_VENDOR_ID_EFAR,    PCI_DEVICE_ID_EFAR_SLC90E66_1})
77 #define DEVID_OSB4      ((ide_pci_devid_t){PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE})
78
79 #define IDE_IGNORE      ((void *)-1)
80
81 #ifdef CONFIG_BLK_DEV_AEC62XX
82 extern unsigned int pci_init_aec62xx(struct pci_dev *, const char *);
83 extern unsigned int ata66_aec62xx(ide_hwif_t *);
84 extern void ide_init_aec62xx(ide_hwif_t *);
85 extern void ide_dmacapable_aec62xx(ide_hwif_t *, unsigned long);
86 #define PCI_AEC62XX     &pci_init_aec62xx
87 #define ATA66_AEC62XX   &ata66_aec62xx
88 #define INIT_AEC62XX    &ide_init_aec62xx
89 #define DMA_AEC62XX     &ide_dmacapable_aec62xx
90 #else
91 #define PCI_AEC62XX     NULL
92 #define ATA66_AEC62XX   NULL
93 #define INIT_AEC62XX    NULL
94 #define DMA_AEC62XX     NULL
95 #endif
96
97 #ifdef CONFIG_BLK_DEV_ALI15X3
98 extern unsigned int pci_init_ali15x3(struct pci_dev *, const char *);
99 extern unsigned int ata66_ali15x3(ide_hwif_t *);
100 extern void ide_init_ali15x3(ide_hwif_t *);
101 extern void ide_dmacapable_ali15x3(ide_hwif_t *, unsigned long);
102 #define PCI_ALI15X3     &pci_init_ali15x3
103 #define ATA66_ALI15X3   &ata66_ali15x3
104 #define INIT_ALI15X3    &ide_init_ali15x3
105 #define DMA_ALI15X3     &ide_dmacapable_ali15x3
106 #else
107 #define PCI_ALI15X3     NULL
108 #define ATA66_ALI15X3   NULL
109 #define INIT_ALI15X3    NULL
110 #define DMA_ALI15X3     NULL
111 #endif
112
113 #ifdef CONFIG_BLK_DEV_AMD7409
114 extern unsigned int pci_init_amd7409(struct pci_dev *, const char *);
115 extern unsigned int ata66_amd7409(ide_hwif_t *);
116 extern void ide_init_amd7409(ide_hwif_t *);
117 extern void ide_dmacapable_amd7409(ide_hwif_t *, unsigned long);
118 #define PCI_AMD7409     &pci_init_amd7409
119 #define ATA66_AMD7409   &ata66_amd7409
120 #define INIT_AMD7409    &ide_init_amd7409
121 #define DMA_AMD7409     &ide_dmacapable_amd7409
122 #else
123 #define PCI_AMD7409     NULL
124 #define ATA66_AMD7409   NULL
125 #define INIT_AMD7409    NULL
126 #define DMA_AMD7409     NULL
127 #endif
128
129 #ifdef CONFIG_BLK_DEV_CMD64X
130 extern unsigned int pci_init_cmd64x(struct pci_dev *, const char *);
131 extern unsigned int ata66_cmd64x(ide_hwif_t *);
132 extern void ide_init_cmd64x(ide_hwif_t *);
133 extern void ide_dmacapable_cmd64x(ide_hwif_t *, unsigned long);
134 #define PCI_CMD64X      &pci_init_cmd64x
135 #define ATA66_CMD64X    &ata66_cmd64x
136 #define INIT_CMD64X     &ide_init_cmd64x
137 #else
138 #define PCI_CMD64X      NULL
139 #define ATA66_CMD64X    NULL
140 #ifdef __sparc_v9__
141 #define INIT_CMD64X     IDE_IGNORE
142 #else
143 #define INIT_CMD64X     NULL
144 #endif
145 #endif
146
147 #ifdef CONFIG_BLK_DEV_CY82C693
148 extern unsigned int pci_init_cy82c693(struct pci_dev *, const char *);
149 extern void ide_init_cy82c693(ide_hwif_t *);
150 #define PCI_CY82C693    &pci_init_cy82c693
151 #define INIT_CY82C693   &ide_init_cy82c693
152 #else
153 #define PCI_CY82C693    NULL
154 #define INIT_CY82C693   NULL
155 #endif
156
157 #ifdef CONFIG_BLK_DEV_CS5530
158 extern unsigned int pci_init_cs5530(struct pci_dev *, const char *);
159 extern void ide_init_cs5530(ide_hwif_t *);
160 #define PCI_CS5530      &pci_init_cs5530
161 #define INIT_CS5530     &ide_init_cs5530
162 #else
163 #define PCI_CS5530      NULL
164 #define INIT_CS5530     NULL
165 #endif
166
167 #ifdef CONFIG_BLK_DEV_HPT34X
168 extern unsigned int pci_init_hpt34x(struct pci_dev *, const char *);
169 extern void ide_init_hpt34x(ide_hwif_t *);
170 #define PCI_HPT34X      &pci_init_hpt34x
171 #define INIT_HPT34X     &ide_init_hpt34x
172 #else
173 #define PCI_HPT34X      NULL
174 #define INIT_HPT34X     IDE_IGNORE
175 #endif
176
177 #ifdef CONFIG_BLK_DEV_HPT366
178 extern byte hpt363_shared_irq;
179 extern byte hpt363_shared_pin;
180 extern unsigned int pci_init_hpt366(struct pci_dev *, const char *);
181 extern unsigned int ata66_hpt366(ide_hwif_t *);
182 extern void ide_init_hpt366(ide_hwif_t *);
183 extern void ide_dmacapable_hpt366(ide_hwif_t *, unsigned long);
184 #define PCI_HPT366      &pci_init_hpt366
185 #define ATA66_HPT366    &ata66_hpt366
186 #define INIT_HPT366     &ide_init_hpt366
187 #define DMA_HPT366      &ide_dmacapable_hpt366
188 #else
189 static byte hpt363_shared_irq = 0;
190 static byte hpt363_shared_pin = 0;
191 #define PCI_HPT366      NULL
192 #define ATA66_HPT366    NULL
193 #define INIT_HPT366     NULL
194 #define DMA_HPT366      NULL
195 #endif
196
197 #ifdef CONFIG_BLK_DEV_NS87415
198 extern void ide_init_ns87415(ide_hwif_t *);
199 #define INIT_NS87415    &ide_init_ns87415
200 #else
201 #define INIT_NS87415    IDE_IGNORE
202 #endif
203
204 #ifdef CONFIG_BLK_DEV_OPTI621
205 extern void ide_init_opti621(ide_hwif_t *);
206 #define INIT_OPTI621    &ide_init_opti621
207 #else
208 #define INIT_OPTI621    NULL
209 #endif
210
211 #ifdef CONFIG_BLK_DEV_OSB4
212 extern unsigned int pci_init_osb4(struct pci_dev *, const char *);
213 extern unsigned int ata66_osb4(ide_hwif_t *);
214 extern void ide_init_osb4(ide_hwif_t *);
215 #define PCI_OSB4        &pci_init_osb4
216 #define ATA66_OSB4      &ata66_osb4
217 #define INIT_OSB4       &ide_init_osb4
218 #else
219 #define PCI_OSB4        NULL
220 #define ATA66_OSB4      NULL
221 #define INIT_OSB4       NULL
222 #endif
223
224 #ifdef CONFIG_BLK_DEV_PDC202XX
225 extern unsigned int pci_init_pdc202xx(struct pci_dev *, const char *);
226 extern unsigned int ata66_pdc202xx(ide_hwif_t *);
227 extern void ide_init_pdc202xx(ide_hwif_t *);
228 #define PCI_PDC202XX    &pci_init_pdc202xx
229 #define ATA66_PDC202XX  &ata66_pdc202xx
230 #define INIT_PDC202XX   &ide_init_pdc202xx
231 #else
232 #define PCI_PDC202XX    NULL
233 #define ATA66_PDC202XX  NULL
234 #define INIT_PDC202XX   NULL
235 #endif
236
237 #ifdef CONFIG_BLK_DEV_PIIX
238 extern unsigned int pci_init_piix(struct pci_dev *, const char *);
239 extern unsigned int ata66_piix(ide_hwif_t *);
240 extern void ide_init_piix(ide_hwif_t *);
241 #define PCI_PIIX        &pci_init_piix
242 #define ATA66_PIIX      &ata66_piix
243 #define INIT_PIIX       &ide_init_piix
244 #else
245 #define PCI_PIIX        NULL
246 #define ATA66_PIIX      NULL
247 #define INIT_PIIX       NULL
248 #endif
249
250 #ifdef CONFIG_BLK_DEV_RZ1000
251 extern void ide_init_rz1000(ide_hwif_t *);
252 #define INIT_RZ1000     &ide_init_rz1000
253 #else
254 #define INIT_RZ1000     IDE_IGNORE
255 #endif
256
257 #define INIT_SAMURAI    NULL
258
259 #ifdef CONFIG_BLK_DEV_SIS5513
260 extern unsigned int pci_init_sis5513(struct pci_dev *, const char *);
261 extern unsigned int ata66_sis5513(ide_hwif_t *);
262 extern void ide_init_sis5513(ide_hwif_t *);
263 #define PCI_SIS5513     &pci_init_sis5513
264 #define ATA66_SIS5513   &ata66_sis5513
265 #define INIT_SIS5513    &ide_init_sis5513
266 #else
267 #define PCI_SIS5513     NULL
268 #define ATA66_SIS5513   NULL
269 #define INIT_SIS5513    NULL
270 #endif
271
272 #ifdef CONFIG_BLK_DEV_SLC90E66
273 extern unsigned int pci_init_slc90e66(struct pci_dev *, const char *);
274 extern unsigned int ata66_slc90e66(ide_hwif_t *);
275 extern void ide_init_slc90e66(ide_hwif_t *);
276 #define PCI_SLC90E66    &pci_init_slc90e66
277 #define ATA66_SLC90E66  &ata66_slc90e66
278 #define INIT_SLC90E66   &ide_init_slc90e66
279 #else
280 #define PCI_SLC90E66    NULL
281 #define ATA66_SLC90E66  NULL
282 #define INIT_SLC90E66   NULL
283 #endif
284
285 #ifdef CONFIG_BLK_DEV_SL82C105
286 extern unsigned int pci_init_sl82c105(struct pci_dev *, const char *);
287 extern void dma_init_sl82c105(ide_hwif_t *, unsigned long);
288 extern void ide_init_sl82c105(ide_hwif_t *);
289 #define PCI_W82C105     &pci_init_sl82c105
290 #define DMA_W82C105     &dma_init_sl82c105
291 #define INIT_W82C105    &ide_init_sl82c105
292 #else
293 #define PCI_W82C105     NULL
294 #define DMA_W82C105     NULL
295 #define INIT_W82C105    IDE_IGNORE
296 #endif
297
298 #ifdef CONFIG_BLK_DEV_TRM290
299 extern void ide_init_trm290(ide_hwif_t *);
300 #define INIT_TRM290     &ide_init_trm290
301 #else
302 #define INIT_TRM290     IDE_IGNORE
303 #endif
304
305 #ifdef CONFIG_BLK_DEV_VIA82CXXX
306 extern unsigned int pci_init_via82cxxx(struct pci_dev *, const char *);
307 extern unsigned int ata66_via82cxxx(ide_hwif_t *);
308 extern void ide_init_via82cxxx(ide_hwif_t *);
309 extern void ide_dmacapable_via82cxxx(ide_hwif_t *, unsigned long);
310 #define PCI_VIA82CXXX   &pci_init_via82cxxx
311 #define ATA66_VIA82CXXX &ata66_via82cxxx
312 #define INIT_VIA82CXXX  &ide_init_via82cxxx
313 #define DMA_VIA82CXXX   &ide_dmacapable_via82cxxx
314 #else
315 #define PCI_VIA82CXXX   NULL
316 #define ATA66_VIA82CXXX NULL
317 #define INIT_VIA82CXXX  NULL
318 #define DMA_VIA82CXXX   NULL
319 #endif
320
321 typedef struct ide_pci_enablebit_s {
322         byte    reg;    /* byte pci reg holding the enable-bit */
323         byte    mask;   /* mask to isolate the enable-bit */
324         byte    val;    /* value of masked reg when "enabled" */
325 } ide_pci_enablebit_t;
326
327 typedef struct ide_pci_device_s {
328         ide_pci_devid_t         devid;
329         char                    *name;
330         unsigned int            (*init_chipset)(struct pci_dev *dev, const char *name);
331         unsigned int            (*ata66_check)(ide_hwif_t *hwif);
332         void                    (*init_hwif)(ide_hwif_t *hwif);
333         void                    (*dma_init)(ide_hwif_t *hwif, unsigned long dmabase);
334         ide_pci_enablebit_t     enablebits[2];
335         byte                    bootable;
336         unsigned int            extra;
337 } ide_pci_device_t;
338
339 static ide_pci_device_t ide_pci_chipsets[] __initdata = {
340         {DEVID_PIIXa,   "PIIX",         NULL,           NULL,           INIT_PIIX,      NULL,           {{0x41,0x80,0x80}, {0x43,0x80,0x80}},   ON_BOARD,       0 },
341         {DEVID_PIIXb,   "PIIX",         NULL,           NULL,           INIT_PIIX,      NULL,           {{0x41,0x80,0x80}, {0x43,0x80,0x80}},   ON_BOARD,       0 },
342         {DEVID_PIIX3,   "PIIX3",        PCI_PIIX,       NULL,           INIT_PIIX,      NULL,           {{0x41,0x80,0x80}, {0x43,0x80,0x80}},   ON_BOARD,       0 },
343         {DEVID_PIIX4,   "PIIX4",        PCI_PIIX,       NULL,           INIT_PIIX,      NULL,           {{0x41,0x80,0x80}, {0x43,0x80,0x80}},   ON_BOARD,       0 },
344         {DEVID_ICH0,    "ICH0",         PCI_PIIX,       NULL,           INIT_PIIX,      NULL,           {{0x41,0x80,0x80}, {0x43,0x80,0x80}},   ON_BOARD,       0 },
345         {DEVID_PIIX4E2, "PIIX4",        PCI_PIIX,       NULL,           INIT_PIIX,      NULL,           {{0x41,0x80,0x80}, {0x43,0x80,0x80}},   ON_BOARD,       0 },
346         {DEVID_ICH,     "ICH",          PCI_PIIX,       ATA66_PIIX,     INIT_PIIX,      NULL,           {{0x41,0x80,0x80}, {0x43,0x80,0x80}},   ON_BOARD,       0 },
347         {DEVID_PIIX4U2, "PIIX4",        PCI_PIIX,       ATA66_PIIX,     INIT_PIIX,      NULL,           {{0x41,0x80,0x80}, {0x43,0x80,0x80}},   ON_BOARD,       0 },
348         {DEVID_PIIX4NX, "PIIX4",        PCI_PIIX,       NULL,           INIT_PIIX,      NULL,           {{0x41,0x80,0x80}, {0x43,0x80,0x80}},   ON_BOARD,       0 },
349         {DEVID_ICH2,    "ICH2",         PCI_PIIX,       ATA66_PIIX,     INIT_PIIX,      NULL,           {{0x41,0x80,0x80}, {0x43,0x80,0x80}},   ON_BOARD,       0 },
350         {DEVID_ICH2M,   "ICH2-M",       PCI_PIIX,       ATA66_PIIX,     INIT_PIIX,      NULL,           {{0x41,0x80,0x80}, {0x43,0x80,0x80}},   ON_BOARD,       0 },
351         {DEVID_VIA_IDE, "VIA_IDE",      NULL,           NULL,           NULL,           NULL,           {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   ON_BOARD,       0 },
352         {DEVID_VP_IDE,  "VP_IDE",       PCI_VIA82CXXX,  ATA66_VIA82CXXX,INIT_VIA82CXXX, DMA_VIA82CXXX,  {{0x40,0x02,0x02}, {0x40,0x01,0x01}},   ON_BOARD,       0 },
353         {DEVID_PDC20246,"PDC20246",     PCI_PDC202XX,   NULL,           INIT_PDC202XX,  NULL,           {{0x50,0x02,0x02}, {0x50,0x04,0x04}},   OFF_BOARD,      16 },
354         {DEVID_PDC20262,"PDC20262",     PCI_PDC202XX,   ATA66_PDC202XX, INIT_PDC202XX,  NULL,           {{0x50,0x02,0x02}, {0x50,0x04,0x04}},   OFF_BOARD,      48 },
355         {DEVID_PDC20265,"PDC20265",     PCI_PDC202XX,   ATA66_PDC202XX, INIT_PDC202XX,  NULL,           {{0x50,0x02,0x02}, {0x50,0x04,0x04}},   OFF_BOARD,      48 },
356         {DEVID_PDC20267,"PDC20267",     PCI_PDC202XX,   ATA66_PDC202XX, INIT_PDC202XX,  NULL,           {{0x50,0x02,0x02}, {0x50,0x04,0x04}},   OFF_BOARD,      48 },
357         {DEVID_RZ1000,  "RZ1000",       NULL,           NULL,           INIT_RZ1000,    NULL,           {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   ON_BOARD,       0 },
358         {DEVID_RZ1001,  "RZ1001",       NULL,           NULL,           INIT_RZ1000,    NULL,           {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   ON_BOARD,       0 },
359         {DEVID_SAMURAI, "SAMURAI",      NULL,           NULL,           INIT_SAMURAI,   NULL,           {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   ON_BOARD,       0 },
360         {DEVID_CMD640,  "CMD640",       NULL,           NULL,           IDE_IGNORE,     NULL,           {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   ON_BOARD,       0 },
361         {DEVID_NS87410, "NS87410",      NULL,           NULL,           NULL,           NULL,           {{0x43,0x08,0x08}, {0x47,0x08,0x08}},   ON_BOARD,       0 },
362         {DEVID_SIS5513, "SIS5513",      PCI_SIS5513,    ATA66_SIS5513,  INIT_SIS5513,   NULL,           {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},   ON_BOARD,       0 },
363         {DEVID_CMD643,  "CMD643",       PCI_CMD64X,     NULL,           INIT_CMD64X,    NULL,           {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   ON_BOARD,       0 },
364         {DEVID_CMD646,  "CMD646",       PCI_CMD64X,     NULL,           INIT_CMD64X,    NULL,           {{0x00,0x00,0x00}, {0x51,0x80,0x80}},   ON_BOARD,       0 },
365         {DEVID_CMD648,  "CMD648",       PCI_CMD64X,     ATA66_CMD64X,   INIT_CMD64X,    NULL,           {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   ON_BOARD,       0 },
366         {DEVID_CMD649,  "CMD649",       PCI_CMD64X,     ATA66_CMD64X,   INIT_CMD64X,    NULL,           {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   ON_BOARD,       0 },
367         {DEVID_HT6565,  "HT6565",       NULL,           NULL,           NULL,           NULL,           {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   ON_BOARD,       0 },
368         {DEVID_OPTI621, "OPTI621",      NULL,           NULL,           INIT_OPTI621,   NULL,           {{0x45,0x80,0x00}, {0x40,0x08,0x00}},   ON_BOARD,       0 },
369         {DEVID_OPTI621X,"OPTI621X",     NULL,           NULL,           INIT_OPTI621,   NULL,           {{0x45,0x80,0x00}, {0x40,0x08,0x00}},   ON_BOARD,       0 },
370         {DEVID_TRM290,  "TRM290",       NULL,           NULL,           INIT_TRM290,    NULL,           {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   ON_BOARD,       0 },
371         {DEVID_NS87415, "NS87415",      NULL,           NULL,           INIT_NS87415,   NULL,           {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   ON_BOARD,       0 },
372         {DEVID_AEC6210, "AEC6210",      PCI_AEC62XX,    NULL,           INIT_AEC62XX,   DMA_AEC62XX,    {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},   OFF_BOARD,      0 },
373         {DEVID_AEC6260, "AEC6260",      PCI_AEC62XX,    ATA66_AEC62XX,  INIT_AEC62XX,   NULL,           {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   NEVER_BOARD,    0 },
374         {DEVID_AEC6260R,"AEC6260R",     PCI_AEC62XX,    ATA66_AEC62XX,  INIT_AEC62XX,   NULL,           {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},   OFF_BOARD,      0 },
375         {DEVID_W82C105, "W82C105",      PCI_W82C105,    NULL,           INIT_W82C105,   DMA_W82C105,    {{0x40,0x01,0x01}, {0x40,0x10,0x10}},   ON_BOARD,       0 },
376         {DEVID_UM8673F, "UM8673F",      NULL,           NULL,           NULL,           NULL,           {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   ON_BOARD,       0 },
377         {DEVID_UM8886A, "UM8886A",      NULL,           NULL,           NULL,           NULL,           {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   ON_BOARD,       0 },
378         {DEVID_UM8886BF,"UM8886BF",     NULL,           NULL,           NULL,           NULL,           {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   ON_BOARD,       0 },
379         {DEVID_HPT34X,  "HPT34X",       PCI_HPT34X,     NULL,           INIT_HPT34X,    NULL,           {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   NEVER_BOARD,    16 },
380         {DEVID_HPT366,  "HPT366",       PCI_HPT366,     ATA66_HPT366,   INIT_HPT366,    DMA_HPT366,     {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   OFF_BOARD,      240 },
381         {DEVID_ALI15X3, "ALI15X3",      PCI_ALI15X3,    ATA66_ALI15X3,  INIT_ALI15X3,   DMA_ALI15X3,    {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   ON_BOARD,       0 },
382         {DEVID_CY82C693,"CY82C693",     PCI_CY82C693,   NULL,           INIT_CY82C693,  NULL,           {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   ON_BOARD,       0 },
383         {DEVID_HINT,    "HINT_IDE",     NULL,           NULL,           NULL,           NULL,           {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   ON_BOARD,       0 },
384         {DEVID_CS5530,  "CS5530",       PCI_CS5530,     NULL,           INIT_CS5530,    NULL,           {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   ON_BOARD,       0 },
385         {DEVID_AMD7403, "AMD7403",      NULL,           NULL,           NULL,           NULL,           {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   ON_BOARD,       0 },
386         {DEVID_AMD7409, "AMD7409",      PCI_AMD7409,    ATA66_AMD7409,  INIT_AMD7409,   DMA_AMD7409,    {{0x40,0x01,0x01}, {0x40,0x02,0x02}},   ON_BOARD,       0 },
387         {DEVID_SLC90E66,"SLC90E66",     PCI_SLC90E66,   ATA66_SLC90E66, INIT_SLC90E66,  NULL,           {{0x41,0x80,0x80}, {0x43,0x80,0x80}},   ON_BOARD,       0 },
388         {DEVID_OSB4,    "ServerWorks OSB4",     PCI_OSB4,       ATA66_OSB4,     INIT_OSB4,      NULL,   {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   ON_BOARD,       0 },
389         {IDE_PCI_DEVID_NULL, "PCI_IDE", NULL,           NULL,           NULL,           NULL,           {{0x00,0x00,0x00}, {0x00,0x00,0x00}},   ON_BOARD,       0 }};
390
391 /*
392  * This allows offboard ide-pci cards the enable a BIOS, verify interrupt
393  * settings of split-mirror pci-config space, place chipset into init-mode,
394  * and/or preserve an interrupt if the card is not native ide support.
395  */
396 static unsigned int __init ide_special_settings (struct pci_dev *dev, const char *name)
397 {
398         switch(dev->device) {
399                 case PCI_DEVICE_ID_TTI_HPT366:
400                 case PCI_DEVICE_ID_PROMISE_20246:
401                 case PCI_DEVICE_ID_PROMISE_20262:
402                 case PCI_DEVICE_ID_PROMISE_20265:
403                 case PCI_DEVICE_ID_PROMISE_20267:
404                 case PCI_DEVICE_ID_ARTOP_ATP850UF:
405                 case PCI_DEVICE_ID_ARTOP_ATP860:
406                 case PCI_DEVICE_ID_ARTOP_ATP860R:
407                         return dev->irq;
408                 default:
409                         break;
410         }
411         return 0;
412 }
413
414 /*
415  * Match a PCI IDE port against an entry in ide_hwifs[],
416  * based on io_base port if possible.
417  */
418 static ide_hwif_t __init *ide_match_hwif (unsigned long io_base, byte bootable, const char *name)
419 {
420         int h;
421         ide_hwif_t *hwif;
422
423         /*
424          * Look for a hwif with matching io_base specified using
425          * parameters to ide_setup().
426          */
427         for (h = 0; h < MAX_HWIFS; ++h) {
428                 hwif = &ide_hwifs[h];
429                 if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) {
430                         if (hwif->chipset == ide_generic)
431                                 return hwif; /* a perfect match */
432                 }
433         }
434         /*
435          * Look for a hwif with matching io_base default value.
436          * If chipset is "ide_unknown", then claim that hwif slot.
437          * Otherwise, some other chipset has already claimed it..  :(
438          */
439         for (h = 0; h < MAX_HWIFS; ++h) {
440                 hwif = &ide_hwifs[h];
441                 if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) {
442                         if (hwif->chipset == ide_unknown)
443                                 return hwif; /* match */
444                         printk("%s: port 0x%04lx already claimed by %s\n", name, io_base, hwif->name);
445                         return NULL;    /* already claimed */
446                 }
447         }
448         /*
449          * Okay, there is no hwif matching our io_base,
450          * so we'll just claim an unassigned slot.
451          * Give preference to claiming other slots before claiming ide0/ide1,
452          * just in case there's another interface yet-to-be-scanned
453          * which uses ports 1f0/170 (the ide0/ide1 defaults).
454          *
455          * Unless there is a bootable card that does not use the standard
456          * ports 1f0/170 (the ide0/ide1 defaults). The (bootable) flag.
457          */
458         if (bootable) {
459                 for (h = 0; h < MAX_HWIFS; ++h) {
460                         hwif = &ide_hwifs[h];
461                         if (hwif->chipset == ide_unknown)
462                                 return hwif;    /* pick an unused entry */
463                 }
464         } else {
465                 for (h = 2; h < MAX_HWIFS; ++h) {
466                         hwif = ide_hwifs + h;
467                         if (hwif->chipset == ide_unknown)
468                                 return hwif;    /* pick an unused entry */
469                 }
470         }
471         for (h = 0; h < 2; ++h) {
472                 hwif = ide_hwifs + h;
473                 if (hwif->chipset == ide_unknown)
474                         return hwif;    /* pick an unused entry */
475         }
476         printk("%s: too many IDE interfaces, no room in table\n", name);
477         return NULL;
478 }
479
480 static int __init ide_setup_pci_baseregs (struct pci_dev *dev, const char *name)
481 {
482         byte reg, progif = 0;
483
484         /*
485          * Place both IDE interfaces into PCI "native" mode:
486          */
487         if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || (progif & 5) != 5) {
488                 if ((progif & 0xa) != 0xa) {
489                         printk("%s: device not capable of full native PCI mode\n", name);
490                         return 1;
491                 }
492                 printk("%s: placing both ports into native PCI mode\n", name);
493                 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
494                 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || (progif & 5) != 5) {
495                         printk("%s: rewrite of PROGIF failed, wanted 0x%04x, got 0x%04x\n", name, progif|5, progif);
496                         return 1;
497                 }
498         }
499         /*
500          * Setup base registers for IDE command/control spaces for each interface:
501          */
502         for (reg = 0; reg < 4; reg++) {
503                 struct resource *res = dev->resource + reg;
504                 if ((res->flags & IORESOURCE_IO) == 0)
505                         continue;
506                 if (!res->start) {
507                         printk("%s: Missing I/O address #%d\n", name, reg);
508                         return 1;
509                 }
510         }
511         return 0;
512 }
513
514 /*
515  * ide_setup_pci_device() looks at the primary/secondary interfaces
516  * on a PCI IDE device and, if they are enabled, prepares the IDE driver
517  * for use with them.  This generic code works for most PCI chipsets.
518  *
519  * One thing that is not standardized is the location of the
520  * primary/secondary interface "enable/disable" bits.  For chipsets that
521  * we "know" about, this information is in the ide_pci_device_t struct;
522  * for all other chipsets, we just assume both interfaces are enabled.
523  */
524 static void __init ide_setup_pci_device (struct pci_dev *dev, ide_pci_device_t *d)
525 {
526         unsigned int port, at_least_one_hwif_enabled = 0, autodma = 0, pciirq = 0;
527         unsigned short pcicmd = 0, tried_config = 0;
528         byte tmp = 0;
529         ide_hwif_t *hwif, *mate = NULL;
530         unsigned int class_rev;
531
532 #ifdef CONFIG_IDEDMA_AUTO
533         autodma = 1;
534 #endif
535
536         pci_enable_device(dev);
537
538 check_if_enabled:
539         if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) {
540                 printk("%s: error accessing PCI regs\n", d->name);
541                 return;
542         }
543         if (!(pcicmd & PCI_COMMAND_IO)) {       /* is device disabled? */
544                 /*
545                  * PnP BIOS was *supposed* to have set this device up for us,
546                  * but we can do it ourselves, so long as the BIOS has assigned an IRQ
547                  *  (or possibly the device is using a "legacy header" for IRQs).
548                  * Maybe the user deliberately *disabled* the device,
549                  * but we'll eventually ignore it again if no drives respond.
550                  */
551                 if (tried_config++
552                  || ide_setup_pci_baseregs(dev, d->name)
553                  || pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_IO)) {
554                         printk("%s: device disabled (BIOS)\n", d->name);
555                         return;
556                 }
557                 autodma = 0;    /* default DMA off if we had to configure it here */
558                 goto check_if_enabled;
559         }
560         if (tried_config)
561                 printk("%s: device enabled (Linux)\n", d->name);
562
563         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
564         class_rev &= 0xff;
565
566         if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X)) {
567                 /* see comments in hpt34x.c on why..... */
568                 char *chipset_names[] = {"HPT343", "HPT345"};
569                 strcpy(d->name, chipset_names[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0]);
570                 d->bootable = (pcicmd & PCI_COMMAND_MEMORY) ? OFF_BOARD : NEVER_BOARD;
571         }
572
573         printk("%s: chipset revision %d\n", d->name, class_rev);
574
575         /*
576          * Can we trust the reported IRQ?
577          */
578         pciirq = dev->irq;
579         
580         if (dev->class >> 8 == PCI_CLASS_STORAGE_RAID)
581         {
582                 /* By rights we want to ignore these, but the Promise Fastrak
583                    people have some strange ideas about proprietary so we have
584                    to act otherwise on those. The supertrak however we need
585                    to skip */
586                 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20265))
587                 {
588                         printk(KERN_INFO "ide: Found promise 20265 in RAID mode.\n");
589                         if(dev->bus->self && dev->bus->self->vendor == PCI_VENDOR_ID_INTEL &&
590                                 dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960)
591                         {
592                                 printk(KERN_INFO "ide: Skipping Promise PDC20265 attached to I2O RAID controller.\n");
593                                 return;
594                         }
595                 }
596                 /* Its attached to something else, just a random bridge. 
597                    Suspect a fastrak and fall through */
598         }
599         if ((dev->class & ~(0xfa)) != ((PCI_CLASS_STORAGE_IDE << 8) | 5)) {
600                 printk("%s: not 100%% native mode: will probe irqs later\n", d->name);
601                 /*
602                  * This allows offboard ide-pci cards the enable a BIOS,
603                  * verify interrupt settings of split-mirror pci-config
604                  * space, place chipset into init-mode, and/or preserve
605                  * an interrupt if the card is not native ide support.
606                  */
607                 pciirq = (d->init_chipset) ? d->init_chipset(dev, d->name) : ide_special_settings(dev, d->name);
608         } else if (tried_config) {
609                 printk("%s: will probe irqs later\n", d->name);
610                 pciirq = 0;
611         } else if (!pciirq) {
612                 printk("%s: bad irq (%d): will probe later\n", d->name, pciirq);
613                 pciirq = 0;
614         } else {
615                 if (d->init_chipset)
616                         (void) d->init_chipset(dev, d->name);
617 #ifdef __sparc__
618                 printk("%s: 100%% native mode on irq %s\n",
619                        d->name, __irq_itoa(pciirq));
620 #else
621                 printk("%s: 100%% native mode on irq %d\n", d->name, pciirq);
622 #endif
623         }
624
625         /*
626          * Set up the IDE ports
627          */
628         for (port = 0; port <= 1; ++port) {
629                 unsigned long base = 0, ctl = 0;
630                 ide_pci_enablebit_t *e = &(d->enablebits[port]);
631                 if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) || (tmp & e->mask) != e->val))
632                         continue;       /* port not enabled */
633                 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366) && (port) && (class_rev < 0x03))
634                         return;
635                 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE || (dev->class & (port ? 4 : 1)) != 0) {
636                         ctl  = dev->resource[(2*port)+1].start;
637                         base = dev->resource[2*port].start;
638                         if (!(ctl & PCI_BASE_ADDRESS_IO_MASK) ||
639                             !(base & PCI_BASE_ADDRESS_IO_MASK)) {
640                                 printk("%s: IO baseregs (BIOS) are reported as MEM, report to <andre@linux-ide.org>.\n", d->name);
641 #if 0
642                                 /* FIXME! This really should check that it really gets the IO/MEM part right! */
643                                 continue;
644 #endif
645                         }
646                 }
647                 if ((ctl && !base) || (base && !ctl)) {
648                         printk("%s: inconsistent baseregs (BIOS) for port %d, skipping\n", d->name, port);
649                         continue;
650                 }
651                 if (!ctl)
652                         ctl = port ? 0x374 : 0x3f4;     /* use default value */
653                 if (!base)
654                         base = port ? 0x170 : 0x1f0;    /* use default value */
655                 if ((hwif = ide_match_hwif(base, d->bootable, d->name)) == NULL)
656                         continue;       /* no room in ide_hwifs[] */
657                 if (hwif->io_ports[IDE_DATA_OFFSET] != base) {
658                         ide_init_hwif_ports(&hwif->hw, base, (ctl | 2), NULL);
659                         memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
660                         hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
661                 }
662                 hwif->chipset = ide_pci;
663                 hwif->pci_dev = dev;
664                 hwif->pci_devid = d->devid;
665                 hwif->channel = port;
666                 if (!hwif->irq)
667                         hwif->irq = pciirq;
668                 if (mate) {
669                         hwif->mate = mate;
670                         mate->mate = hwif;
671                         if (IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6210)) {
672                                 hwif->serialized = 1;
673                                 mate->serialized = 1;
674                         }
675                 }
676                 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886A) ||
677                     IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886BF) ||
678                     IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8673F)) {
679                         hwif->irq = hwif->channel ? 15 : 14;
680                         goto bypass_umc_dma;
681                 }
682                 if (hwif->udma_four) {
683                         printk("%s: ATA-66/100 forced bit set (WARNING)!!\n", d->name);
684                 } else {
685                         hwif->udma_four = (d->ata66_check) ? d->ata66_check(hwif) : 0;
686                 }
687 #ifdef CONFIG_BLK_DEV_IDEDMA
688                 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_SIS5513) ||
689                     IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6260) ||
690                     IDE_PCI_DEVID_EQ(d->devid, DEVID_PIIX4NX) ||
691                     IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X))
692                         autodma = 0;
693                 if (autodma)
694                         hwif->autodma = 1;
695                 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20246) ||
696                     IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20262) ||
697                     IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20265) ||
698                     IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20267) ||
699                     IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6210) ||
700                     IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6260) ||
701                     IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6260R) ||
702                     IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X) ||
703                     IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366) ||
704                     IDE_PCI_DEVID_EQ(d->devid, DEVID_CS5530) ||
705                     IDE_PCI_DEVID_EQ(d->devid, DEVID_CY82C693) ||
706                     IDE_PCI_DEVID_EQ(d->devid, DEVID_CMD646) ||
707                     IDE_PCI_DEVID_EQ(d->devid, DEVID_CMD648) ||
708                     IDE_PCI_DEVID_EQ(d->devid, DEVID_CMD649) ||
709                     IDE_PCI_DEVID_EQ(d->devid, DEVID_OSB4) ||
710                     ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 0x80))) {
711                         unsigned long dma_base = ide_get_or_set_dma_base(hwif, (!mate && d->extra) ? d->extra : 0, d->name);
712                         if (dma_base && !(pcicmd & PCI_COMMAND_MASTER)) {
713                                 /*
714                                  * Set up BM-DMA capability (PnP BIOS should have done this)
715                                  */
716                                 if (!IDE_PCI_DEVID_EQ(d->devid, DEVID_CS5530))
717                                         hwif->autodma = 0;      /* default DMA off if we had to configure it here */
718                                 (void) pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_MASTER);
719                                 if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) || !(pcicmd & PCI_COMMAND_MASTER)) {
720                                         printk("%s: %s error updating PCICMD\n", hwif->name, d->name);
721                                         dma_base = 0;
722                                 }
723                         }
724                         if (dma_base) {
725                                 if (d->dma_init) {
726                                         d->dma_init(hwif, dma_base);
727                                 } else {
728                                         ide_setup_dma(hwif, dma_base, 8);
729                                 }
730                         } else {
731                                 printk("%s: %s Bus-Master DMA disabled (BIOS)\n", hwif->name, d->name);
732                         }
733                 }
734 #endif  /* CONFIG_BLK_DEV_IDEDMA */
735 bypass_umc_dma:
736                 if (d->init_hwif)  /* Call chipset-specific routine for each enabled hwif */
737                         d->init_hwif(hwif);
738                 mate = hwif;
739                 at_least_one_hwif_enabled = 1;
740         }
741         if (!at_least_one_hwif_enabled)
742                 printk("%s: neither IDE port enabled (BIOS)\n", d->name);
743 }
744
745 static void __init hpt366_device_order_fixup (struct pci_dev *dev, ide_pci_device_t *d)
746 {
747         struct pci_dev *dev2 = NULL, *findev;
748         ide_pci_device_t *d2;
749         unsigned char pin1 = 0, pin2 = 0;
750         unsigned int class_rev;
751         char *chipset_names[] = {"HPT366", "HPT366", "HPT368", "HPT370", "HPT370A"};
752
753         if (PCI_FUNC(dev->devfn) & 1)
754                 return;
755
756         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
757         class_rev &= 0xff;
758
759         strcpy(d->name, chipset_names[class_rev]);
760
761         switch(class_rev) {
762                 case 4:
763                 case 3: printk("%s: IDE controller on PCI slot %s\n", d->name, dev->slot_name);
764                         ide_setup_pci_device(dev, d);
765                         return;
766                 default:        break;
767         }
768
769         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
770         pci_for_each_dev(findev) {
771                 if ((findev->vendor == dev->vendor) &&
772                     (findev->device == dev->device) &&
773                     ((findev->devfn - dev->devfn) == 1) &&
774                     (PCI_FUNC(findev->devfn) & 1)) {
775                         dev2 = findev;
776                         pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
777                         hpt363_shared_pin = (pin1 != pin2) ? 1 : 0;
778                         hpt363_shared_irq = (dev->irq == dev2->irq) ? 1 : 0;
779                         if (hpt363_shared_pin && hpt363_shared_irq) {
780                                 d->bootable = ON_BOARD;
781                                 printk("%s: onboard version of chipset, pin1=%d pin2=%d\n", d->name, pin1, pin2);
782                         }
783                         break;
784                 }
785         }
786         printk("%s: IDE controller on PCI slot %s\n", d->name, dev->slot_name);
787         ide_setup_pci_device(dev, d);
788         if (!dev2)
789                 return;
790         d2 = d;
791         printk("%s: IDE controller on PCI slot %s\n", d2->name, dev2->slot_name);
792         ide_setup_pci_device(dev2, d2);
793 }
794
795 /*
796  * ide_scan_pcibus() gets invoked at boot time from ide.c.
797  * It finds all PCI IDE controllers and calls ide_setup_pci_device for them.
798  */
799 void __init ide_scan_pcidev (struct pci_dev *dev)
800 {
801         ide_pci_devid_t         devid;
802         ide_pci_device_t        *d;
803
804         devid.vid = dev->vendor;
805         devid.did = dev->device;
806         for (d = ide_pci_chipsets; d->devid.vid && !IDE_PCI_DEVID_EQ(d->devid, devid); ++d);
807         if (d->init_hwif == IDE_IGNORE)
808                 printk("%s: ignored by ide_scan_pci_device() (uses own driver)\n", d->name);
809         else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_OPTI621V) && !(PCI_FUNC(dev->devfn) & 1))
810                 return;
811         else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_CY82C693) && (!(PCI_FUNC(dev->devfn) & 1) || !((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)))
812                 return; /* CY82C693 is more than only a IDE controller */
813         else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886A) && !(PCI_FUNC(dev->devfn) & 1))
814                 return; /* UM8886A/BF pair */
815         else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366))
816                 hpt366_device_order_fixup(dev, d);
817         else if (!IDE_PCI_DEVID_EQ(d->devid, IDE_PCI_DEVID_NULL) || (dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
818                 if (IDE_PCI_DEVID_EQ(d->devid, IDE_PCI_DEVID_NULL))
819                         printk("%s: unknown IDE controller on PCI slot %s, VID=%04x, DID=%04x\n",
820                                d->name, dev->slot_name, devid.vid, devid.did);
821                 else
822                         printk("%s: IDE controller on PCI slot %s\n", d->name, dev->slot_name);
823                 ide_setup_pci_device(dev, d);
824         }
825 }
826
827 void __init ide_scan_pcibus (int scan_direction)
828 {
829         struct pci_dev *dev;
830
831         if (!scan_direction) {
832                 pci_for_each_dev(dev) {
833                         ide_scan_pcidev(dev);
834                 }
835         } else {
836                 pci_for_each_dev_reverse(dev) {
837                         ide_scan_pcidev(dev);
838                 }
839         }
840 }