v2.4.8 -> v2.4.8.1
[opensuse:kernel.git] / drivers / char / drm / radeon_cp.c
1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
2  *
3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5  * All Rights Reserved.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the "Software"),
9  * to deal in the Software without restriction, including without limitation
10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11  * and/or sell copies of the Software, and to permit persons to whom the
12  * Software is furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice (including the next
15  * paragraph) shall be included in all copies or substantial portions of the
16  * Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24  * DEALINGS IN THE SOFTWARE.
25  *
26  * Authors:
27  *    Kevin E. Martin <martin@valinux.com>
28  *    Gareth Hughes <gareth@valinux.com>
29  */
30
31 #define __NO_VERSION__
32 #include "radeon.h"
33 #include "drmP.h"
34 #include "radeon_drv.h"
35
36 #include <linux/interrupt.h>    /* For task queue support */
37 #include <linux/delay.h>
38
39 #define RADEON_FIFO_DEBUG       0
40
41 #if defined(__alpha__)
42 # define PCIGART_ENABLED
43 #else
44 # undef PCIGART_ENABLED
45 #endif
46
47
48 /* CP microcode (from ATI) */
49 static u32 radeon_cp_microcode[][2] = {
50         { 0x21007000, 0000000000 },
51         { 0x20007000, 0000000000 },
52         { 0x000000b4, 0x00000004 },
53         { 0x000000b8, 0x00000004 },
54         { 0x6f5b4d4c, 0000000000 },
55         { 0x4c4c427f, 0000000000 },
56         { 0x5b568a92, 0000000000 },
57         { 0x4ca09c6d, 0000000000 },
58         { 0xad4c4c4c, 0000000000 },
59         { 0x4ce1af3d, 0000000000 },
60         { 0xd8afafaf, 0000000000 },
61         { 0xd64c4cdc, 0000000000 },
62         { 0x4cd10d10, 0000000000 },
63         { 0x000f0000, 0x00000016 },
64         { 0x362f242d, 0000000000 },
65         { 0x00000012, 0x00000004 },
66         { 0x000f0000, 0x00000016 },
67         { 0x362f282d, 0000000000 },
68         { 0x000380e7, 0x00000002 },
69         { 0x04002c97, 0x00000002 },
70         { 0x000f0001, 0x00000016 },
71         { 0x333a3730, 0000000000 },
72         { 0x000077ef, 0x00000002 },
73         { 0x00061000, 0x00000002 },
74         { 0x00000021, 0x0000001a },
75         { 0x00004000, 0x0000001e },
76         { 0x00061000, 0x00000002 },
77         { 0x00000021, 0x0000001a },
78         { 0x00004000, 0x0000001e },
79         { 0x00061000, 0x00000002 },
80         { 0x00000021, 0x0000001a },
81         { 0x00004000, 0x0000001e },
82         { 0x00000017, 0x00000004 },
83         { 0x0003802b, 0x00000002 },
84         { 0x040067e0, 0x00000002 },
85         { 0x00000017, 0x00000004 },
86         { 0x000077e0, 0x00000002 },
87         { 0x00065000, 0x00000002 },
88         { 0x000037e1, 0x00000002 },
89         { 0x040067e1, 0x00000006 },
90         { 0x000077e0, 0x00000002 },
91         { 0x000077e1, 0x00000002 },
92         { 0x000077e1, 0x00000006 },
93         { 0xffffffff, 0000000000 },
94         { 0x10000000, 0000000000 },
95         { 0x0003802b, 0x00000002 },
96         { 0x040067e0, 0x00000006 },
97         { 0x00007675, 0x00000002 },
98         { 0x00007676, 0x00000002 },
99         { 0x00007677, 0x00000002 },
100         { 0x00007678, 0x00000006 },
101         { 0x0003802c, 0x00000002 },
102         { 0x04002676, 0x00000002 },
103         { 0x00007677, 0x00000002 },
104         { 0x00007678, 0x00000006 },
105         { 0x0000002f, 0x00000018 },
106         { 0x0000002f, 0x00000018 },
107         { 0000000000, 0x00000006 },
108         { 0x00000030, 0x00000018 },
109         { 0x00000030, 0x00000018 },
110         { 0000000000, 0x00000006 },
111         { 0x01605000, 0x00000002 },
112         { 0x00065000, 0x00000002 },
113         { 0x00098000, 0x00000002 },
114         { 0x00061000, 0x00000002 },
115         { 0x64c0603e, 0x00000004 },
116         { 0x000380e6, 0x00000002 },
117         { 0x040025c5, 0x00000002 },
118         { 0x00080000, 0x00000016 },
119         { 0000000000, 0000000000 },
120         { 0x0400251d, 0x00000002 },
121         { 0x00007580, 0x00000002 },
122         { 0x00067581, 0x00000002 },
123         { 0x04002580, 0x00000002 },
124         { 0x00067581, 0x00000002 },
125         { 0x00000049, 0x00000004 },
126         { 0x00005000, 0000000000 },
127         { 0x000380e6, 0x00000002 },
128         { 0x040025c5, 0x00000002 },
129         { 0x00061000, 0x00000002 },
130         { 0x0000750e, 0x00000002 },
131         { 0x00019000, 0x00000002 },
132         { 0x00011055, 0x00000014 },
133         { 0x00000055, 0x00000012 },
134         { 0x0400250f, 0x00000002 },
135         { 0x0000504f, 0x00000004 },
136         { 0x000380e6, 0x00000002 },
137         { 0x040025c5, 0x00000002 },
138         { 0x00007565, 0x00000002 },
139         { 0x00007566, 0x00000002 },
140         { 0x00000058, 0x00000004 },
141         { 0x000380e6, 0x00000002 },
142         { 0x040025c5, 0x00000002 },
143         { 0x01e655b4, 0x00000002 },
144         { 0x4401b0e4, 0x00000002 },
145         { 0x01c110e4, 0x00000002 },
146         { 0x26667066, 0x00000018 },
147         { 0x040c2565, 0x00000002 },
148         { 0x00000066, 0x00000018 },
149         { 0x04002564, 0x00000002 },
150         { 0x00007566, 0x00000002 },
151         { 0x0000005d, 0x00000004 },
152         { 0x00401069, 0x00000008 },
153         { 0x00101000, 0x00000002 },
154         { 0x000d80ff, 0x00000002 },
155         { 0x0080006c, 0x00000008 },
156         { 0x000f9000, 0x00000002 },
157         { 0x000e00ff, 0x00000002 },
158         { 0000000000, 0x00000006 },
159         { 0x0000008f, 0x00000018 },
160         { 0x0000005b, 0x00000004 },
161         { 0x000380e6, 0x00000002 },
162         { 0x040025c5, 0x00000002 },
163         { 0x00007576, 0x00000002 },
164         { 0x00065000, 0x00000002 },
165         { 0x00009000, 0x00000002 },
166         { 0x00041000, 0x00000002 },
167         { 0x0c00350e, 0x00000002 },
168         { 0x00049000, 0x00000002 },
169         { 0x00051000, 0x00000002 },
170         { 0x01e785f8, 0x00000002 },
171         { 0x00200000, 0x00000002 },
172         { 0x0060007e, 0x0000000c },
173         { 0x00007563, 0x00000002 },
174         { 0x006075f0, 0x00000021 },
175         { 0x20007073, 0x00000004 },
176         { 0x00005073, 0x00000004 },
177         { 0x000380e6, 0x00000002 },
178         { 0x040025c5, 0x00000002 },
179         { 0x00007576, 0x00000002 },
180         { 0x00007577, 0x00000002 },
181         { 0x0000750e, 0x00000002 },
182         { 0x0000750f, 0x00000002 },
183         { 0x00a05000, 0x00000002 },
184         { 0x00600083, 0x0000000c },
185         { 0x006075f0, 0x00000021 },
186         { 0x000075f8, 0x00000002 },
187         { 0x00000083, 0x00000004 },
188         { 0x000a750e, 0x00000002 },
189         { 0x000380e6, 0x00000002 },
190         { 0x040025c5, 0x00000002 },
191         { 0x0020750f, 0x00000002 },
192         { 0x00600086, 0x00000004 },
193         { 0x00007570, 0x00000002 },
194         { 0x00007571, 0x00000002 },
195         { 0x00007572, 0x00000006 },
196         { 0x000380e6, 0x00000002 },
197         { 0x040025c5, 0x00000002 },
198         { 0x00005000, 0x00000002 },
199         { 0x00a05000, 0x00000002 },
200         { 0x00007568, 0x00000002 },
201         { 0x00061000, 0x00000002 },
202         { 0x00000095, 0x0000000c },
203         { 0x00058000, 0x00000002 },
204         { 0x0c607562, 0x00000002 },
205         { 0x00000097, 0x00000004 },
206         { 0x000380e6, 0x00000002 },
207         { 0x040025c5, 0x00000002 },
208         { 0x00600096, 0x00000004 },
209         { 0x400070e5, 0000000000 },
210         { 0x000380e6, 0x00000002 },
211         { 0x040025c5, 0x00000002 },
212         { 0x000380e5, 0x00000002 },
213         { 0x000000a8, 0x0000001c },
214         { 0x000650aa, 0x00000018 },
215         { 0x040025bb, 0x00000002 },
216         { 0x000610ab, 0x00000018 },
217         { 0x040075bc, 0000000000 },
218         { 0x000075bb, 0x00000002 },
219         { 0x000075bc, 0000000000 },
220         { 0x00090000, 0x00000006 },
221         { 0x00090000, 0x00000002 },
222         { 0x000d8002, 0x00000006 },
223         { 0x00007832, 0x00000002 },
224         { 0x00005000, 0x00000002 },
225         { 0x000380e7, 0x00000002 },
226         { 0x04002c97, 0x00000002 },
227         { 0x00007820, 0x00000002 },
228         { 0x00007821, 0x00000002 },
229         { 0x00007800, 0000000000 },
230         { 0x01200000, 0x00000002 },
231         { 0x20077000, 0x00000002 },
232         { 0x01200000, 0x00000002 },
233         { 0x20007000, 0x00000002 },
234         { 0x00061000, 0x00000002 },
235         { 0x0120751b, 0x00000002 },
236         { 0x8040750a, 0x00000002 },
237         { 0x8040750b, 0x00000002 },
238         { 0x00110000, 0x00000002 },
239         { 0x000380e5, 0x00000002 },
240         { 0x000000c6, 0x0000001c },
241         { 0x000610ab, 0x00000018 },
242         { 0x844075bd, 0x00000002 },
243         { 0x000610aa, 0x00000018 },
244         { 0x840075bb, 0x00000002 },
245         { 0x000610ab, 0x00000018 },
246         { 0x844075bc, 0x00000002 },
247         { 0x000000c9, 0x00000004 },
248         { 0x804075bd, 0x00000002 },
249         { 0x800075bb, 0x00000002 },
250         { 0x804075bc, 0x00000002 },
251         { 0x00108000, 0x00000002 },
252         { 0x01400000, 0x00000002 },
253         { 0x006000cd, 0x0000000c },
254         { 0x20c07000, 0x00000020 },
255         { 0x000000cf, 0x00000012 },
256         { 0x00800000, 0x00000006 },
257         { 0x0080751d, 0x00000006 },
258         { 0000000000, 0000000000 },
259         { 0x0000775c, 0x00000002 },
260         { 0x00a05000, 0x00000002 },
261         { 0x00661000, 0x00000002 },
262         { 0x0460275d, 0x00000020 },
263         { 0x00004000, 0000000000 },
264         { 0x01e00830, 0x00000002 },
265         { 0x21007000, 0000000000 },
266         { 0x6464614d, 0000000000 },
267         { 0x69687420, 0000000000 },
268         { 0x00000073, 0000000000 },
269         { 0000000000, 0000000000 },
270         { 0x00005000, 0x00000002 },
271         { 0x000380d0, 0x00000002 },
272         { 0x040025e0, 0x00000002 },
273         { 0x000075e1, 0000000000 },
274         { 0x00000001, 0000000000 },
275         { 0x000380e0, 0x00000002 },
276         { 0x04002394, 0x00000002 },
277         { 0x00005000, 0000000000 },
278         { 0000000000, 0000000000 },
279         { 0000000000, 0000000000 },
280         { 0x00000008, 0000000000 },
281         { 0x00000004, 0000000000 },
282         { 0000000000, 0000000000 },
283         { 0000000000, 0000000000 },
284         { 0000000000, 0000000000 },
285         { 0000000000, 0000000000 },
286         { 0000000000, 0000000000 },
287         { 0000000000, 0000000000 },
288         { 0000000000, 0000000000 },
289         { 0000000000, 0000000000 },
290         { 0000000000, 0000000000 },
291         { 0000000000, 0000000000 },
292         { 0000000000, 0000000000 },
293         { 0000000000, 0000000000 },
294         { 0000000000, 0000000000 },
295         { 0000000000, 0000000000 },
296         { 0000000000, 0000000000 },
297         { 0000000000, 0000000000 },
298         { 0000000000, 0000000000 },
299         { 0000000000, 0000000000 },
300         { 0000000000, 0000000000 },
301         { 0000000000, 0000000000 },
302         { 0000000000, 0000000000 },
303         { 0000000000, 0000000000 },
304         { 0000000000, 0000000000 },
305         { 0000000000, 0000000000 },
306 };
307
308
309 int RADEON_READ_PLL(drm_device_t *dev, int addr)
310 {
311         drm_radeon_private_t *dev_priv = dev->dev_private;
312
313         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
314         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
315 }
316
317 #if RADEON_FIFO_DEBUG
318 static void radeon_status( drm_radeon_private_t *dev_priv )
319 {
320         printk( "%s:\n", __FUNCTION__ );
321         printk( "RBBM_STATUS = 0x%08x\n",
322                 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
323         printk( "CP_RB_RTPR = 0x%08x\n",
324                 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
325         printk( "CP_RB_WTPR = 0x%08x\n",
326                 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
327         printk( "AIC_CNTL = 0x%08x\n",
328                 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
329         printk( "AIC_STAT = 0x%08x\n",
330                 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
331         printk( "AIC_PT_BASE = 0x%08x\n",
332                 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
333         printk( "TLB_ADDR = 0x%08x\n",
334                 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
335         printk( "TLB_DATA = 0x%08x\n",
336                 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
337 }
338 #endif
339
340
341 /* ================================================================
342  * Engine, FIFO control
343  */
344
345 static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
346 {
347         u32 tmp;
348         int i;
349
350         tmp  = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
351         tmp |= RADEON_RB2D_DC_FLUSH_ALL;
352         RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
353
354         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
355                 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
356                        & RADEON_RB2D_DC_BUSY) ) {
357                         return 0;
358                 }
359                 udelay( 1 );
360         }
361
362 #if RADEON_FIFO_DEBUG
363         DRM_ERROR( "failed!\n" );
364         radeon_status( dev_priv );
365 #endif
366         return -EBUSY;
367 }
368
369 static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
370                                     int entries )
371 {
372         int i;
373
374         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
375                 int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
376                               & RADEON_RBBM_FIFOCNT_MASK );
377                 if ( slots >= entries ) return 0;
378                 udelay( 1 );
379         }
380
381 #if RADEON_FIFO_DEBUG
382         DRM_ERROR( "failed!\n" );
383         radeon_status( dev_priv );
384 #endif
385         return -EBUSY;
386 }
387
388 static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
389 {
390         int i, ret;
391
392         ret = radeon_do_wait_for_fifo( dev_priv, 64 );
393         if ( ret < 0 ) return ret;
394
395         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
396                 if ( !(RADEON_READ( RADEON_RBBM_STATUS )
397                        & RADEON_RBBM_ACTIVE) ) {
398                         radeon_do_pixcache_flush( dev_priv );
399                         return 0;
400                 }
401                 udelay( 1 );
402         }
403
404 #if RADEON_FIFO_DEBUG
405         DRM_ERROR( "failed!\n" );
406         radeon_status( dev_priv );
407 #endif
408         return -EBUSY;
409 }
410
411
412 /* ================================================================
413  * CP control, initialization
414  */
415
416 /* Load the microcode for the CP */
417 static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
418 {
419         int i;
420         DRM_DEBUG( "%s\n", __FUNCTION__ );
421
422         radeon_do_wait_for_idle( dev_priv );
423
424         RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
425         for ( i = 0 ; i < 256 ; i++ ) {
426                 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
427                               radeon_cp_microcode[i][1] );
428                 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
429                               radeon_cp_microcode[i][0] );
430         }
431 }
432
433 /* Flush any pending commands to the CP.  This should only be used just
434  * prior to a wait for idle, as it informs the engine that the command
435  * stream is ending.
436  */
437 static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
438 {
439         DRM_DEBUG( "%s\n", __FUNCTION__ );
440 #if 0
441         u32 tmp;
442
443         tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
444         RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
445 #endif
446 }
447
448 /* Wait for the CP to go idle.
449  */
450 int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
451 {
452         RING_LOCALS;
453         DRM_DEBUG( "%s\n", __FUNCTION__ );
454
455         BEGIN_RING( 6 );
456
457         RADEON_PURGE_CACHE();
458         RADEON_PURGE_ZCACHE();
459         RADEON_WAIT_UNTIL_IDLE();
460
461         ADVANCE_RING();
462
463         return radeon_do_wait_for_idle( dev_priv );
464 }
465
466 /* Start the Command Processor.
467  */
468 static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
469 {
470         RING_LOCALS;
471         DRM_DEBUG( "%s\n", __FUNCTION__ );
472
473         radeon_do_wait_for_idle( dev_priv );
474
475         RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
476
477         dev_priv->cp_running = 1;
478
479         BEGIN_RING( 6 );
480
481         RADEON_PURGE_CACHE();
482         RADEON_PURGE_ZCACHE();
483         RADEON_WAIT_UNTIL_IDLE();
484
485         ADVANCE_RING();
486 }
487
488 /* Reset the Command Processor.  This will not flush any pending
489  * commands, so you must wait for the CP command stream to complete
490  * before calling this routine.
491  */
492 static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
493 {
494         u32 cur_read_ptr;
495         DRM_DEBUG( "%s\n", __FUNCTION__ );
496
497         cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
498         RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
499         *dev_priv->ring.head = cur_read_ptr;
500         dev_priv->ring.tail = cur_read_ptr;
501 }
502
503 /* Stop the Command Processor.  This will not flush any pending
504  * commands, so you must flush the command stream and wait for the CP
505  * to go idle before calling this routine.
506  */
507 static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
508 {
509         DRM_DEBUG( "%s\n", __FUNCTION__ );
510
511         RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
512
513         dev_priv->cp_running = 0;
514 }
515
516 /* Reset the engine.  This will stop the CP if it is running.
517  */
518 static int radeon_do_engine_reset( drm_device_t *dev )
519 {
520         drm_radeon_private_t *dev_priv = dev->dev_private;
521         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
522         DRM_DEBUG( "%s\n", __FUNCTION__ );
523
524         radeon_do_pixcache_flush( dev_priv );
525
526         clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
527         mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
528
529         RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
530                                               RADEON_FORCEON_MCLKA |
531                                               RADEON_FORCEON_MCLKB |
532                                               RADEON_FORCEON_YCLKA |
533                                               RADEON_FORCEON_YCLKB |
534                                               RADEON_FORCEON_MC |
535                                               RADEON_FORCEON_AIC ) );
536
537         rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
538
539         RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
540                                                 RADEON_SOFT_RESET_CP |
541                                                 RADEON_SOFT_RESET_HI |
542                                                 RADEON_SOFT_RESET_SE |
543                                                 RADEON_SOFT_RESET_RE |
544                                                 RADEON_SOFT_RESET_PP |
545                                                 RADEON_SOFT_RESET_E2 |
546                                                 RADEON_SOFT_RESET_RB |
547                                                 RADEON_SOFT_RESET_HDP ) );
548         RADEON_READ( RADEON_RBBM_SOFT_RESET );
549         RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
550                                                 ~( RADEON_SOFT_RESET_CP |
551                                                    RADEON_SOFT_RESET_HI |
552                                                    RADEON_SOFT_RESET_SE |
553                                                    RADEON_SOFT_RESET_RE |
554                                                    RADEON_SOFT_RESET_PP |
555                                                    RADEON_SOFT_RESET_E2 |
556                                                    RADEON_SOFT_RESET_RB |
557                                                    RADEON_SOFT_RESET_HDP ) ) );
558         RADEON_READ( RADEON_RBBM_SOFT_RESET );
559
560
561         RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
562         RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
563         RADEON_WRITE( RADEON_RBBM_SOFT_RESET,  rbbm_soft_reset );
564
565         /* Reset the CP ring */
566         radeon_do_cp_reset( dev_priv );
567
568         /* The CP is no longer running after an engine reset */
569         dev_priv->cp_running = 0;
570
571         /* Reset any pending vertex, indirect buffers */
572         radeon_freelist_reset( dev );
573
574         return 0;
575 }
576
577 static void radeon_cp_init_ring_buffer( drm_device_t *dev,
578                                         drm_radeon_private_t *dev_priv )
579 {
580         u32 ring_start, cur_read_ptr;
581         u32 tmp;
582
583         /* Initialize the memory controller */
584         RADEON_WRITE( RADEON_MC_FB_LOCATION,
585                       (dev_priv->agp_vm_start - 1) & 0xffff0000 );
586
587         if ( !dev_priv->is_pci ) {
588                 RADEON_WRITE( RADEON_MC_AGP_LOCATION,
589                               (((dev_priv->agp_vm_start - 1 +
590                                  dev_priv->agp_size) & 0xffff0000) |
591                                (dev_priv->agp_vm_start >> 16)) );
592         }
593
594 #if __REALLY_HAVE_AGP
595         if ( !dev_priv->is_pci )
596                 ring_start = (dev_priv->cp_ring->offset
597                               - dev->agp->base
598                               + dev_priv->agp_vm_start);
599        else
600 #endif
601                 ring_start = (dev_priv->cp_ring->offset
602                               - dev->sg->handle
603                               + dev_priv->agp_vm_start);
604
605         RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
606
607         /* Set the write pointer delay */
608         RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
609
610         /* Initialize the ring buffer's read and write pointers */
611         cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
612         RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
613         *dev_priv->ring.head = cur_read_ptr;
614         dev_priv->ring.tail = cur_read_ptr;
615
616         if ( !dev_priv->is_pci ) {
617                 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
618                               dev_priv->ring_rptr->offset );
619         } else {
620                 drm_sg_mem_t *entry = dev->sg;
621                 unsigned long tmp_ofs, page_ofs;
622
623                 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
624                 page_ofs = tmp_ofs >> PAGE_SHIFT;
625
626                 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
627                               page_to_bus(entry->pagelist[page_ofs]));
628
629                 DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n",
630                            page_to_bus(entry->pagelist[page_ofs]),
631                            entry->handle + tmp_ofs );
632         }
633
634         /* Set ring buffer size */
635         RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
636
637         radeon_do_wait_for_idle( dev_priv );
638
639         /* Turn on bus mastering */
640         tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
641         RADEON_WRITE( RADEON_BUS_CNTL, tmp );
642
643         /* Sync everything up */
644         RADEON_WRITE( RADEON_ISYNC_CNTL,
645                       (RADEON_ISYNC_ANY2D_IDLE3D |
646                        RADEON_ISYNC_ANY3D_IDLE2D |
647                        RADEON_ISYNC_WAIT_IDLEGUI |
648                        RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
649 }
650
651 static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
652 {
653         drm_radeon_private_t *dev_priv;
654         struct list_head *list;
655         u32 tmp;
656         DRM_DEBUG( "%s\n", __FUNCTION__ );
657
658         dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
659         if ( dev_priv == NULL )
660                 return -ENOMEM;
661
662         memset( dev_priv, 0, sizeof(drm_radeon_private_t) );
663
664         dev_priv->is_pci = init->is_pci;
665
666 #if !defined(PCIGART_ENABLED)
667         /* PCI support is not 100% working, so we disable it here.
668          */
669         if ( dev_priv->is_pci ) {
670                 DRM_ERROR( "PCI GART not yet supported for Radeon!\n" );
671                 dev->dev_private = (void *)dev_priv;
672                 radeon_do_cleanup_cp(dev);
673                 return -EINVAL;
674         }
675 #endif
676
677         if ( dev_priv->is_pci && !dev->sg ) {
678                 DRM_ERROR( "PCI GART memory not allocated!\n" );
679                 dev->dev_private = (void *)dev_priv;
680                 radeon_do_cleanup_cp(dev);
681                 return -EINVAL;
682         }
683
684         dev_priv->usec_timeout = init->usec_timeout;
685         if ( dev_priv->usec_timeout < 1 ||
686              dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
687                 DRM_DEBUG( "TIMEOUT problem!\n" );
688                 dev->dev_private = (void *)dev_priv;
689                 radeon_do_cleanup_cp(dev);
690                 return -EINVAL;
691         }
692
693         dev_priv->cp_mode = init->cp_mode;
694
695         /* Simple idle check.
696          */
697         atomic_set( &dev_priv->idle_count, 0 );
698
699         /* We don't support anything other than bus-mastering ring mode,
700          * but the ring can be in either AGP or PCI space for the ring
701          * read pointer.
702          */
703         if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
704              ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
705                 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
706                 dev->dev_private = (void *)dev_priv;
707                 radeon_do_cleanup_cp(dev);
708                 return -EINVAL;
709         }
710
711         switch ( init->fb_bpp ) {
712         case 16:
713                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
714                 break;
715         case 32:
716         default:
717                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
718                 break;
719         }
720         dev_priv->front_offset  = init->front_offset;
721         dev_priv->front_pitch   = init->front_pitch;
722         dev_priv->back_offset   = init->back_offset;
723         dev_priv->back_pitch    = init->back_pitch;
724
725         switch ( init->depth_bpp ) {
726         case 16:
727                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
728                 break;
729         case 32:
730         default:
731                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
732                 break;
733         }
734         dev_priv->depth_offset  = init->depth_offset;
735         dev_priv->depth_pitch   = init->depth_pitch;
736
737         dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
738                                         (dev_priv->front_offset >> 10));
739         dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
740                                        (dev_priv->back_offset >> 10));
741         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
742                                         (dev_priv->depth_offset >> 10));
743
744         /* Hardware state for depth clears.  Remove this if/when we no
745          * longer clear the depth buffer with a 3D rectangle.  Hard-code
746          * all values to prevent unwanted 3D state from slipping through
747          * and screwing with the clear operation.
748          */
749         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
750                                            RADEON_Z_ENABLE |
751                                            (dev_priv->color_fmt << 10) |
752                                            RADEON_ZBLOCK16);
753
754         dev_priv->depth_clear.rb3d_zstencilcntl = (dev_priv->depth_fmt |
755                                                    RADEON_Z_TEST_ALWAYS |
756                                                    RADEON_STENCIL_TEST_ALWAYS |
757                                                    RADEON_STENCIL_S_FAIL_KEEP |
758                                                    RADEON_STENCIL_ZPASS_KEEP |
759                                                    RADEON_STENCIL_ZFAIL_KEEP |
760                                                    RADEON_Z_WRITE_ENABLE);
761
762         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
763                                          RADEON_BFACE_SOLID |
764                                          RADEON_FFACE_SOLID |
765                                          RADEON_FLAT_SHADE_VTX_LAST |
766                                          RADEON_DIFFUSE_SHADE_FLAT |
767                                          RADEON_ALPHA_SHADE_FLAT |
768                                          RADEON_SPECULAR_SHADE_FLAT |
769                                          RADEON_FOG_SHADE_FLAT |
770                                          RADEON_VTX_PIX_CENTER_OGL |
771                                          RADEON_ROUND_MODE_TRUNC |
772                                          RADEON_ROUND_PREC_8TH_PIX);
773
774         list_for_each(list, &dev->maplist->head) {
775                 drm_map_list_t *r_list = (drm_map_list_t *)list;
776                 if( r_list->map &&
777                     r_list->map->type == _DRM_SHM &&
778                     r_list->map->flags & _DRM_CONTAINS_LOCK ) {
779                         dev_priv->sarea = r_list->map;
780                         break;
781                 }
782         }
783         if(!dev_priv->sarea) {
784                 DRM_ERROR("could not find sarea!\n");
785                 dev->dev_private = (void *)dev_priv;
786                 radeon_do_cleanup_cp(dev);
787                 return -EINVAL;
788         }
789
790         DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
791         if(!dev_priv->fb) {
792                 DRM_ERROR("could not find framebuffer!\n");
793                 dev->dev_private = (void *)dev_priv;
794                 radeon_do_cleanup_cp(dev);
795                 return -EINVAL;
796         }
797         DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
798         if(!dev_priv->mmio) {
799                 DRM_ERROR("could not find mmio region!\n");
800                 dev->dev_private = (void *)dev_priv;
801                 radeon_do_cleanup_cp(dev);
802                 return -EINVAL;
803         }
804         DRM_FIND_MAP( dev_priv->cp_ring, init->ring_offset );
805         if(!dev_priv->cp_ring) {
806                 DRM_ERROR("could not find cp ring region!\n");
807                 dev->dev_private = (void *)dev_priv;
808                 radeon_do_cleanup_cp(dev);
809                 return -EINVAL;
810         }
811         DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
812         if(!dev_priv->ring_rptr) {
813                 DRM_ERROR("could not find ring read pointer!\n");
814                 dev->dev_private = (void *)dev_priv;
815                 radeon_do_cleanup_cp(dev);
816                 return -EINVAL;
817         }
818         DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
819         if(!dev_priv->buffers) {
820                 DRM_ERROR("could not find dma buffer region!\n");
821                 dev->dev_private = (void *)dev_priv;
822                 radeon_do_cleanup_cp(dev);
823                 return -EINVAL;
824         }
825
826         if ( !dev_priv->is_pci ) {
827                 DRM_FIND_MAP( dev_priv->agp_textures,
828                               init->agp_textures_offset );
829                 if(!dev_priv->agp_textures) {
830                         DRM_ERROR("could not find agp texture region!\n");
831                         dev->dev_private = (void *)dev_priv;
832                         radeon_do_cleanup_cp(dev);
833                         return -EINVAL;
834                 }
835         }
836
837         dev_priv->sarea_priv =
838                 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
839                                        init->sarea_priv_offset);
840
841         if ( !dev_priv->is_pci ) {
842                 DRM_IOREMAP( dev_priv->cp_ring );
843                 DRM_IOREMAP( dev_priv->ring_rptr );
844                 DRM_IOREMAP( dev_priv->buffers );
845                 if(!dev_priv->cp_ring->handle ||
846                    !dev_priv->ring_rptr->handle ||
847                    !dev_priv->buffers->handle) {
848                         DRM_ERROR("could not find ioremap agp regions!\n");
849                         dev->dev_private = (void *)dev_priv;
850                         radeon_do_cleanup_cp(dev);
851                         return -EINVAL;
852                 }
853         } else {
854                 dev_priv->cp_ring->handle =
855                         (void *)dev_priv->cp_ring->offset;
856                 dev_priv->ring_rptr->handle =
857                         (void *)dev_priv->ring_rptr->offset;
858                 dev_priv->buffers->handle = (void *)dev_priv->buffers->offset;
859
860                 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
861                            dev_priv->cp_ring->handle );
862                 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
863                            dev_priv->ring_rptr->handle );
864                 DRM_DEBUG( "dev_priv->buffers->handle %p\n",
865                            dev_priv->buffers->handle );
866         }
867
868
869         dev_priv->agp_size = init->agp_size;
870         dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
871 #if __REALLY_HAVE_AGP
872         if ( !dev_priv->is_pci )
873                 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
874                                                 - dev->agp->base
875                                                 + dev_priv->agp_vm_start);
876         else
877 #endif
878                 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
879                                                 - dev->sg->handle
880                                                 + dev_priv->agp_vm_start);
881
882         DRM_DEBUG( "dev_priv->agp_size %d\n",
883                    dev_priv->agp_size );
884         DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
885                    dev_priv->agp_vm_start );
886         DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
887                    dev_priv->agp_buffers_offset );
888
889         dev_priv->ring.head = ((__volatile__ u32 *)
890                                dev_priv->ring_rptr->handle);
891
892         dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
893         dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
894                               + init->ring_size / sizeof(u32));
895         dev_priv->ring.size = init->ring_size;
896         dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
897
898         dev_priv->ring.tail_mask =
899                 (dev_priv->ring.size / sizeof(u32)) - 1;
900
901         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
902
903 #if 0
904         /* Initialize the scratch register pointer.  This will cause
905          * the scratch register values to be written out to memory
906          * whenever they are updated.
907          * FIXME: This doesn't quite work yet, so we're disabling it
908          * for the release.
909          */
910         RADEON_WRITE( RADEON_SCRATCH_ADDR, (dev_priv->ring_rptr->offset +
911                                             RADEON_SCRATCH_REG_OFFSET) );
912         RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
913 #endif
914
915         dev_priv->scratch = ((__volatile__ u32 *)
916                              dev_priv->ring_rptr->handle +
917                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
918
919         dev_priv->sarea_priv->last_frame = 0;
920         RADEON_WRITE( RADEON_LAST_FRAME_REG,
921                       dev_priv->sarea_priv->last_frame );
922
923         dev_priv->sarea_priv->last_dispatch = 0;
924         RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
925                       dev_priv->sarea_priv->last_dispatch );
926
927         dev_priv->sarea_priv->last_clear = 0;
928         RADEON_WRITE( RADEON_LAST_CLEAR_REG,
929                       dev_priv->sarea_priv->last_clear );
930
931         if ( dev_priv->is_pci ) {
932                 dev_priv->phys_pci_gart = DRM(ati_pcigart_init)( dev );
933                 if ( !dev_priv->phys_pci_gart ) {
934                         DRM_ERROR( "failed to init PCI GART!\n" );
935                         dev->dev_private = (void *)dev_priv;
936                         radeon_do_cleanup_cp(dev);
937                         return -ENOMEM;
938                 }
939                 /* Turn on PCI GART
940                  */
941                 tmp = RADEON_READ( RADEON_AIC_CNTL )
942                       | RADEON_PCIGART_TRANSLATE_EN;
943                 RADEON_WRITE( RADEON_AIC_CNTL, tmp );
944
945                 /* set PCI GART page-table base address
946                  */
947                 RADEON_WRITE( RADEON_AIC_PT_BASE,
948                               virt_to_bus( (void *)dev_priv->phys_pci_gart ) );
949
950                 /* set address range for PCI address translate
951                  */
952                 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
953                 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
954                                                   + dev_priv->agp_size - 1);
955
956                 /* Turn off AGP aperture -- is this required for PCIGART?
957                  */
958                 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
959                 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
960         } else {
961                 /* Turn off PCI GART
962                  */
963                 tmp = RADEON_READ( RADEON_AIC_CNTL )
964                       & ~RADEON_PCIGART_TRANSLATE_EN;
965                 RADEON_WRITE( RADEON_AIC_CNTL, tmp );
966         }
967
968         radeon_cp_load_microcode( dev_priv );
969         radeon_cp_init_ring_buffer( dev, dev_priv );
970
971 #if ROTATE_BUFS
972         dev_priv->last_buf = 0;
973 #endif
974
975         dev->dev_private = (void *)dev_priv;
976
977         radeon_do_engine_reset( dev );
978
979         return 0;
980 }
981
982 int radeon_do_cleanup_cp( drm_device_t *dev )
983 {
984         DRM_DEBUG( "%s\n", __FUNCTION__ );
985
986         if ( dev->dev_private ) {
987                 drm_radeon_private_t *dev_priv = dev->dev_private;
988
989                 if ( !dev_priv->is_pci ) {
990                         DRM_IOREMAPFREE( dev_priv->cp_ring );
991                         DRM_IOREMAPFREE( dev_priv->ring_rptr );
992                         DRM_IOREMAPFREE( dev_priv->buffers );
993                 }
994
995                 DRM(free)( dev->dev_private, sizeof(drm_radeon_private_t),
996                            DRM_MEM_DRIVER );
997                 dev->dev_private = NULL;
998         }
999
1000         return 0;
1001 }
1002
1003 int radeon_cp_init( struct inode *inode, struct file *filp,
1004                     unsigned int cmd, unsigned long arg )
1005 {
1006         drm_file_t *priv = filp->private_data;
1007         drm_device_t *dev = priv->dev;
1008         drm_radeon_init_t init;
1009
1010         if ( copy_from_user( &init, (drm_radeon_init_t *)arg, sizeof(init) ) )
1011                 return -EFAULT;
1012
1013         switch ( init.func ) {
1014         case RADEON_INIT_CP:
1015                 return radeon_do_init_cp( dev, &init );
1016         case RADEON_CLEANUP_CP:
1017                 return radeon_do_cleanup_cp( dev );
1018         }
1019
1020         return -EINVAL;
1021 }
1022
1023 int radeon_cp_start( struct inode *inode, struct file *filp,
1024                      unsigned int cmd, unsigned long arg )
1025 {
1026         drm_file_t *priv = filp->private_data;
1027         drm_device_t *dev = priv->dev;
1028         drm_radeon_private_t *dev_priv = dev->dev_private;
1029         DRM_DEBUG( "%s\n", __FUNCTION__ );
1030
1031         LOCK_TEST_WITH_RETURN( dev );
1032
1033         if ( dev_priv->cp_running ) {
1034                 DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
1035                 return 0;
1036         }
1037         if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
1038                 DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
1039                            __FUNCTION__, dev_priv->cp_mode );
1040                 return 0;
1041         }
1042
1043         radeon_do_cp_start( dev_priv );
1044
1045         return 0;
1046 }
1047
1048 /* Stop the CP.  The engine must have been idled before calling this
1049  * routine.
1050  */
1051 int radeon_cp_stop( struct inode *inode, struct file *filp,
1052                     unsigned int cmd, unsigned long arg )
1053 {
1054         drm_file_t *priv = filp->private_data;
1055         drm_device_t *dev = priv->dev;
1056         drm_radeon_private_t *dev_priv = dev->dev_private;
1057         drm_radeon_cp_stop_t stop;
1058         int ret;
1059         DRM_DEBUG( "%s\n", __FUNCTION__ );
1060
1061         LOCK_TEST_WITH_RETURN( dev );
1062
1063         if ( copy_from_user( &stop, (drm_radeon_init_t *)arg, sizeof(stop) ) )
1064                 return -EFAULT;
1065
1066         /* Flush any pending CP commands.  This ensures any outstanding
1067          * commands are exectuted by the engine before we turn it off.
1068          */
1069         if ( stop.flush ) {
1070                 radeon_do_cp_flush( dev_priv );
1071         }
1072
1073         /* If we fail to make the engine go idle, we return an error
1074          * code so that the DRM ioctl wrapper can try again.
1075          */
1076         if ( stop.idle ) {
1077                 ret = radeon_do_cp_idle( dev_priv );
1078                 if ( ret < 0 ) return ret;
1079         }
1080
1081         /* Finally, we can turn off the CP.  If the engine isn't idle,
1082          * we will get some dropped triangles as they won't be fully
1083          * rendered before the CP is shut down.
1084          */
1085         radeon_do_cp_stop( dev_priv );
1086
1087         /* Reset the engine */
1088         radeon_do_engine_reset( dev );
1089
1090         return 0;
1091 }
1092
1093 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1094  */
1095 int radeon_cp_reset( struct inode *inode, struct file *filp,
1096                      unsigned int cmd, unsigned long arg )
1097 {
1098         drm_file_t *priv = filp->private_data;
1099         drm_device_t *dev = priv->dev;
1100         drm_radeon_private_t *dev_priv = dev->dev_private;
1101         DRM_DEBUG( "%s\n", __FUNCTION__ );
1102
1103         LOCK_TEST_WITH_RETURN( dev );
1104
1105         if ( !dev_priv ) {
1106                 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
1107                 return -EINVAL;
1108         }
1109
1110         radeon_do_cp_reset( dev_priv );
1111
1112         /* The CP is no longer running after an engine reset */
1113         dev_priv->cp_running = 0;
1114
1115         return 0;
1116 }
1117
1118 int radeon_cp_idle( struct inode *inode, struct file *filp,
1119                     unsigned int cmd, unsigned long arg )
1120 {
1121         drm_file_t *priv = filp->private_data;
1122         drm_device_t *dev = priv->dev;
1123         drm_radeon_private_t *dev_priv = dev->dev_private;
1124         DRM_DEBUG( "%s\n", __FUNCTION__ );
1125
1126         LOCK_TEST_WITH_RETURN( dev );
1127
1128         return radeon_do_cp_idle( dev_priv );
1129 }
1130
1131 int radeon_engine_reset( struct inode *inode, struct file *filp,
1132                          unsigned int cmd, unsigned long arg )
1133 {
1134         drm_file_t *priv = filp->private_data;
1135         drm_device_t *dev = priv->dev;
1136         DRM_DEBUG( "%s\n", __FUNCTION__ );
1137
1138         LOCK_TEST_WITH_RETURN( dev );
1139
1140         return radeon_do_engine_reset( dev );
1141 }
1142
1143
1144 /* ================================================================
1145  * Fullscreen mode
1146  */
1147
1148 static int radeon_do_init_pageflip( drm_device_t *dev )
1149 {
1150         drm_radeon_private_t *dev_priv = dev->dev_private;
1151         DRM_DEBUG( "%s\n", __FUNCTION__ );
1152
1153         dev_priv->crtc_offset =      RADEON_READ( RADEON_CRTC_OFFSET );
1154         dev_priv->crtc_offset_cntl = RADEON_READ( RADEON_CRTC_OFFSET_CNTL );
1155
1156         RADEON_WRITE( RADEON_CRTC_OFFSET, dev_priv->front_offset );
1157         RADEON_WRITE( RADEON_CRTC_OFFSET_CNTL,
1158                       dev_priv->crtc_offset_cntl |
1159                       RADEON_CRTC_OFFSET_FLIP_CNTL );
1160
1161         dev_priv->page_flipping = 1;
1162         dev_priv->current_page = 0;
1163
1164         return 0;
1165 }
1166
1167 int radeon_do_cleanup_pageflip( drm_device_t *dev )
1168 {
1169         drm_radeon_private_t *dev_priv = dev->dev_private;
1170         DRM_DEBUG( "%s\n", __FUNCTION__ );
1171
1172         RADEON_WRITE( RADEON_CRTC_OFFSET,      dev_priv->crtc_offset );
1173         RADEON_WRITE( RADEON_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl );
1174
1175         dev_priv->page_flipping = 0;
1176         dev_priv->current_page = 0;
1177
1178         return 0;
1179 }
1180
1181 int radeon_fullscreen( struct inode *inode, struct file *filp,
1182                        unsigned int cmd, unsigned long arg )
1183 {
1184         drm_file_t *priv = filp->private_data;
1185         drm_device_t *dev = priv->dev;
1186         drm_radeon_fullscreen_t fs;
1187
1188         LOCK_TEST_WITH_RETURN( dev );
1189
1190         if ( copy_from_user( &fs, (drm_radeon_fullscreen_t *)arg,
1191                              sizeof(fs) ) )
1192                 return -EFAULT;
1193
1194         switch ( fs.func ) {
1195         case RADEON_INIT_FULLSCREEN:
1196                 return radeon_do_init_pageflip( dev );
1197         case RADEON_CLEANUP_FULLSCREEN:
1198                 return radeon_do_cleanup_pageflip( dev );
1199         }
1200
1201         return -EINVAL;
1202 }
1203
1204
1205 /* ================================================================
1206  * Freelist management
1207  */
1208 #define RADEON_BUFFER_USED      0xffffffff
1209 #define RADEON_BUFFER_FREE      0
1210
1211 #if 0
1212 static int radeon_freelist_init( drm_device_t *dev )
1213 {
1214         drm_device_dma_t *dma = dev->dma;
1215         drm_radeon_private_t *dev_priv = dev->dev_private;
1216         drm_buf_t *buf;
1217         drm_radeon_buf_priv_t *buf_priv;
1218         drm_radeon_freelist_t *entry;
1219         int i;
1220
1221         dev_priv->head = DRM(alloc)( sizeof(drm_radeon_freelist_t),
1222                                      DRM_MEM_DRIVER );
1223         if ( dev_priv->head == NULL )
1224                 return -ENOMEM;
1225
1226         memset( dev_priv->head, 0, sizeof(drm_radeon_freelist_t) );
1227         dev_priv->head->age = RADEON_BUFFER_USED;
1228
1229         for ( i = 0 ; i < dma->buf_count ; i++ ) {
1230                 buf = dma->buflist[i];
1231                 buf_priv = buf->dev_private;
1232
1233                 entry = DRM(alloc)( sizeof(drm_radeon_freelist_t),
1234                                     DRM_MEM_DRIVER );
1235                 if ( !entry ) return -ENOMEM;
1236
1237                 entry->age = RADEON_BUFFER_FREE;
1238                 entry->buf = buf;
1239                 entry->prev = dev_priv->head;
1240                 entry->next = dev_priv->head->next;
1241                 if ( !entry->next )
1242                         dev_priv->tail = entry;
1243
1244                 buf_priv->discard = 0;
1245                 buf_priv->dispatched = 0;
1246                 buf_priv->list_entry = entry;
1247
1248                 dev_priv->head->next = entry;
1249
1250                 if ( dev_priv->head->next )
1251                         dev_priv->head->next->prev = entry;
1252         }
1253
1254         return 0;
1255
1256 }
1257 #endif
1258
1259 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1260 {
1261         drm_device_dma_t *dma = dev->dma;
1262         drm_radeon_private_t *dev_priv = dev->dev_private;
1263         drm_radeon_buf_priv_t *buf_priv;
1264         drm_buf_t *buf;
1265         int i, t;
1266 #if ROTATE_BUFS
1267         int start;
1268 #endif
1269
1270         /* FIXME: Optimize -- use freelist code */
1271
1272         for ( i = 0 ; i < dma->buf_count ; i++ ) {
1273                 buf = dma->buflist[i];
1274                 buf_priv = buf->dev_private;
1275                 if ( buf->pid == 0 ) {
1276                         DRM_DEBUG( "  ret buf=%d last=%d pid=0\n",
1277                                    buf->idx, dev_priv->last_buf );
1278                         return buf;
1279                 }
1280                 DRM_DEBUG( "    skipping buf=%d pid=%d\n",
1281                            buf->idx, buf->pid );
1282         }
1283
1284 #if ROTATE_BUFS
1285         if ( ++dev_priv->last_buf >= dma->buf_count )
1286                 dev_priv->last_buf = 0;
1287         start = dev_priv->last_buf;
1288 #endif
1289         for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
1290 #if 0
1291                 /* FIXME: Disable this for now */
1292                 u32 done_age = dev_priv->scratch[RADEON_LAST_DISPATCH];
1293 #else
1294                 u32 done_age = RADEON_READ( RADEON_LAST_DISPATCH_REG );
1295 #endif
1296 #if ROTATE_BUFS
1297                 for ( i = start ; i < dma->buf_count ; i++ ) {
1298 #else
1299                 for ( i = 0 ; i < dma->buf_count ; i++ ) {
1300 #endif
1301                         buf = dma->buflist[i];
1302                         buf_priv = buf->dev_private;
1303                         if ( buf->pending && buf_priv->age <= done_age ) {
1304                                 /* The buffer has been processed, so it
1305                                  * can now be used.
1306                                  */
1307                                 buf->pending = 0;
1308                                 DRM_DEBUG( "  ret buf=%d last=%d age=%d done=%d\n", buf->idx, dev_priv->last_buf, buf_priv->age, done_age );
1309                                 return buf;
1310                         }
1311                         DRM_DEBUG( "    skipping buf=%d age=%d done=%d\n",
1312                                    buf->idx, buf_priv->age,
1313                                    done_age );
1314 #if ROTATE_BUFS
1315                         start = 0;
1316 #endif
1317                 }
1318                 udelay( 1 );
1319         }
1320
1321         DRM_ERROR( "returning NULL!\n" );
1322         return NULL;
1323 }
1324
1325 void radeon_freelist_reset( drm_device_t *dev )
1326 {
1327         drm_device_dma_t *dma = dev->dma;
1328 #if ROTATE_BUFS
1329         drm_radeon_private_t *dev_priv = dev->dev_private;
1330 #endif
1331         int i;
1332
1333 #if ROTATE_BUFS
1334         dev_priv->last_buf = 0;
1335 #endif
1336         for ( i = 0 ; i < dma->buf_count ; i++ ) {
1337                 drm_buf_t *buf = dma->buflist[i];
1338                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1339                 buf_priv->age = 0;
1340         }
1341 }
1342
1343
1344 /* ================================================================
1345  * CP command submission
1346  */
1347
1348 int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
1349 {
1350         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1351         int i;
1352
1353         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
1354                 radeon_update_ring_snapshot( ring );
1355                 if ( ring->space > n )
1356                         return 0;
1357                 udelay( 1 );
1358         }
1359
1360         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1361 #if RADEON_FIFO_DEBUG
1362         radeon_status( dev_priv );
1363         DRM_ERROR( "failed!\n" );
1364 #endif
1365         return -EBUSY;
1366 }
1367
1368 static int radeon_cp_get_buffers( drm_device_t *dev, drm_dma_t *d )
1369 {
1370         int i;
1371         drm_buf_t *buf;
1372
1373         for ( i = d->granted_count ; i < d->request_count ; i++ ) {
1374                 buf = radeon_freelist_get( dev );
1375                 if ( !buf ) return -EAGAIN;
1376
1377                 buf->pid = current->pid;
1378
1379                 if ( copy_to_user( &d->request_indices[i], &buf->idx,
1380                                    sizeof(buf->idx) ) )
1381                         return -EFAULT;
1382                 if ( copy_to_user( &d->request_sizes[i], &buf->total,
1383                                    sizeof(buf->total) ) )
1384                         return -EFAULT;
1385
1386                 d->granted_count++;
1387         }
1388         return 0;
1389 }
1390
1391 int radeon_cp_buffers( struct inode *inode, struct file *filp,
1392                        unsigned int cmd, unsigned long arg )
1393 {
1394         drm_file_t *priv = filp->private_data;
1395         drm_device_t *dev = priv->dev;
1396         drm_device_dma_t *dma = dev->dma;
1397         int ret = 0;
1398         drm_dma_t d;
1399
1400         LOCK_TEST_WITH_RETURN( dev );
1401
1402         if ( copy_from_user( &d, (drm_dma_t *)arg, sizeof(d) ) )
1403                 return -EFAULT;
1404
1405         /* Please don't send us buffers.
1406          */
1407         if ( d.send_count != 0 ) {
1408                 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
1409                            current->pid, d.send_count );
1410                 return -EINVAL;
1411         }
1412
1413         /* We'll send you buffers.
1414          */
1415         if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
1416                 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
1417                            current->pid, d.request_count, dma->buf_count );
1418                 return -EINVAL;
1419         }
1420
1421         d.granted_count = 0;
1422
1423         if ( d.request_count ) {
1424                 ret = radeon_cp_get_buffers( dev, &d );
1425         }
1426
1427         if ( copy_to_user( (drm_dma_t *)arg, &d, sizeof(d) ) )
1428                 return -EFAULT;
1429
1430         return ret;
1431 }