v2.4.8 -> v2.4.8.1
[opensuse:kernel.git] / arch / ppc / kernel / chrp_pci.c
1 /*
2  * BK Id: SCCS/s.chrp_pci.c 1.20 08/08/01 16:35:43 paulus
3  */
4 /*
5  * CHRP pci routines.
6  */
7
8 #include <linux/config.h>
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/delay.h>
12 #include <linux/string.h>
13 #include <linux/init.h>
14 #include <linux/ide.h>
15 #include <linux/bootmem.h>
16
17 #include <asm/io.h>
18 #include <asm/pgtable.h>
19 #include <asm/irq.h>
20 #include <asm/hydra.h>
21 #include <asm/prom.h>
22 #include <asm/gg2.h>
23 #include <asm/machdep.h>
24 #include <asm/init.h>
25 #include <asm/pci-bridge.h>
26
27 #include "open_pic.h"
28 #include "pci.h"
29
30 /* LongTrail */
31 unsigned long gg2_pci_config_base;
32
33 #define pci_config_addr(dev, offset) \
34 (gg2_pci_config_base | ((dev->bus->number)<<16) | ((dev->devfn)<<8) | (offset))
35
36 volatile struct Hydra *Hydra = NULL;
37
38 /*
39  * The VLSI Golden Gate II has only 512K of PCI configuration space, so we
40  * limit the bus number to 3 bits
41  */
42
43 #define cfg_read(val, addr, type, op)   *val = op((type)(addr))
44 #define cfg_write(val, addr, type, op)  op((type *)(addr), (val))
45
46 #define cfg_read_bad(val, size)         *val = bad_##size;
47 #define cfg_write_bad(val, size)
48
49 #define bad_byte        0xff
50 #define bad_word        0xffff
51 #define bad_dword       0xffffffffU
52
53 #define GG2_PCI_OP(rw, size, type, op)                                      \
54 int __chrp gg2_##rw##_config_##size(struct pci_dev *dev, int off, type val) \
55 {                                                                           \
56         if (dev->bus->number > 7) {                                         \
57                 cfg_##rw##_bad(val, size)                                   \
58                 return PCIBIOS_DEVICE_NOT_FOUND;                            \
59         }                                                                   \
60         cfg_##rw(val, pci_config_addr(dev, off), type, op);                 \
61         return PCIBIOS_SUCCESSFUL;                                          \
62 }
63
64 GG2_PCI_OP(read, byte, u8 *, in_8)
65 GG2_PCI_OP(read, word, u16 *, in_le16)
66 GG2_PCI_OP(read, dword, u32 *, in_le32)
67 GG2_PCI_OP(write, byte, u8, out_8)
68 GG2_PCI_OP(write, word, u16, out_le16)
69 GG2_PCI_OP(write, dword, u32, out_le32)
70
71 static struct pci_ops gg2_pci_ops =
72 {
73         gg2_read_config_byte,
74         gg2_read_config_word,
75         gg2_read_config_dword,
76         gg2_write_config_byte,
77         gg2_write_config_word,
78         gg2_write_config_dword
79 };
80
81 /*
82  * Access functions for PCI config space on IBM "python" host bridges.
83  */
84 #define PYTHON_CFA(b, d, o)     (0x80 | ((b) << 8) | ((d) << 16) \
85                                  | (((o) & ~3) << 24))
86
87 #define PYTHON_PCI_OP(rw, size, type, op, mask)                              \
88 int __chrp                                                                   \
89 python_##rw##_config_##size(struct pci_dev *dev, int offset, type val)       \
90 {                                                                            \
91         struct pci_controller *hose = dev->sysdata;                          \
92                                                                              \
93         out_be32(hose->cfg_addr,                                             \
94                  PYTHON_CFA(dev->bus->number, dev->devfn, offset));          \
95         cfg_##rw(val, hose->cfg_data + (offset & mask), type, op);           \
96         return PCIBIOS_SUCCESSFUL;                                           \
97 }
98
99 PYTHON_PCI_OP(read, byte, u8 *, in_8, 3)
100 PYTHON_PCI_OP(read, word, u16 *, in_le16, 2)
101 PYTHON_PCI_OP(read, dword, u32 *, in_le32, 0)
102 PYTHON_PCI_OP(write, byte, u8, out_8, 3)
103 PYTHON_PCI_OP(write, word, u16, out_le16, 2)
104 PYTHON_PCI_OP(write, dword, u32, out_le32, 0)
105
106 static struct pci_ops python_pci_ops =
107 {
108         python_read_config_byte,
109         python_read_config_word,
110         python_read_config_dword,
111         python_write_config_byte,
112         python_write_config_word,
113         python_write_config_dword
114 };
115
116 /*
117  * Access functions for PCI config space using RTAS calls.
118  */
119 #define RTAS_PCI_READ_OP(size, type, nbytes)                              \
120 int __chrp                                                                \
121 rtas_read_config_##size(struct pci_dev *dev, int offset, type val)        \
122 {                                                                         \
123         unsigned long addr = (offset & 0xff) | ((dev->devfn & 0xff) << 8) \
124                 | ((dev->bus->number & 0xff) << 16);                      \
125         unsigned long ret = ~0UL;                                         \
126         int rval;                                                         \
127                                                                           \
128         rval = call_rtas("read-pci-config", 2, 2, &ret, addr, nbytes);    \
129         *val = ret;                                                       \
130         return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;        \
131 }
132
133 #define RTAS_PCI_WRITE_OP(size, type, nbytes)                             \
134 int __chrp                                                                \
135 rtas_write_config_##size(struct pci_dev *dev, int offset, type val)       \
136 {                                                                         \
137         unsigned long addr = (offset & 0xff) | ((dev->devfn & 0xff) << 8) \
138                 | ((dev->bus->number & 0xff) << 16);                      \
139         int rval;                                                         \
140                                                                           \
141         rval = call_rtas("write-pci-config", 3, 1, NULL,                  \
142                          addr, nbytes, (ulong)val);                       \
143         return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;        \
144 }
145
146 RTAS_PCI_READ_OP(byte, u8 *, 1)
147 RTAS_PCI_READ_OP(word, u16 *, 2)
148 RTAS_PCI_READ_OP(dword, u32 *, 4)
149 RTAS_PCI_WRITE_OP(byte, u8, 1)
150 RTAS_PCI_WRITE_OP(word, u16, 2)
151 RTAS_PCI_WRITE_OP(dword, u32, 4)
152
153 static struct pci_ops rtas_pci_ops =
154 {
155         rtas_read_config_byte,
156         rtas_read_config_word,
157         rtas_read_config_dword,
158         rtas_write_config_byte,
159         rtas_write_config_word,
160         rtas_write_config_dword
161 };
162
163     /*
164      *  Temporary fixes for PCI devices. These should be replaced by OF query
165      *  code -- Geert
166      */
167
168 static u_char hydra_openpic_initsenses[] __initdata = {
169     1,  /* HYDRA_INT_SIO */
170     0,  /* HYDRA_INT_SCSI_DMA */
171     0,  /* HYDRA_INT_SCCA_TX_DMA */
172     0,  /* HYDRA_INT_SCCA_RX_DMA */
173     0,  /* HYDRA_INT_SCCB_TX_DMA */
174     0,  /* HYDRA_INT_SCCB_RX_DMA */
175     1,  /* HYDRA_INT_SCSI */
176     1,  /* HYDRA_INT_SCCA */
177     1,  /* HYDRA_INT_SCCB */
178     1,  /* HYDRA_INT_VIA */
179     1,  /* HYDRA_INT_ADB */
180     0,  /* HYDRA_INT_ADB_NMI */
181         /* all others are 1 (= default) */
182 };
183
184 int __init
185 hydra_init(void)
186 {
187         struct device_node *np;
188
189         np = find_devices("mac-io");
190         if (np == NULL || np->n_addrs == 0) {
191                 printk(KERN_WARNING "Warning: no mac-io found\n");
192                 return 0;
193         }
194         Hydra = ioremap(np->addrs[0].address, np->addrs[0].size);
195         printk("Hydra Mac I/O at %x\n", np->addrs[0].address);
196         out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |
197                                            HYDRA_FC_SCSI_CELL_EN |
198                                            HYDRA_FC_SCCA_ENABLE |
199                                            HYDRA_FC_SCCB_ENABLE |
200                                            HYDRA_FC_ARB_BYPASS |
201                                            HYDRA_FC_MPIC_ENABLE |
202                                            HYDRA_FC_SLOW_SCC_PCLK |
203                                            HYDRA_FC_MPIC_IS_MASTER));
204         OpenPIC_Addr = &Hydra->OpenPIC;
205         OpenPIC_InitSenses = hydra_openpic_initsenses;
206         OpenPIC_NumInitSenses = sizeof(hydra_openpic_initsenses);
207         return 1;
208 }
209
210 void __init
211 chrp_pcibios_fixup(void)
212 {
213         struct pci_dev *dev;
214         struct device_node *np;
215
216         /* PCI interrupts are controlled by the OpenPIC */
217         pci_for_each_dev(dev) {
218                 np = pci_device_to_OF_node(dev);
219                 if ((np != 0) && (np->n_intrs > 0) && (np->intrs[0].line != 0))
220                         dev->irq = np->intrs[0].line;
221                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
222         }
223 }
224
225 void __init
226 chrp_find_bridges(void)
227 {
228         struct device_node *dev;
229         int *bus_range;
230         int len, index = -1;
231         struct pci_controller *hose;
232         volatile unsigned char *cfg;
233         unsigned int *dma;
234         char *model, *machine;
235         int is_longtrail = 0, is_mot = 0;
236         struct device_node *root = find_path_device("/");
237 #ifdef CONFIG_POWER3
238         unsigned int *opprop = (unsigned int *)
239                 get_property(root, "platform-open-pic", NULL);
240         int i;
241 #endif
242
243         /*
244          * The PCI host bridge nodes on some machines don't have
245          * properties to adequately identify them, so we have to
246          * look at what sort of machine this is as well.
247          */
248         machine = get_property(root, "model", NULL);
249         if (machine != NULL) {
250                 is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
251                 is_mot = strncmp(machine, "MOT", 3) == 0;
252         }
253         for (dev = root->child; dev != NULL; dev = dev->sibling) {
254                 if (dev->type == NULL || strcmp(dev->type, "pci") != 0)
255                         continue;
256                 ++index;
257                 /* The GG2 bridge on the LongTrail doesn't have an address */
258                 if (dev->n_addrs < 1 && !is_longtrail) {
259                         printk(KERN_WARNING "Can't use %s: no address\n",
260                                dev->full_name);
261                         continue;
262                 }
263                 bus_range = (int *) get_property(dev, "bus-range", &len);
264                 if (bus_range == NULL || len < 2 * sizeof(int)) {
265                         printk(KERN_WARNING "Can't get bus-range for %s\n",
266                                 dev->full_name);
267                         continue;
268                 }
269                 if (bus_range[1] == bus_range[0])
270                         printk(KERN_INFO "PCI bus %d", bus_range[0]);
271                 else
272                         printk(KERN_INFO "PCI buses %d..%d",
273                                bus_range[0], bus_range[1]);
274                 printk(" controlled by %s", dev->type);
275                 if (dev->n_addrs > 0)
276                         printk(" at %x", dev->addrs[0].address);
277                 printk("\n");
278
279                 hose = pcibios_alloc_controller();
280                 if (!hose) {
281                         printk("Can't allocate PCI controller structure for %s\n",
282                                 dev->full_name);
283                         continue;
284                 }
285                 hose->arch_data = dev;
286                 hose->first_busno = bus_range[0];
287                 hose->last_busno = bus_range[1];
288
289                 model = get_property(dev, "model", NULL);
290                 if (model == NULL)
291                         model = "<none>";
292                 if (device_is_compatible(dev, "IBM,python")) {
293                         hose->ops = &python_pci_ops;
294                         cfg = ioremap(dev->addrs[0].address + 0xf8000, 0x20);
295                         hose->cfg_addr = (volatile unsigned int *) cfg;
296                         hose->cfg_data = cfg + 0x10;
297                 } else if (is_mot
298                            || strncmp(model, "Motorola, Grackle", 17) == 0) {
299                         setup_grackle(hose);
300                 } else if (is_longtrail) {
301                         hose->ops = &gg2_pci_ops;
302                         gg2_pci_config_base = (unsigned long)
303                                 ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
304                 } else {
305                         printk("No methods for %s (model %s), using RTAS\n",
306                                dev->full_name, model);
307                         hose->ops = &rtas_pci_ops;
308                 }
309
310                 pci_process_bridge_OF_ranges(hose, dev, index == 0);
311
312 #ifdef CONFIG_POWER3
313                 if (opprop != NULL) {
314                         i = prom_n_addr_cells(root) * (index + 2) - 1;
315                         openpic_setup_ISU(index, opprop[i]);
316                 }
317 #endif /* CONFIG_POWER3 */
318
319                 /* check the first bridge for a property that we can
320                    use to set pci_dram_offset */
321                 dma = (unsigned int *)
322                         get_property(dev, "ibm,dma-ranges", &len);
323                 if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
324                         pci_dram_offset = dma[2] - dma[3];
325                         printk("pci_dram_offset = %lx\n", pci_dram_offset);
326                 }
327         }
328
329         ppc_md.pcibios_fixup = chrp_pcibios_fixup;
330 }