OMAPDSS: move blocking mgr enable/disable to compat layer
[linux-omap-dss2:linux.git] / drivers / video / omap2 / dss / dispc.c
1 /*
2  * linux/drivers/video/omap2/dss/dispc.c
3  *
4  * Copyright (C) 2009 Nokia Corporation
5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6  *
7  * Some code and ideas taken from drivers/video/omap/ driver
8  * by Imre Deak.
9  *
10  * This program is free software; you can redistribute it and/or modify it
11  * under the terms of the GNU General Public License version 2 as published by
12  * the Free Software Foundation.
13  *
14  * This program is distributed in the hope that it will be useful, but WITHOUT
15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17  * more details.
18  *
19  * You should have received a copy of the GNU General Public License along with
20  * this program.  If not, see <http://www.gnu.org/licenses/>.
21  */
22
23 #define DSS_SUBSYS_NAME "DISPC"
24
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/export.h>
29 #include <linux/clk.h>
30 #include <linux/io.h>
31 #include <linux/jiffies.h>
32 #include <linux/seq_file.h>
33 #include <linux/delay.h>
34 #include <linux/workqueue.h>
35 #include <linux/hardirq.h>
36 #include <linux/interrupt.h>
37 #include <linux/platform_device.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/sizes.h>
40
41 #include <video/omapdss.h>
42
43 #include "dss.h"
44 #include "dss_features.h"
45 #include "dispc.h"
46
47 /* DISPC */
48 #define DISPC_SZ_REGS                   SZ_4K
49
50 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
51                                          DISPC_IRQ_OCP_ERR | \
52                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
53                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
54                                          DISPC_IRQ_SYNC_LOST | \
55                                          DISPC_IRQ_SYNC_LOST_DIGIT)
56
57 #define DISPC_MAX_NR_ISRS               8
58
59 struct omap_dispc_isr_data {
60         omap_dispc_isr_t        isr;
61         void                    *arg;
62         u32                     mask;
63 };
64
65 enum omap_burst_size {
66         BURST_SIZE_X2 = 0,
67         BURST_SIZE_X4 = 1,
68         BURST_SIZE_X8 = 2,
69 };
70
71 #define REG_GET(idx, start, end) \
72         FLD_GET(dispc_read_reg(idx), start, end)
73
74 #define REG_FLD_MOD(idx, val, start, end)                               \
75         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
76
77 struct dispc_irq_stats {
78         unsigned long last_reset;
79         unsigned irq_count;
80         unsigned irqs[32];
81 };
82
83 struct dispc_features {
84         u8 sw_start;
85         u8 fp_start;
86         u8 bp_start;
87         u16 sw_max;
88         u16 vp_max;
89         u16 hp_max;
90         u8 mgr_width_start;
91         u8 mgr_height_start;
92         u16 mgr_width_max;
93         u16 mgr_height_max;
94         int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
95                 const struct omap_video_timings *mgr_timings,
96                 u16 width, u16 height, u16 out_width, u16 out_height,
97                 enum omap_color_mode color_mode, bool *five_taps,
98                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
99                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
100         unsigned long (*calc_core_clk) (unsigned long pclk,
101                 u16 width, u16 height, u16 out_width, u16 out_height,
102                 bool mem_to_mem);
103         u8 num_fifos;
104
105         /* swap GFX & WB fifos */
106         bool gfx_fifo_workaround:1;
107
108         /* no DISPC_IRQ_FRAMEDONETV on this SoC */
109         bool no_framedone_tv:1;
110 };
111
112 #define DISPC_MAX_NR_FIFOS 5
113
114 static struct {
115         struct platform_device *pdev;
116         void __iomem    *base;
117
118         int             ctx_loss_cnt;
119
120         int irq;
121         struct clk *dss_clk;
122
123         u32 fifo_size[DISPC_MAX_NR_FIFOS];
124         /* maps which plane is using a fifo. fifo-id -> plane-id */
125         int fifo_assignment[DISPC_MAX_NR_FIFOS];
126
127         spinlock_t irq_lock;
128         u32 irq_error_mask;
129         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
130         u32 error_irqs;
131         struct work_struct error_work;
132
133         bool            ctx_valid;
134         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
135
136         const struct dispc_features *feat;
137
138 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
139         spinlock_t irq_stats_lock;
140         struct dispc_irq_stats irq_stats;
141 #endif
142 } dispc;
143
144 enum omap_color_component {
145         /* used for all color formats for OMAP3 and earlier
146          * and for RGB and Y color component on OMAP4
147          */
148         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
149         /* used for UV component for
150          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
151          * color formats on OMAP4
152          */
153         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
154 };
155
156 enum mgr_reg_fields {
157         DISPC_MGR_FLD_ENABLE,
158         DISPC_MGR_FLD_STNTFT,
159         DISPC_MGR_FLD_GO,
160         DISPC_MGR_FLD_TFTDATALINES,
161         DISPC_MGR_FLD_STALLMODE,
162         DISPC_MGR_FLD_TCKENABLE,
163         DISPC_MGR_FLD_TCKSELECTION,
164         DISPC_MGR_FLD_CPR,
165         DISPC_MGR_FLD_FIFOHANDCHECK,
166         /* used to maintain a count of the above fields */
167         DISPC_MGR_FLD_NUM,
168 };
169
170 static const struct {
171         const char *name;
172         u32 vsync_irq;
173         u32 framedone_irq;
174         u32 sync_lost_irq;
175         struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
176 } mgr_desc[] = {
177         [OMAP_DSS_CHANNEL_LCD] = {
178                 .name           = "LCD",
179                 .vsync_irq      = DISPC_IRQ_VSYNC,
180                 .framedone_irq  = DISPC_IRQ_FRAMEDONE,
181                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST,
182                 .reg_desc       = {
183                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  0,  0 },
184                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL,  3,  3 },
185                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  5,  5 },
186                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL,  9,  8 },
187                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL, 11, 11 },
188                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  10, 10 },
189                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  11, 11 },
190                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG,  15, 15 },
191                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
192                 },
193         },
194         [OMAP_DSS_CHANNEL_DIGIT] = {
195                 .name           = "DIGIT",
196                 .vsync_irq      = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
197                 .framedone_irq  = DISPC_IRQ_FRAMEDONETV,
198                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST_DIGIT,
199                 .reg_desc       = {
200                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  1,  1 },
201                         [DISPC_MGR_FLD_STNTFT]          = { },
202                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  6,  6 },
203                         [DISPC_MGR_FLD_TFTDATALINES]    = { },
204                         [DISPC_MGR_FLD_STALLMODE]       = { },
205                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  12, 12 },
206                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  13, 13 },
207                         [DISPC_MGR_FLD_CPR]             = { },
208                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
209                 },
210         },
211         [OMAP_DSS_CHANNEL_LCD2] = {
212                 .name           = "LCD2",
213                 .vsync_irq      = DISPC_IRQ_VSYNC2,
214                 .framedone_irq  = DISPC_IRQ_FRAMEDONE2,
215                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST2,
216                 .reg_desc       = {
217                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL2,  0,  0 },
218                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL2,  3,  3 },
219                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL2,  5,  5 },
220                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL2,  9,  8 },
221                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL2, 11, 11 },
222                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG2,  10, 10 },
223                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG2,  11, 11 },
224                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG2,  15, 15 },
225                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG2,  16, 16 },
226                 },
227         },
228         [OMAP_DSS_CHANNEL_LCD3] = {
229                 .name           = "LCD3",
230                 .vsync_irq      = DISPC_IRQ_VSYNC3,
231                 .framedone_irq  = DISPC_IRQ_FRAMEDONE3,
232                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST3,
233                 .reg_desc       = {
234                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL3,  0,  0 },
235                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL3,  3,  3 },
236                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL3,  5,  5 },
237                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL3,  9,  8 },
238                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL3, 11, 11 },
239                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG3,  10, 10 },
240                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG3,  11, 11 },
241                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG3,  15, 15 },
242                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG3,  16, 16 },
243                 },
244         },
245 };
246
247 struct color_conv_coef {
248         int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
249         int full_range;
250 };
251
252 static void _omap_dispc_set_irqs(void);
253 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
254 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
255
256 static inline void dispc_write_reg(const u16 idx, u32 val)
257 {
258         __raw_writel(val, dispc.base + idx);
259 }
260
261 static inline u32 dispc_read_reg(const u16 idx)
262 {
263         return __raw_readl(dispc.base + idx);
264 }
265
266 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
267 {
268         const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
269         return REG_GET(rfld.reg, rfld.high, rfld.low);
270 }
271
272 static void mgr_fld_write(enum omap_channel channel,
273                                         enum mgr_reg_fields regfld, int val) {
274         const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
275         REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
276 }
277
278 #define SR(reg) \
279         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
280 #define RR(reg) \
281         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
282
283 static void dispc_save_context(void)
284 {
285         int i, j;
286
287         DSSDBG("dispc_save_context\n");
288
289         SR(IRQENABLE);
290         SR(CONTROL);
291         SR(CONFIG);
292         SR(LINE_NUMBER);
293         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
294                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
295                 SR(GLOBAL_ALPHA);
296         if (dss_has_feature(FEAT_MGR_LCD2)) {
297                 SR(CONTROL2);
298                 SR(CONFIG2);
299         }
300         if (dss_has_feature(FEAT_MGR_LCD3)) {
301                 SR(CONTROL3);
302                 SR(CONFIG3);
303         }
304
305         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
306                 SR(DEFAULT_COLOR(i));
307                 SR(TRANS_COLOR(i));
308                 SR(SIZE_MGR(i));
309                 if (i == OMAP_DSS_CHANNEL_DIGIT)
310                         continue;
311                 SR(TIMING_H(i));
312                 SR(TIMING_V(i));
313                 SR(POL_FREQ(i));
314                 SR(DIVISORo(i));
315
316                 SR(DATA_CYCLE1(i));
317                 SR(DATA_CYCLE2(i));
318                 SR(DATA_CYCLE3(i));
319
320                 if (dss_has_feature(FEAT_CPR)) {
321                         SR(CPR_COEF_R(i));
322                         SR(CPR_COEF_G(i));
323                         SR(CPR_COEF_B(i));
324                 }
325         }
326
327         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
328                 SR(OVL_BA0(i));
329                 SR(OVL_BA1(i));
330                 SR(OVL_POSITION(i));
331                 SR(OVL_SIZE(i));
332                 SR(OVL_ATTRIBUTES(i));
333                 SR(OVL_FIFO_THRESHOLD(i));
334                 SR(OVL_ROW_INC(i));
335                 SR(OVL_PIXEL_INC(i));
336                 if (dss_has_feature(FEAT_PRELOAD))
337                         SR(OVL_PRELOAD(i));
338                 if (i == OMAP_DSS_GFX) {
339                         SR(OVL_WINDOW_SKIP(i));
340                         SR(OVL_TABLE_BA(i));
341                         continue;
342                 }
343                 SR(OVL_FIR(i));
344                 SR(OVL_PICTURE_SIZE(i));
345                 SR(OVL_ACCU0(i));
346                 SR(OVL_ACCU1(i));
347
348                 for (j = 0; j < 8; j++)
349                         SR(OVL_FIR_COEF_H(i, j));
350
351                 for (j = 0; j < 8; j++)
352                         SR(OVL_FIR_COEF_HV(i, j));
353
354                 for (j = 0; j < 5; j++)
355                         SR(OVL_CONV_COEF(i, j));
356
357                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
358                         for (j = 0; j < 8; j++)
359                                 SR(OVL_FIR_COEF_V(i, j));
360                 }
361
362                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
363                         SR(OVL_BA0_UV(i));
364                         SR(OVL_BA1_UV(i));
365                         SR(OVL_FIR2(i));
366                         SR(OVL_ACCU2_0(i));
367                         SR(OVL_ACCU2_1(i));
368
369                         for (j = 0; j < 8; j++)
370                                 SR(OVL_FIR_COEF_H2(i, j));
371
372                         for (j = 0; j < 8; j++)
373                                 SR(OVL_FIR_COEF_HV2(i, j));
374
375                         for (j = 0; j < 8; j++)
376                                 SR(OVL_FIR_COEF_V2(i, j));
377                 }
378                 if (dss_has_feature(FEAT_ATTR2))
379                         SR(OVL_ATTRIBUTES2(i));
380         }
381
382         if (dss_has_feature(FEAT_CORE_CLK_DIV))
383                 SR(DIVISOR);
384
385         dispc.ctx_loss_cnt = dss_get_ctx_loss_count();
386         dispc.ctx_valid = true;
387
388         DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
389 }
390
391 static void dispc_restore_context(void)
392 {
393         int i, j, ctx;
394
395         DSSDBG("dispc_restore_context\n");
396
397         if (!dispc.ctx_valid)
398                 return;
399
400         ctx = dss_get_ctx_loss_count();
401
402         if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
403                 return;
404
405         DSSDBG("ctx_loss_count: saved %d, current %d\n",
406                         dispc.ctx_loss_cnt, ctx);
407
408         /*RR(IRQENABLE);*/
409         /*RR(CONTROL);*/
410         RR(CONFIG);
411         RR(LINE_NUMBER);
412         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
413                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
414                 RR(GLOBAL_ALPHA);
415         if (dss_has_feature(FEAT_MGR_LCD2))
416                 RR(CONFIG2);
417         if (dss_has_feature(FEAT_MGR_LCD3))
418                 RR(CONFIG3);
419
420         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
421                 RR(DEFAULT_COLOR(i));
422                 RR(TRANS_COLOR(i));
423                 RR(SIZE_MGR(i));
424                 if (i == OMAP_DSS_CHANNEL_DIGIT)
425                         continue;
426                 RR(TIMING_H(i));
427                 RR(TIMING_V(i));
428                 RR(POL_FREQ(i));
429                 RR(DIVISORo(i));
430
431                 RR(DATA_CYCLE1(i));
432                 RR(DATA_CYCLE2(i));
433                 RR(DATA_CYCLE3(i));
434
435                 if (dss_has_feature(FEAT_CPR)) {
436                         RR(CPR_COEF_R(i));
437                         RR(CPR_COEF_G(i));
438                         RR(CPR_COEF_B(i));
439                 }
440         }
441
442         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
443                 RR(OVL_BA0(i));
444                 RR(OVL_BA1(i));
445                 RR(OVL_POSITION(i));
446                 RR(OVL_SIZE(i));
447                 RR(OVL_ATTRIBUTES(i));
448                 RR(OVL_FIFO_THRESHOLD(i));
449                 RR(OVL_ROW_INC(i));
450                 RR(OVL_PIXEL_INC(i));
451                 if (dss_has_feature(FEAT_PRELOAD))
452                         RR(OVL_PRELOAD(i));
453                 if (i == OMAP_DSS_GFX) {
454                         RR(OVL_WINDOW_SKIP(i));
455                         RR(OVL_TABLE_BA(i));
456                         continue;
457                 }
458                 RR(OVL_FIR(i));
459                 RR(OVL_PICTURE_SIZE(i));
460                 RR(OVL_ACCU0(i));
461                 RR(OVL_ACCU1(i));
462
463                 for (j = 0; j < 8; j++)
464                         RR(OVL_FIR_COEF_H(i, j));
465
466                 for (j = 0; j < 8; j++)
467                         RR(OVL_FIR_COEF_HV(i, j));
468
469                 for (j = 0; j < 5; j++)
470                         RR(OVL_CONV_COEF(i, j));
471
472                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
473                         for (j = 0; j < 8; j++)
474                                 RR(OVL_FIR_COEF_V(i, j));
475                 }
476
477                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
478                         RR(OVL_BA0_UV(i));
479                         RR(OVL_BA1_UV(i));
480                         RR(OVL_FIR2(i));
481                         RR(OVL_ACCU2_0(i));
482                         RR(OVL_ACCU2_1(i));
483
484                         for (j = 0; j < 8; j++)
485                                 RR(OVL_FIR_COEF_H2(i, j));
486
487                         for (j = 0; j < 8; j++)
488                                 RR(OVL_FIR_COEF_HV2(i, j));
489
490                         for (j = 0; j < 8; j++)
491                                 RR(OVL_FIR_COEF_V2(i, j));
492                 }
493                 if (dss_has_feature(FEAT_ATTR2))
494                         RR(OVL_ATTRIBUTES2(i));
495         }
496
497         if (dss_has_feature(FEAT_CORE_CLK_DIV))
498                 RR(DIVISOR);
499
500         /* enable last, because LCD & DIGIT enable are here */
501         RR(CONTROL);
502         if (dss_has_feature(FEAT_MGR_LCD2))
503                 RR(CONTROL2);
504         if (dss_has_feature(FEAT_MGR_LCD3))
505                 RR(CONTROL3);
506         /* clear spurious SYNC_LOST_DIGIT interrupts */
507         dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
508
509         /*
510          * enable last so IRQs won't trigger before
511          * the context is fully restored
512          */
513         RR(IRQENABLE);
514
515         DSSDBG("context restored\n");
516 }
517
518 #undef SR
519 #undef RR
520
521 int dispc_runtime_get(void)
522 {
523         int r;
524
525         DSSDBG("dispc_runtime_get\n");
526
527         r = pm_runtime_get_sync(&dispc.pdev->dev);
528         WARN_ON(r < 0);
529         return r < 0 ? r : 0;
530 }
531
532 void dispc_runtime_put(void)
533 {
534         int r;
535
536         DSSDBG("dispc_runtime_put\n");
537
538         r = pm_runtime_put_sync(&dispc.pdev->dev);
539         WARN_ON(r < 0 && r != -ENOSYS);
540 }
541
542 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
543 {
544         return mgr_desc[channel].vsync_irq;
545 }
546
547 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
548 {
549         if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
550                 return 0;
551
552         return mgr_desc[channel].framedone_irq;
553 }
554
555 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
556 {
557         return mgr_desc[channel].sync_lost_irq;
558 }
559
560 u32 dispc_wb_get_framedone_irq(void)
561 {
562         return DISPC_IRQ_FRAMEDONEWB;
563 }
564
565 bool dispc_mgr_go_busy(enum omap_channel channel)
566 {
567         return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
568 }
569
570 void dispc_mgr_go(enum omap_channel channel)
571 {
572         WARN_ON(dispc_mgr_is_enabled(channel) == false);
573         WARN_ON(dispc_mgr_go_busy(channel));
574
575         DSSDBG("GO %s\n", mgr_desc[channel].name);
576
577         mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
578 }
579
580 bool dispc_wb_go_busy(void)
581 {
582         return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
583 }
584
585 void dispc_wb_go(void)
586 {
587         enum omap_plane plane = OMAP_DSS_WB;
588         bool enable, go;
589
590         enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
591
592         if (!enable)
593                 return;
594
595         go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
596         if (go) {
597                 DSSERR("GO bit not down for WB\n");
598                 return;
599         }
600
601         REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
602 }
603
604 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
605 {
606         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
607 }
608
609 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
610 {
611         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
612 }
613
614 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
615 {
616         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
617 }
618
619 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
620 {
621         BUG_ON(plane == OMAP_DSS_GFX);
622
623         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
624 }
625
626 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
627                 u32 value)
628 {
629         BUG_ON(plane == OMAP_DSS_GFX);
630
631         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
632 }
633
634 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
635 {
636         BUG_ON(plane == OMAP_DSS_GFX);
637
638         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
639 }
640
641 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
642                                 int fir_vinc, int five_taps,
643                                 enum omap_color_component color_comp)
644 {
645         const struct dispc_coef *h_coef, *v_coef;
646         int i;
647
648         h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
649         v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
650
651         for (i = 0; i < 8; i++) {
652                 u32 h, hv;
653
654                 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
655                         | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
656                         | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
657                         | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
658                 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
659                         | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
660                         | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
661                         | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
662
663                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
664                         dispc_ovl_write_firh_reg(plane, i, h);
665                         dispc_ovl_write_firhv_reg(plane, i, hv);
666                 } else {
667                         dispc_ovl_write_firh2_reg(plane, i, h);
668                         dispc_ovl_write_firhv2_reg(plane, i, hv);
669                 }
670
671         }
672
673         if (five_taps) {
674                 for (i = 0; i < 8; i++) {
675                         u32 v;
676                         v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
677                                 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
678                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
679                                 dispc_ovl_write_firv_reg(plane, i, v);
680                         else
681                                 dispc_ovl_write_firv2_reg(plane, i, v);
682                 }
683         }
684 }
685
686
687 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
688                 const struct color_conv_coef *ct)
689 {
690 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
691
692         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
693         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy,  ct->rcb));
694         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
695         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
696         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
697
698         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
699
700 #undef CVAL
701 }
702
703 static void dispc_setup_color_conv_coef(void)
704 {
705         int i;
706         int num_ovl = dss_feat_get_num_ovls();
707         int num_wb = dss_feat_get_num_wbs();
708         const struct color_conv_coef ctbl_bt601_5_ovl = {
709                 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
710         };
711         const struct color_conv_coef ctbl_bt601_5_wb = {
712                 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
713         };
714
715         for (i = 1; i < num_ovl; i++)
716                 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
717
718         for (; i < num_wb; i++)
719                 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
720 }
721
722 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
723 {
724         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
725 }
726
727 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
728 {
729         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
730 }
731
732 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
733 {
734         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
735 }
736
737 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
738 {
739         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
740 }
741
742 static void dispc_ovl_set_pos(enum omap_plane plane,
743                 enum omap_overlay_caps caps, int x, int y)
744 {
745         u32 val;
746
747         if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
748                 return;
749
750         val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
751
752         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
753 }
754
755 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
756                 int height)
757 {
758         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
759
760         if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
761                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
762         else
763                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
764 }
765
766 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
767                 int height)
768 {
769         u32 val;
770
771         BUG_ON(plane == OMAP_DSS_GFX);
772
773         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
774
775         if (plane == OMAP_DSS_WB)
776                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
777         else
778                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
779 }
780
781 static void dispc_ovl_set_zorder(enum omap_plane plane,
782                 enum omap_overlay_caps caps, u8 zorder)
783 {
784         if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
785                 return;
786
787         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
788 }
789
790 static void dispc_ovl_enable_zorder_planes(void)
791 {
792         int i;
793
794         if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
795                 return;
796
797         for (i = 0; i < dss_feat_get_num_ovls(); i++)
798                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
799 }
800
801 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
802                 enum omap_overlay_caps caps, bool enable)
803 {
804         if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
805                 return;
806
807         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
808 }
809
810 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
811                 enum omap_overlay_caps caps, u8 global_alpha)
812 {
813         static const unsigned shifts[] = { 0, 8, 16, 24, };
814         int shift;
815
816         if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
817                 return;
818
819         shift = shifts[plane];
820         REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
821 }
822
823 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
824 {
825         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
826 }
827
828 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
829 {
830         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
831 }
832
833 static void dispc_ovl_set_color_mode(enum omap_plane plane,
834                 enum omap_color_mode color_mode)
835 {
836         u32 m = 0;
837         if (plane != OMAP_DSS_GFX) {
838                 switch (color_mode) {
839                 case OMAP_DSS_COLOR_NV12:
840                         m = 0x0; break;
841                 case OMAP_DSS_COLOR_RGBX16:
842                         m = 0x1; break;
843                 case OMAP_DSS_COLOR_RGBA16:
844                         m = 0x2; break;
845                 case OMAP_DSS_COLOR_RGB12U:
846                         m = 0x4; break;
847                 case OMAP_DSS_COLOR_ARGB16:
848                         m = 0x5; break;
849                 case OMAP_DSS_COLOR_RGB16:
850                         m = 0x6; break;
851                 case OMAP_DSS_COLOR_ARGB16_1555:
852                         m = 0x7; break;
853                 case OMAP_DSS_COLOR_RGB24U:
854                         m = 0x8; break;
855                 case OMAP_DSS_COLOR_RGB24P:
856                         m = 0x9; break;
857                 case OMAP_DSS_COLOR_YUV2:
858                         m = 0xa; break;
859                 case OMAP_DSS_COLOR_UYVY:
860                         m = 0xb; break;
861                 case OMAP_DSS_COLOR_ARGB32:
862                         m = 0xc; break;
863                 case OMAP_DSS_COLOR_RGBA32:
864                         m = 0xd; break;
865                 case OMAP_DSS_COLOR_RGBX32:
866                         m = 0xe; break;
867                 case OMAP_DSS_COLOR_XRGB16_1555:
868                         m = 0xf; break;
869                 default:
870                         BUG(); return;
871                 }
872         } else {
873                 switch (color_mode) {
874                 case OMAP_DSS_COLOR_CLUT1:
875                         m = 0x0; break;
876                 case OMAP_DSS_COLOR_CLUT2:
877                         m = 0x1; break;
878                 case OMAP_DSS_COLOR_CLUT4:
879                         m = 0x2; break;
880                 case OMAP_DSS_COLOR_CLUT8:
881                         m = 0x3; break;
882                 case OMAP_DSS_COLOR_RGB12U:
883                         m = 0x4; break;
884                 case OMAP_DSS_COLOR_ARGB16:
885                         m = 0x5; break;
886                 case OMAP_DSS_COLOR_RGB16:
887                         m = 0x6; break;
888                 case OMAP_DSS_COLOR_ARGB16_1555:
889                         m = 0x7; break;
890                 case OMAP_DSS_COLOR_RGB24U:
891                         m = 0x8; break;
892                 case OMAP_DSS_COLOR_RGB24P:
893                         m = 0x9; break;
894                 case OMAP_DSS_COLOR_RGBX16:
895                         m = 0xa; break;
896                 case OMAP_DSS_COLOR_RGBA16:
897                         m = 0xb; break;
898                 case OMAP_DSS_COLOR_ARGB32:
899                         m = 0xc; break;
900                 case OMAP_DSS_COLOR_RGBA32:
901                         m = 0xd; break;
902                 case OMAP_DSS_COLOR_RGBX32:
903                         m = 0xe; break;
904                 case OMAP_DSS_COLOR_XRGB16_1555:
905                         m = 0xf; break;
906                 default:
907                         BUG(); return;
908                 }
909         }
910
911         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
912 }
913
914 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
915                 enum omap_dss_rotation_type rotation_type)
916 {
917         if (dss_has_feature(FEAT_BURST_2D) == 0)
918                 return;
919
920         if (rotation_type == OMAP_DSS_ROT_TILER)
921                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
922         else
923                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
924 }
925
926 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
927 {
928         int shift;
929         u32 val;
930         int chan = 0, chan2 = 0;
931
932         switch (plane) {
933         case OMAP_DSS_GFX:
934                 shift = 8;
935                 break;
936         case OMAP_DSS_VIDEO1:
937         case OMAP_DSS_VIDEO2:
938         case OMAP_DSS_VIDEO3:
939                 shift = 16;
940                 break;
941         default:
942                 BUG();
943                 return;
944         }
945
946         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
947         if (dss_has_feature(FEAT_MGR_LCD2)) {
948                 switch (channel) {
949                 case OMAP_DSS_CHANNEL_LCD:
950                         chan = 0;
951                         chan2 = 0;
952                         break;
953                 case OMAP_DSS_CHANNEL_DIGIT:
954                         chan = 1;
955                         chan2 = 0;
956                         break;
957                 case OMAP_DSS_CHANNEL_LCD2:
958                         chan = 0;
959                         chan2 = 1;
960                         break;
961                 case OMAP_DSS_CHANNEL_LCD3:
962                         if (dss_has_feature(FEAT_MGR_LCD3)) {
963                                 chan = 0;
964                                 chan2 = 2;
965                         } else {
966                                 BUG();
967                                 return;
968                         }
969                         break;
970                 default:
971                         BUG();
972                         return;
973                 }
974
975                 val = FLD_MOD(val, chan, shift, shift);
976                 val = FLD_MOD(val, chan2, 31, 30);
977         } else {
978                 val = FLD_MOD(val, channel, shift, shift);
979         }
980         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
981 }
982
983 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
984 {
985         int shift;
986         u32 val;
987         enum omap_channel channel;
988
989         switch (plane) {
990         case OMAP_DSS_GFX:
991                 shift = 8;
992                 break;
993         case OMAP_DSS_VIDEO1:
994         case OMAP_DSS_VIDEO2:
995         case OMAP_DSS_VIDEO3:
996                 shift = 16;
997                 break;
998         default:
999                 BUG();
1000                 return 0;
1001         }
1002
1003         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1004
1005         if (dss_has_feature(FEAT_MGR_LCD3)) {
1006                 if (FLD_GET(val, 31, 30) == 0)
1007                         channel = FLD_GET(val, shift, shift);
1008                 else if (FLD_GET(val, 31, 30) == 1)
1009                         channel = OMAP_DSS_CHANNEL_LCD2;
1010                 else
1011                         channel = OMAP_DSS_CHANNEL_LCD3;
1012         } else if (dss_has_feature(FEAT_MGR_LCD2)) {
1013                 if (FLD_GET(val, 31, 30) == 0)
1014                         channel = FLD_GET(val, shift, shift);
1015                 else
1016                         channel = OMAP_DSS_CHANNEL_LCD2;
1017         } else {
1018                 channel = FLD_GET(val, shift, shift);
1019         }
1020
1021         return channel;
1022 }
1023
1024 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1025 {
1026         enum omap_plane plane = OMAP_DSS_WB;
1027
1028         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1029 }
1030
1031 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1032                 enum omap_burst_size burst_size)
1033 {
1034         static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1035         int shift;
1036
1037         shift = shifts[plane];
1038         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1039 }
1040
1041 static void dispc_configure_burst_sizes(void)
1042 {
1043         int i;
1044         const int burst_size = BURST_SIZE_X8;
1045
1046         /* Configure burst size always to maximum size */
1047         for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1048                 dispc_ovl_set_burst_size(i, burst_size);
1049 }
1050
1051 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1052 {
1053         unsigned unit = dss_feat_get_burst_size_unit();
1054         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1055         return unit * 8;
1056 }
1057
1058 void dispc_enable_gamma_table(bool enable)
1059 {
1060         /*
1061          * This is partially implemented to support only disabling of
1062          * the gamma table.
1063          */
1064         if (enable) {
1065                 DSSWARN("Gamma table enabling for TV not yet supported");
1066                 return;
1067         }
1068
1069         REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1070 }
1071
1072 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1073 {
1074         if (channel == OMAP_DSS_CHANNEL_DIGIT)
1075                 return;
1076
1077         mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1078 }
1079
1080 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1081                 const struct omap_dss_cpr_coefs *coefs)
1082 {
1083         u32 coef_r, coef_g, coef_b;
1084
1085         if (!dss_mgr_is_lcd(channel))
1086                 return;
1087
1088         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1089                 FLD_VAL(coefs->rb, 9, 0);
1090         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1091                 FLD_VAL(coefs->gb, 9, 0);
1092         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1093                 FLD_VAL(coefs->bb, 9, 0);
1094
1095         dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1096         dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1097         dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1098 }
1099
1100 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1101 {
1102         u32 val;
1103
1104         BUG_ON(plane == OMAP_DSS_GFX);
1105
1106         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1107         val = FLD_MOD(val, enable, 9, 9);
1108         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1109 }
1110
1111 static void dispc_ovl_enable_replication(enum omap_plane plane,
1112                 enum omap_overlay_caps caps, bool enable)
1113 {
1114         static const unsigned shifts[] = { 5, 10, 10, 10 };
1115         int shift;
1116
1117         if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1118                 return;
1119
1120         shift = shifts[plane];
1121         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1122 }
1123
1124 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1125                 u16 height)
1126 {
1127         u32 val;
1128
1129         val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1130                 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1131
1132         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1133 }
1134
1135 static void dispc_init_fifos(void)
1136 {
1137         u32 size;
1138         int fifo;
1139         u8 start, end;
1140         u32 unit;
1141
1142         unit = dss_feat_get_buffer_size_unit();
1143
1144         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1145
1146         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1147                 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1148                 size *= unit;
1149                 dispc.fifo_size[fifo] = size;
1150
1151                 /*
1152                  * By default fifos are mapped directly to overlays, fifo 0 to
1153                  * ovl 0, fifo 1 to ovl 1, etc.
1154                  */
1155                 dispc.fifo_assignment[fifo] = fifo;
1156         }
1157
1158         /*
1159          * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1160          * causes problems with certain use cases, like using the tiler in 2D
1161          * mode. The below hack swaps the fifos of GFX and WB planes, thus
1162          * giving GFX plane a larger fifo. WB but should work fine with a
1163          * smaller fifo.
1164          */
1165         if (dispc.feat->gfx_fifo_workaround) {
1166                 u32 v;
1167
1168                 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1169
1170                 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1171                 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1172                 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1173                 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1174
1175                 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1176
1177                 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1178                 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1179         }
1180 }
1181
1182 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1183 {
1184         int fifo;
1185         u32 size = 0;
1186
1187         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1188                 if (dispc.fifo_assignment[fifo] == plane)
1189                         size += dispc.fifo_size[fifo];
1190         }
1191
1192         return size;
1193 }
1194
1195 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1196 {
1197         u8 hi_start, hi_end, lo_start, lo_end;
1198         u32 unit;
1199
1200         unit = dss_feat_get_buffer_size_unit();
1201
1202         WARN_ON(low % unit != 0);
1203         WARN_ON(high % unit != 0);
1204
1205         low /= unit;
1206         high /= unit;
1207
1208         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1209         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1210
1211         DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1212                         plane,
1213                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1214                                 lo_start, lo_end) * unit,
1215                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1216                                 hi_start, hi_end) * unit,
1217                         low * unit, high * unit);
1218
1219         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1220                         FLD_VAL(high, hi_start, hi_end) |
1221                         FLD_VAL(low, lo_start, lo_end));
1222 }
1223
1224 void dispc_enable_fifomerge(bool enable)
1225 {
1226         if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1227                 WARN_ON(enable);
1228                 return;
1229         }
1230
1231         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1232         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1233 }
1234
1235 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1236                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1237                 bool manual_update)
1238 {
1239         /*
1240          * All sizes are in bytes. Both the buffer and burst are made of
1241          * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1242          */
1243
1244         unsigned buf_unit = dss_feat_get_buffer_size_unit();
1245         unsigned ovl_fifo_size, total_fifo_size, burst_size;
1246         int i;
1247
1248         burst_size = dispc_ovl_get_burst_size(plane);
1249         ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1250
1251         if (use_fifomerge) {
1252                 total_fifo_size = 0;
1253                 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1254                         total_fifo_size += dispc_ovl_get_fifo_size(i);
1255         } else {
1256                 total_fifo_size = ovl_fifo_size;
1257         }
1258
1259         /*
1260          * We use the same low threshold for both fifomerge and non-fifomerge
1261          * cases, but for fifomerge we calculate the high threshold using the
1262          * combined fifo size
1263          */
1264
1265         if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1266                 *fifo_low = ovl_fifo_size - burst_size * 2;
1267                 *fifo_high = total_fifo_size - burst_size;
1268         } else if (plane == OMAP_DSS_WB) {
1269                 /*
1270                  * Most optimal configuration for writeback is to push out data
1271                  * to the interconnect the moment writeback pushes enough pixels
1272                  * in the FIFO to form a burst
1273                  */
1274                 *fifo_low = 0;
1275                 *fifo_high = burst_size;
1276         } else {
1277                 *fifo_low = ovl_fifo_size - burst_size;
1278                 *fifo_high = total_fifo_size - buf_unit;
1279         }
1280 }
1281
1282 static void dispc_ovl_set_fir(enum omap_plane plane,
1283                                 int hinc, int vinc,
1284                                 enum omap_color_component color_comp)
1285 {
1286         u32 val;
1287
1288         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1289                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1290
1291                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1292                                         &hinc_start, &hinc_end);
1293                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1294                                         &vinc_start, &vinc_end);
1295                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1296                                 FLD_VAL(hinc, hinc_start, hinc_end);
1297
1298                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1299         } else {
1300                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1301                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1302         }
1303 }
1304
1305 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1306 {
1307         u32 val;
1308         u8 hor_start, hor_end, vert_start, vert_end;
1309
1310         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1311         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1312
1313         val = FLD_VAL(vaccu, vert_start, vert_end) |
1314                         FLD_VAL(haccu, hor_start, hor_end);
1315
1316         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1317 }
1318
1319 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1320 {
1321         u32 val;
1322         u8 hor_start, hor_end, vert_start, vert_end;
1323
1324         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1325         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1326
1327         val = FLD_VAL(vaccu, vert_start, vert_end) |
1328                         FLD_VAL(haccu, hor_start, hor_end);
1329
1330         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1331 }
1332
1333 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1334                 int vaccu)
1335 {
1336         u32 val;
1337
1338         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1339         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1340 }
1341
1342 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1343                 int vaccu)
1344 {
1345         u32 val;
1346
1347         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1348         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1349 }
1350
1351 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1352                 u16 orig_width, u16 orig_height,
1353                 u16 out_width, u16 out_height,
1354                 bool five_taps, u8 rotation,
1355                 enum omap_color_component color_comp)
1356 {
1357         int fir_hinc, fir_vinc;
1358
1359         fir_hinc = 1024 * orig_width / out_width;
1360         fir_vinc = 1024 * orig_height / out_height;
1361
1362         dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1363                                 color_comp);
1364         dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1365 }
1366
1367 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1368                 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1369                 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1370 {
1371         int h_accu2_0, h_accu2_1;
1372         int v_accu2_0, v_accu2_1;
1373         int chroma_hinc, chroma_vinc;
1374         int idx;
1375
1376         struct accu {
1377                 s8 h0_m, h0_n;
1378                 s8 h1_m, h1_n;
1379                 s8 v0_m, v0_n;
1380                 s8 v1_m, v1_n;
1381         };
1382
1383         const struct accu *accu_table;
1384         const struct accu *accu_val;
1385
1386         static const struct accu accu_nv12[4] = {
1387                 {  0, 1,  0, 1 , -1, 2, 0, 1 },
1388                 {  1, 2, -3, 4 ,  0, 1, 0, 1 },
1389                 { -1, 1,  0, 1 , -1, 2, 0, 1 },
1390                 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1391         };
1392
1393         static const struct accu accu_nv12_ilace[4] = {
1394                 {  0, 1,  0, 1 , -3, 4, -1, 4 },
1395                 { -1, 4, -3, 4 ,  0, 1,  0, 1 },
1396                 { -1, 1,  0, 1 , -1, 4, -3, 4 },
1397                 { -3, 4, -3, 4 , -1, 1,  0, 1 },
1398         };
1399
1400         static const struct accu accu_yuv[4] = {
1401                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1402                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1403                 { -1, 1, 0, 1,  0, 1, 0, 1 },
1404                 {  0, 1, 0, 1, -1, 1, 0, 1 },
1405         };
1406
1407         switch (rotation) {
1408         case OMAP_DSS_ROT_0:
1409                 idx = 0;
1410                 break;
1411         case OMAP_DSS_ROT_90:
1412                 idx = 1;
1413                 break;
1414         case OMAP_DSS_ROT_180:
1415                 idx = 2;
1416                 break;
1417         case OMAP_DSS_ROT_270:
1418                 idx = 3;
1419                 break;
1420         default:
1421                 BUG();
1422                 return;
1423         }
1424
1425         switch (color_mode) {
1426         case OMAP_DSS_COLOR_NV12:
1427                 if (ilace)
1428                         accu_table = accu_nv12_ilace;
1429                 else
1430                         accu_table = accu_nv12;
1431                 break;
1432         case OMAP_DSS_COLOR_YUV2:
1433         case OMAP_DSS_COLOR_UYVY:
1434                 accu_table = accu_yuv;
1435                 break;
1436         default:
1437                 BUG();
1438                 return;
1439         }
1440
1441         accu_val = &accu_table[idx];
1442
1443         chroma_hinc = 1024 * orig_width / out_width;
1444         chroma_vinc = 1024 * orig_height / out_height;
1445
1446         h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1447         h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1448         v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1449         v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1450
1451         dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1452         dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1453 }
1454
1455 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1456                 u16 orig_width, u16 orig_height,
1457                 u16 out_width, u16 out_height,
1458                 bool ilace, bool five_taps,
1459                 bool fieldmode, enum omap_color_mode color_mode,
1460                 u8 rotation)
1461 {
1462         int accu0 = 0;
1463         int accu1 = 0;
1464         u32 l;
1465
1466         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1467                                 out_width, out_height, five_taps,
1468                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1469         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1470
1471         /* RESIZEENABLE and VERTICALTAPS */
1472         l &= ~((0x3 << 5) | (0x1 << 21));
1473         l |= (orig_width != out_width) ? (1 << 5) : 0;
1474         l |= (orig_height != out_height) ? (1 << 6) : 0;
1475         l |= five_taps ? (1 << 21) : 0;
1476
1477         /* VRESIZECONF and HRESIZECONF */
1478         if (dss_has_feature(FEAT_RESIZECONF)) {
1479                 l &= ~(0x3 << 7);
1480                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1481                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1482         }
1483
1484         /* LINEBUFFERSPLIT */
1485         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1486                 l &= ~(0x1 << 22);
1487                 l |= five_taps ? (1 << 22) : 0;
1488         }
1489
1490         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1491
1492         /*
1493          * field 0 = even field = bottom field
1494          * field 1 = odd field = top field
1495          */
1496         if (ilace && !fieldmode) {
1497                 accu1 = 0;
1498                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1499                 if (accu0 >= 1024/2) {
1500                         accu1 = 1024/2;
1501                         accu0 -= accu1;
1502                 }
1503         }
1504
1505         dispc_ovl_set_vid_accu0(plane, 0, accu0);
1506         dispc_ovl_set_vid_accu1(plane, 0, accu1);
1507 }
1508
1509 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1510                 u16 orig_width, u16 orig_height,
1511                 u16 out_width, u16 out_height,
1512                 bool ilace, bool five_taps,
1513                 bool fieldmode, enum omap_color_mode color_mode,
1514                 u8 rotation)
1515 {
1516         int scale_x = out_width != orig_width;
1517         int scale_y = out_height != orig_height;
1518         bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1519
1520         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1521                 return;
1522         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1523                         color_mode != OMAP_DSS_COLOR_UYVY &&
1524                         color_mode != OMAP_DSS_COLOR_NV12)) {
1525                 /* reset chroma resampling for RGB formats  */
1526                 if (plane != OMAP_DSS_WB)
1527                         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1528                 return;
1529         }
1530
1531         dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1532                         out_height, ilace, color_mode, rotation);
1533
1534         switch (color_mode) {
1535         case OMAP_DSS_COLOR_NV12:
1536                 if (chroma_upscale) {
1537                         /* UV is subsampled by 2 horizontally and vertically */
1538                         orig_height >>= 1;
1539                         orig_width >>= 1;
1540                 } else {
1541                         /* UV is downsampled by 2 horizontally and vertically */
1542                         orig_height <<= 1;
1543                         orig_width <<= 1;
1544                 }
1545
1546                 break;
1547         case OMAP_DSS_COLOR_YUV2:
1548         case OMAP_DSS_COLOR_UYVY:
1549                 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1550                 if (rotation == OMAP_DSS_ROT_0 ||
1551                                 rotation == OMAP_DSS_ROT_180) {
1552                         if (chroma_upscale)
1553                                 /* UV is subsampled by 2 horizontally */
1554                                 orig_width >>= 1;
1555                         else
1556                                 /* UV is downsampled by 2 horizontally */
1557                                 orig_width <<= 1;
1558                 }
1559
1560                 /* must use FIR for YUV422 if rotated */
1561                 if (rotation != OMAP_DSS_ROT_0)
1562                         scale_x = scale_y = true;
1563
1564                 break;
1565         default:
1566                 BUG();
1567                 return;
1568         }
1569
1570         if (out_width != orig_width)
1571                 scale_x = true;
1572         if (out_height != orig_height)
1573                 scale_y = true;
1574
1575         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1576                         out_width, out_height, five_taps,
1577                                 rotation, DISPC_COLOR_COMPONENT_UV);
1578
1579         if (plane != OMAP_DSS_WB)
1580                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1581                         (scale_x || scale_y) ? 1 : 0, 8, 8);
1582
1583         /* set H scaling */
1584         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1585         /* set V scaling */
1586         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1587 }
1588
1589 static void dispc_ovl_set_scaling(enum omap_plane plane,
1590                 u16 orig_width, u16 orig_height,
1591                 u16 out_width, u16 out_height,
1592                 bool ilace, bool five_taps,
1593                 bool fieldmode, enum omap_color_mode color_mode,
1594                 u8 rotation)
1595 {
1596         BUG_ON(plane == OMAP_DSS_GFX);
1597
1598         dispc_ovl_set_scaling_common(plane,
1599                         orig_width, orig_height,
1600                         out_width, out_height,
1601                         ilace, five_taps,
1602                         fieldmode, color_mode,
1603                         rotation);
1604
1605         dispc_ovl_set_scaling_uv(plane,
1606                 orig_width, orig_height,
1607                 out_width, out_height,
1608                 ilace, five_taps,
1609                 fieldmode, color_mode,
1610                 rotation);
1611 }
1612
1613 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1614                 bool mirroring, enum omap_color_mode color_mode)
1615 {
1616         bool row_repeat = false;
1617         int vidrot = 0;
1618
1619         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1620                         color_mode == OMAP_DSS_COLOR_UYVY) {
1621
1622                 if (mirroring) {
1623                         switch (rotation) {
1624                         case OMAP_DSS_ROT_0:
1625                                 vidrot = 2;
1626                                 break;
1627                         case OMAP_DSS_ROT_90:
1628                                 vidrot = 1;
1629                                 break;
1630                         case OMAP_DSS_ROT_180:
1631                                 vidrot = 0;
1632                                 break;
1633                         case OMAP_DSS_ROT_270:
1634                                 vidrot = 3;
1635                                 break;
1636                         }
1637                 } else {
1638                         switch (rotation) {
1639                         case OMAP_DSS_ROT_0:
1640                                 vidrot = 0;
1641                                 break;
1642                         case OMAP_DSS_ROT_90:
1643                                 vidrot = 1;
1644                                 break;
1645                         case OMAP_DSS_ROT_180:
1646                                 vidrot = 2;
1647                                 break;
1648                         case OMAP_DSS_ROT_270:
1649                                 vidrot = 3;
1650                                 break;
1651                         }
1652                 }
1653
1654                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1655                         row_repeat = true;
1656                 else
1657                         row_repeat = false;
1658         }
1659
1660         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1661         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1662                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1663                         row_repeat ? 1 : 0, 18, 18);
1664 }
1665
1666 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1667 {
1668         switch (color_mode) {
1669         case OMAP_DSS_COLOR_CLUT1:
1670                 return 1;
1671         case OMAP_DSS_COLOR_CLUT2:
1672                 return 2;
1673         case OMAP_DSS_COLOR_CLUT4:
1674                 return 4;
1675         case OMAP_DSS_COLOR_CLUT8:
1676         case OMAP_DSS_COLOR_NV12:
1677                 return 8;
1678         case OMAP_DSS_COLOR_RGB12U:
1679         case OMAP_DSS_COLOR_RGB16:
1680         case OMAP_DSS_COLOR_ARGB16:
1681         case OMAP_DSS_COLOR_YUV2:
1682         case OMAP_DSS_COLOR_UYVY:
1683         case OMAP_DSS_COLOR_RGBA16:
1684         case OMAP_DSS_COLOR_RGBX16:
1685         case OMAP_DSS_COLOR_ARGB16_1555:
1686         case OMAP_DSS_COLOR_XRGB16_1555:
1687                 return 16;
1688         case OMAP_DSS_COLOR_RGB24P:
1689                 return 24;
1690         case OMAP_DSS_COLOR_RGB24U:
1691         case OMAP_DSS_COLOR_ARGB32:
1692         case OMAP_DSS_COLOR_RGBA32:
1693         case OMAP_DSS_COLOR_RGBX32:
1694                 return 32;
1695         default:
1696                 BUG();
1697                 return 0;
1698         }
1699 }
1700
1701 static s32 pixinc(int pixels, u8 ps)
1702 {
1703         if (pixels == 1)
1704                 return 1;
1705         else if (pixels > 1)
1706                 return 1 + (pixels - 1) * ps;
1707         else if (pixels < 0)
1708                 return 1 - (-pixels + 1) * ps;
1709         else
1710                 BUG();
1711                 return 0;
1712 }
1713
1714 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1715                 u16 screen_width,
1716                 u16 width, u16 height,
1717                 enum omap_color_mode color_mode, bool fieldmode,
1718                 unsigned int field_offset,
1719                 unsigned *offset0, unsigned *offset1,
1720                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1721 {
1722         u8 ps;
1723
1724         /* FIXME CLUT formats */
1725         switch (color_mode) {
1726         case OMAP_DSS_COLOR_CLUT1:
1727         case OMAP_DSS_COLOR_CLUT2:
1728         case OMAP_DSS_COLOR_CLUT4:
1729         case OMAP_DSS_COLOR_CLUT8:
1730                 BUG();
1731                 return;
1732         case OMAP_DSS_COLOR_YUV2:
1733         case OMAP_DSS_COLOR_UYVY:
1734                 ps = 4;
1735                 break;
1736         default:
1737                 ps = color_mode_to_bpp(color_mode) / 8;
1738                 break;
1739         }
1740
1741         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1742                         width, height);
1743
1744         /*
1745          * field 0 = even field = bottom field
1746          * field 1 = odd field = top field
1747          */
1748         switch (rotation + mirror * 4) {
1749         case OMAP_DSS_ROT_0:
1750         case OMAP_DSS_ROT_180:
1751                 /*
1752                  * If the pixel format is YUV or UYVY divide the width
1753                  * of the image by 2 for 0 and 180 degree rotation.
1754                  */
1755                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1756                         color_mode == OMAP_DSS_COLOR_UYVY)
1757                         width = width >> 1;
1758         case OMAP_DSS_ROT_90:
1759         case OMAP_DSS_ROT_270:
1760                 *offset1 = 0;
1761                 if (field_offset)
1762                         *offset0 = field_offset * screen_width * ps;
1763                 else
1764                         *offset0 = 0;
1765
1766                 *row_inc = pixinc(1 +
1767                         (y_predecim * screen_width - x_predecim * width) +
1768                         (fieldmode ? screen_width : 0), ps);
1769                 *pix_inc = pixinc(x_predecim, ps);
1770                 break;
1771
1772         case OMAP_DSS_ROT_0 + 4:
1773         case OMAP_DSS_ROT_180 + 4:
1774                 /* If the pixel format is YUV or UYVY divide the width
1775                  * of the image by 2  for 0 degree and 180 degree
1776                  */
1777                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1778                         color_mode == OMAP_DSS_COLOR_UYVY)
1779                         width = width >> 1;
1780         case OMAP_DSS_ROT_90 + 4:
1781         case OMAP_DSS_ROT_270 + 4:
1782                 *offset1 = 0;
1783                 if (field_offset)
1784                         *offset0 = field_offset * screen_width * ps;
1785                 else
1786                         *offset0 = 0;
1787                 *row_inc = pixinc(1 -
1788                         (y_predecim * screen_width + x_predecim * width) -
1789                         (fieldmode ? screen_width : 0), ps);
1790                 *pix_inc = pixinc(x_predecim, ps);
1791                 break;
1792
1793         default:
1794                 BUG();
1795                 return;
1796         }
1797 }
1798
1799 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1800                 u16 screen_width,
1801                 u16 width, u16 height,
1802                 enum omap_color_mode color_mode, bool fieldmode,
1803                 unsigned int field_offset,
1804                 unsigned *offset0, unsigned *offset1,
1805                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1806 {
1807         u8 ps;
1808         u16 fbw, fbh;
1809
1810         /* FIXME CLUT formats */
1811         switch (color_mode) {
1812         case OMAP_DSS_COLOR_CLUT1:
1813         case OMAP_DSS_COLOR_CLUT2:
1814         case OMAP_DSS_COLOR_CLUT4:
1815         case OMAP_DSS_COLOR_CLUT8:
1816                 BUG();
1817                 return;
1818         default:
1819                 ps = color_mode_to_bpp(color_mode) / 8;
1820                 break;
1821         }
1822
1823         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1824                         width, height);
1825
1826         /* width & height are overlay sizes, convert to fb sizes */
1827
1828         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1829                 fbw = width;
1830                 fbh = height;
1831         } else {
1832                 fbw = height;
1833                 fbh = width;
1834         }
1835
1836         /*
1837          * field 0 = even field = bottom field
1838          * field 1 = odd field = top field
1839          */
1840         switch (rotation + mirror * 4) {
1841         case OMAP_DSS_ROT_0:
1842                 *offset1 = 0;
1843                 if (field_offset)
1844                         *offset0 = *offset1 + field_offset * screen_width * ps;
1845                 else
1846                         *offset0 = *offset1;
1847                 *row_inc = pixinc(1 +
1848                         (y_predecim * screen_width - fbw * x_predecim) +
1849                         (fieldmode ? screen_width : 0), ps);
1850                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1851                         color_mode == OMAP_DSS_COLOR_UYVY)
1852                         *pix_inc = pixinc(x_predecim, 2 * ps);
1853                 else
1854                         *pix_inc = pixinc(x_predecim, ps);
1855                 break;
1856         case OMAP_DSS_ROT_90:
1857                 *offset1 = screen_width * (fbh - 1) * ps;
1858                 if (field_offset)
1859                         *offset0 = *offset1 + field_offset * ps;
1860                 else
1861                         *offset0 = *offset1;
1862                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1863                                 y_predecim + (fieldmode ? 1 : 0), ps);
1864                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1865                 break;
1866         case OMAP_DSS_ROT_180:
1867                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1868                 if (field_offset)
1869                         *offset0 = *offset1 - field_offset * screen_width * ps;
1870                 else
1871                         *offset0 = *offset1;
1872                 *row_inc = pixinc(-1 -
1873                         (y_predecim * screen_width - fbw * x_predecim) -
1874                         (fieldmode ? screen_width : 0), ps);
1875                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1876                         color_mode == OMAP_DSS_COLOR_UYVY)
1877                         *pix_inc = pixinc(-x_predecim, 2 * ps);
1878                 else
1879                         *pix_inc = pixinc(-x_predecim, ps);
1880                 break;
1881         case OMAP_DSS_ROT_270:
1882                 *offset1 = (fbw - 1) * ps;
1883                 if (field_offset)
1884                         *offset0 = *offset1 - field_offset * ps;
1885                 else
1886                         *offset0 = *offset1;
1887                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1888                                 y_predecim - (fieldmode ? 1 : 0), ps);
1889                 *pix_inc = pixinc(x_predecim * screen_width, ps);
1890                 break;
1891
1892         /* mirroring */
1893         case OMAP_DSS_ROT_0 + 4:
1894                 *offset1 = (fbw - 1) * ps;
1895                 if (field_offset)
1896                         *offset0 = *offset1 + field_offset * screen_width * ps;
1897                 else
1898                         *offset0 = *offset1;
1899                 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
1900                                 (fieldmode ? screen_width : 0),
1901                                 ps);
1902                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1903                         color_mode == OMAP_DSS_COLOR_UYVY)
1904                         *pix_inc = pixinc(-x_predecim, 2 * ps);
1905                 else
1906                         *pix_inc = pixinc(-x_predecim, ps);
1907                 break;
1908
1909         case OMAP_DSS_ROT_90 + 4:
1910                 *offset1 = 0;
1911                 if (field_offset)
1912                         *offset0 = *offset1 + field_offset * ps;
1913                 else
1914                         *offset0 = *offset1;
1915                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1916                                 y_predecim + (fieldmode ? 1 : 0),
1917                                 ps);
1918                 *pix_inc = pixinc(x_predecim * screen_width, ps);
1919                 break;
1920
1921         case OMAP_DSS_ROT_180 + 4:
1922                 *offset1 = screen_width * (fbh - 1) * ps;
1923                 if (field_offset)
1924                         *offset0 = *offset1 - field_offset * screen_width * ps;
1925                 else
1926                         *offset0 = *offset1;
1927                 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
1928                                 (fieldmode ? screen_width : 0),
1929                                 ps);
1930                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1931                         color_mode == OMAP_DSS_COLOR_UYVY)
1932                         *pix_inc = pixinc(x_predecim, 2 * ps);
1933                 else
1934                         *pix_inc = pixinc(x_predecim, ps);
1935                 break;
1936
1937         case OMAP_DSS_ROT_270 + 4:
1938                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1939                 if (field_offset)
1940                         *offset0 = *offset1 - field_offset * ps;
1941                 else
1942                         *offset0 = *offset1;
1943                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1944                                 y_predecim - (fieldmode ? 1 : 0),
1945                                 ps);
1946                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1947                 break;
1948
1949         default:
1950                 BUG();
1951                 return;
1952         }
1953 }
1954
1955 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1956                 enum omap_color_mode color_mode, bool fieldmode,
1957                 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1958                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1959 {
1960         u8 ps;
1961
1962         switch (color_mode) {
1963         case OMAP_DSS_COLOR_CLUT1:
1964         case OMAP_DSS_COLOR_CLUT2:
1965         case OMAP_DSS_COLOR_CLUT4:
1966         case OMAP_DSS_COLOR_CLUT8:
1967                 BUG();
1968                 return;
1969         default:
1970                 ps = color_mode_to_bpp(color_mode) / 8;
1971                 break;
1972         }
1973
1974         DSSDBG("scrw %d, width %d\n", screen_width, width);
1975
1976         /*
1977          * field 0 = even field = bottom field
1978          * field 1 = odd field = top field
1979          */
1980         *offset1 = 0;
1981         if (field_offset)
1982                 *offset0 = *offset1 + field_offset * screen_width * ps;
1983         else
1984                 *offset0 = *offset1;
1985         *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1986                         (fieldmode ? screen_width : 0), ps);
1987         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1988                 color_mode == OMAP_DSS_COLOR_UYVY)
1989                 *pix_inc = pixinc(x_predecim, 2 * ps);
1990         else
1991                 *pix_inc = pixinc(x_predecim, ps);
1992 }
1993
1994 /*
1995  * This function is used to avoid synclosts in OMAP3, because of some
1996  * undocumented horizontal position and timing related limitations.
1997  */
1998 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
1999                 const struct omap_video_timings *t, u16 pos_x,
2000                 u16 width, u16 height, u16 out_width, u16 out_height)
2001 {
2002         const int ds = DIV_ROUND_UP(height, out_height);
2003         unsigned long nonactive;
2004         static const u8 limits[3] = { 8, 10, 20 };
2005         u64 val, blank;
2006         int i;
2007
2008         nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2009
2010         i = 0;
2011         if (out_height < height)
2012                 i++;
2013         if (out_width < width)
2014                 i++;
2015         blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2016         DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2017         if (blank <= limits[i])
2018                 return -EINVAL;
2019
2020         /*
2021          * Pixel data should be prepared before visible display point starts.
2022          * So, atleast DS-2 lines must have already been fetched by DISPC
2023          * during nonactive - pos_x period.
2024          */
2025         val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2026         DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2027                 val, max(0, ds - 2) * width);
2028         if (val < max(0, ds - 2) * width)
2029                 return -EINVAL;
2030
2031         /*
2032          * All lines need to be refilled during the nonactive period of which
2033          * only one line can be loaded during the active period. So, atleast
2034          * DS - 1 lines should be loaded during nonactive period.
2035          */
2036         val =  div_u64((u64)nonactive * lclk, pclk);
2037         DSSDBG("nonactive * pcd  = %llu, max(0, DS - 1) * width = %d\n",
2038                 val, max(0, ds - 1) * width);
2039         if (val < max(0, ds - 1) * width)
2040                 return -EINVAL;
2041
2042         return 0;
2043 }
2044
2045 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2046                 const struct omap_video_timings *mgr_timings, u16 width,
2047                 u16 height, u16 out_width, u16 out_height,
2048                 enum omap_color_mode color_mode)
2049 {
2050         u32 core_clk = 0;
2051         u64 tmp;
2052
2053         if (height <= out_height && width <= out_width)
2054                 return (unsigned long) pclk;
2055
2056         if (height > out_height) {
2057                 unsigned int ppl = mgr_timings->x_res;
2058
2059                 tmp = pclk * height * out_width;
2060                 do_div(tmp, 2 * out_height * ppl);
2061                 core_clk = tmp;
2062
2063                 if (height > 2 * out_height) {
2064                         if (ppl == out_width)
2065                                 return 0;
2066
2067                         tmp = pclk * (height - 2 * out_height) * out_width;
2068                         do_div(tmp, 2 * out_height * (ppl - out_width));
2069                         core_clk = max_t(u32, core_clk, tmp);
2070                 }
2071         }
2072
2073         if (width > out_width) {
2074                 tmp = pclk * width;
2075                 do_div(tmp, out_width);
2076                 core_clk = max_t(u32, core_clk, tmp);
2077
2078                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2079                         core_clk <<= 1;
2080         }
2081
2082         return core_clk;
2083 }
2084
2085 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2086                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2087 {
2088         if (height > out_height && width > out_width)
2089                 return pclk * 4;
2090         else
2091                 return pclk * 2;
2092 }
2093
2094 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2095                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2096 {
2097         unsigned int hf, vf;
2098
2099         /*
2100          * FIXME how to determine the 'A' factor
2101          * for the no downscaling case ?
2102          */
2103
2104         if (width > 3 * out_width)
2105                 hf = 4;
2106         else if (width > 2 * out_width)
2107                 hf = 3;
2108         else if (width > out_width)
2109                 hf = 2;
2110         else
2111                 hf = 1;
2112         if (height > out_height)
2113                 vf = 2;
2114         else
2115                 vf = 1;
2116
2117         return pclk * vf * hf;
2118 }
2119
2120 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2121                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2122 {
2123         /*
2124          * If the overlay/writeback is in mem to mem mode, there are no
2125          * downscaling limitations with respect to pixel clock, return 1 as
2126          * required core clock to represent that we have sufficient enough
2127          * core clock to do maximum downscaling
2128          */
2129         if (mem_to_mem)
2130                 return 1;
2131
2132         if (width > out_width)
2133                 return DIV_ROUND_UP(pclk, out_width) * width;
2134         else
2135                 return pclk;
2136 }
2137
2138 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2139                 const struct omap_video_timings *mgr_timings,
2140                 u16 width, u16 height, u16 out_width, u16 out_height,
2141                 enum omap_color_mode color_mode, bool *five_taps,
2142                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2143                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2144 {
2145         int error;
2146         u16 in_width, in_height;
2147         int min_factor = min(*decim_x, *decim_y);
2148         const int maxsinglelinewidth =
2149                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2150
2151         *five_taps = false;
2152
2153         do {
2154                 in_height = DIV_ROUND_UP(height, *decim_y);
2155                 in_width = DIV_ROUND_UP(width, *decim_x);
2156                 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2157                                 in_height, out_width, out_height, mem_to_mem);
2158                 error = (in_width > maxsinglelinewidth || !*core_clk ||
2159                         *core_clk > dispc_core_clk_rate());
2160                 if (error) {
2161                         if (*decim_x == *decim_y) {
2162                                 *decim_x = min_factor;
2163                                 ++*decim_y;
2164                         } else {
2165                                 swap(*decim_x, *decim_y);
2166                                 if (*decim_x < *decim_y)
2167                                         ++*decim_x;
2168                         }
2169                 }
2170         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2171
2172         if (in_width > maxsinglelinewidth) {
2173                 DSSERR("Cannot scale max input width exceeded");
2174                 return -EINVAL;
2175         }
2176         return 0;
2177 }
2178
2179 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2180                 const struct omap_video_timings *mgr_timings,
2181                 u16 width, u16 height, u16 out_width, u16 out_height,
2182                 enum omap_color_mode color_mode, bool *five_taps,
2183                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2184                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2185 {
2186         int error;
2187         u16 in_width, in_height;
2188         int min_factor = min(*decim_x, *decim_y);
2189         const int maxsinglelinewidth =
2190                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2191
2192         do {
2193                 in_height = DIV_ROUND_UP(height, *decim_y);
2194                 in_width = DIV_ROUND_UP(width, *decim_x);
2195                 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2196                         in_width, in_height, out_width, out_height, color_mode);
2197
2198                 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2199                                 pos_x, in_width, in_height, out_width,
2200                                 out_height);
2201
2202                 if (in_width > maxsinglelinewidth)
2203                         if (in_height > out_height &&
2204                                                 in_height < out_height * 2)
2205                                 *five_taps = false;
2206                 if (!*five_taps)
2207                         *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2208                                         in_height, out_width, out_height,
2209                                         mem_to_mem);
2210
2211                 error = (error || in_width > maxsinglelinewidth * 2 ||
2212                         (in_width > maxsinglelinewidth && *five_taps) ||
2213                         !*core_clk || *core_clk > dispc_core_clk_rate());
2214                 if (error) {
2215                         if (*decim_x == *decim_y) {
2216                                 *decim_x = min_factor;
2217                                 ++*decim_y;
2218                         } else {
2219                                 swap(*decim_x, *decim_y);
2220                                 if (*decim_x < *decim_y)
2221                                         ++*decim_x;
2222                         }
2223                 }
2224         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2225
2226         if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, width,
2227                                 height, out_width, out_height)){
2228                         DSSERR("horizontal timing too tight\n");
2229                         return -EINVAL;
2230         }
2231
2232         if (in_width > (maxsinglelinewidth * 2)) {
2233                 DSSERR("Cannot setup scaling");
2234                 DSSERR("width exceeds maximum width possible");
2235                 return -EINVAL;
2236         }
2237
2238         if (in_width > maxsinglelinewidth && *five_taps) {
2239                 DSSERR("cannot setup scaling with five taps");
2240                 return -EINVAL;
2241         }
2242         return 0;
2243 }
2244
2245 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2246                 const struct omap_video_timings *mgr_timings,
2247                 u16 width, u16 height, u16 out_width, u16 out_height,
2248                 enum omap_color_mode color_mode, bool *five_taps,
2249                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2250                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2251 {
2252         u16 in_width, in_width_max;
2253         int decim_x_min = *decim_x;
2254         u16 in_height = DIV_ROUND_UP(height, *decim_y);
2255         const int maxsinglelinewidth =
2256                                 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2257         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2258
2259         if (mem_to_mem) {
2260                 in_width_max = out_width * maxdownscale;
2261         } else {
2262                 in_width_max = dispc_core_clk_rate() /
2263                                         DIV_ROUND_UP(pclk, out_width);
2264         }
2265
2266         *decim_x = DIV_ROUND_UP(width, in_width_max);
2267
2268         *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2269         if (*decim_x > *x_predecim)
2270                 return -EINVAL;
2271
2272         do {
2273                 in_width = DIV_ROUND_UP(width, *decim_x);
2274         } while (*decim_x <= *x_predecim &&
2275                         in_width > maxsinglelinewidth && ++*decim_x);
2276
2277         if (in_width > maxsinglelinewidth) {
2278                 DSSERR("Cannot scale width exceeds max line width");
2279                 return -EINVAL;
2280         }
2281
2282         *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2283                                 out_width, out_height, mem_to_mem);
2284         return 0;
2285 }
2286
2287 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2288                 enum omap_overlay_caps caps,
2289                 const struct omap_video_timings *mgr_timings,
2290                 u16 width, u16 height, u16 out_width, u16 out_height,
2291                 enum omap_color_mode color_mode, bool *five_taps,
2292                 int *x_predecim, int *y_predecim, u16 pos_x,
2293                 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2294 {
2295         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2296         const int max_decim_limit = 16;
2297         unsigned long core_clk = 0;
2298         int decim_x, decim_y, ret;
2299
2300         if (width == out_width && height == out_height)
2301                 return 0;
2302
2303         if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2304                 return -EINVAL;
2305
2306         if (mem_to_mem) {
2307                 *x_predecim = *y_predecim = 1;
2308         } else {
2309                 *x_predecim = max_decim_limit;
2310                 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2311                                 dss_has_feature(FEAT_BURST_2D)) ?
2312                                 2 : max_decim_limit;
2313         }
2314
2315         if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2316             color_mode == OMAP_DSS_COLOR_CLUT2 ||
2317             color_mode == OMAP_DSS_COLOR_CLUT4 ||
2318             color_mode == OMAP_DSS_COLOR_CLUT8) {
2319                 *x_predecim = 1;
2320                 *y_predecim = 1;
2321                 *five_taps = false;
2322                 return 0;
2323         }
2324
2325         decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2326         decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2327
2328         if (decim_x > *x_predecim || out_width > width * 8)
2329                 return -EINVAL;
2330
2331         if (decim_y > *y_predecim || out_height > height * 8)
2332                 return -EINVAL;
2333
2334         ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2335                 out_width, out_height, color_mode, five_taps,
2336                 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2337                 mem_to_mem);
2338         if (ret)
2339                 return ret;
2340
2341         DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2342         DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
2343
2344         if (!core_clk || core_clk > dispc_core_clk_rate()) {
2345                 DSSERR("failed to set up scaling, "
2346                         "required core clk rate = %lu Hz, "
2347                         "current core clk rate = %lu Hz\n",
2348                         core_clk, dispc_core_clk_rate());
2349                 return -EINVAL;
2350         }
2351
2352         *x_predecim = decim_x;
2353         *y_predecim = decim_y;
2354         return 0;
2355 }
2356
2357 static int dispc_ovl_setup_common(enum omap_plane plane,
2358                 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2359                 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2360                 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2361                 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2362                 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2363                 bool replication, const struct omap_video_timings *mgr_timings,
2364                 bool mem_to_mem)
2365 {
2366         bool five_taps = true;
2367         bool fieldmode = 0;
2368         int r, cconv = 0;
2369         unsigned offset0, offset1;
2370         s32 row_inc;
2371         s32 pix_inc;
2372         u16 frame_width, frame_height;
2373         unsigned int field_offset = 0;
2374         u16 in_height = height;
2375         u16 in_width = width;
2376         int x_predecim = 1, y_predecim = 1;
2377         bool ilace = mgr_timings->interlace;
2378         unsigned long pclk = dispc_plane_pclk_rate(plane);
2379         unsigned long lclk = dispc_plane_lclk_rate(plane);
2380
2381         if (paddr == 0)
2382                 return -EINVAL;
2383
2384         out_width = out_width == 0 ? width : out_width;
2385         out_height = out_height == 0 ? height : out_height;
2386
2387         if (ilace && height == out_height)
2388                 fieldmode = 1;
2389
2390         if (ilace) {
2391                 if (fieldmode)
2392                         in_height /= 2;
2393                 pos_y /= 2;
2394                 out_height /= 2;
2395
2396                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2397                         "out_height %d\n", in_height, pos_y,
2398                         out_height);
2399         }
2400
2401         if (!dss_feat_color_mode_supported(plane, color_mode))
2402                 return -EINVAL;
2403
2404         r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2405                         in_height, out_width, out_height, color_mode,
2406                         &five_taps, &x_predecim, &y_predecim, pos_x,
2407                         rotation_type, mem_to_mem);
2408         if (r)
2409                 return r;
2410
2411         in_width = DIV_ROUND_UP(in_width, x_predecim);
2412         in_height = DIV_ROUND_UP(in_height, y_predecim);
2413
2414         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2415                         color_mode == OMAP_DSS_COLOR_UYVY ||
2416                         color_mode == OMAP_DSS_COLOR_NV12)
2417                 cconv = 1;
2418
2419         if (ilace && !fieldmode) {
2420                 /*
2421                  * when downscaling the bottom field may have to start several
2422                  * source lines below the top field. Unfortunately ACCUI
2423                  * registers will only hold the fractional part of the offset
2424                  * so the integer part must be added to the base address of the
2425                  * bottom field.
2426                  */
2427                 if (!in_height || in_height == out_height)
2428                         field_offset = 0;
2429                 else
2430                         field_offset = in_height / out_height / 2;
2431         }
2432
2433         /* Fields are independent but interleaved in memory. */
2434         if (fieldmode)
2435                 field_offset = 1;
2436
2437         offset0 = 0;
2438         offset1 = 0;
2439         row_inc = 0;
2440         pix_inc = 0;
2441
2442         if (plane == OMAP_DSS_WB) {
2443                 frame_width = out_width;
2444                 frame_height = out_height;
2445         } else {
2446                 frame_width = in_width;
2447                 frame_height = height;
2448         }
2449
2450         if (rotation_type == OMAP_DSS_ROT_TILER)
2451                 calc_tiler_rotation_offset(screen_width, frame_width,
2452                                 color_mode, fieldmode, field_offset,
2453                                 &offset0, &offset1, &row_inc, &pix_inc,
2454                                 x_predecim, y_predecim);
2455         else if (rotation_type == OMAP_DSS_ROT_DMA)
2456                 calc_dma_rotation_offset(rotation, mirror, screen_width,
2457                                 frame_width, frame_height,
2458                                 color_mode, fieldmode, field_offset,
2459                                 &offset0, &offset1, &row_inc, &pix_inc,
2460                                 x_predecim, y_predecim);
2461         else
2462                 calc_vrfb_rotation_offset(rotation, mirror,
2463                                 screen_width, frame_width, frame_height,
2464                                 color_mode, fieldmode, field_offset,
2465                                 &offset0, &offset1, &row_inc, &pix_inc,
2466                                 x_predecim, y_predecim);
2467
2468         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2469                         offset0, offset1, row_inc, pix_inc);
2470
2471         dispc_ovl_set_color_mode(plane, color_mode);
2472
2473         dispc_ovl_configure_burst_type(plane, rotation_type);
2474
2475         dispc_ovl_set_ba0(plane, paddr + offset0);
2476         dispc_ovl_set_ba1(plane, paddr + offset1);
2477
2478         if (OMAP_DSS_COLOR_NV12 == color_mode) {
2479                 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2480                 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2481         }
2482
2483         dispc_ovl_set_row_inc(plane, row_inc);
2484         dispc_ovl_set_pix_inc(plane, pix_inc);
2485
2486         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2487                         in_height, out_width, out_height);
2488
2489         dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2490
2491         dispc_ovl_set_input_size(plane, in_width, in_height);
2492
2493         if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2494                 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2495                                    out_height, ilace, five_taps, fieldmode,
2496                                    color_mode, rotation);
2497                 dispc_ovl_set_output_size(plane, out_width, out_height);
2498                 dispc_ovl_set_vid_color_conv(plane, cconv);
2499         }
2500
2501         dispc_ovl_set_rotation_attrs(plane, rotation, mirror, color_mode);
2502
2503         dispc_ovl_set_zorder(plane, caps, zorder);
2504         dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2505         dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2506
2507         dispc_ovl_enable_replication(plane, caps, replication);
2508
2509         return 0;
2510 }
2511
2512 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2513                 bool replication, const struct omap_video_timings *mgr_timings,
2514                 bool mem_to_mem)
2515 {
2516         int r;
2517         enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2518         enum omap_channel channel;
2519
2520         channel = dispc_ovl_get_channel_out(plane);
2521
2522         DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
2523                 "%dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2524                 plane, oi->paddr, oi->p_uv_addr, oi->screen_width, oi->pos_x,
2525                 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2526                 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2527
2528         r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2529                 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2530                 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2531                 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2532                 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2533
2534         return r;
2535 }
2536
2537 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2538                 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2539 {
2540         int r;
2541         u32 l;
2542         enum omap_plane plane = OMAP_DSS_WB;
2543         const int pos_x = 0, pos_y = 0;
2544         const u8 zorder = 0, global_alpha = 0;
2545         const bool replication = false;
2546         bool truncation;
2547         int in_width = mgr_timings->x_res;
2548         int in_height = mgr_timings->y_res;
2549         enum omap_overlay_caps caps =
2550                 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2551
2552         DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2553                 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2554                 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2555                 wi->mirror);
2556
2557         r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2558                 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2559                 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2560                 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2561                 replication, mgr_timings, mem_to_mem);
2562
2563         switch (wi->color_mode) {
2564         case OMAP_DSS_COLOR_RGB16:
2565         case OMAP_DSS_COLOR_RGB24P:
2566         case OMAP_DSS_COLOR_ARGB16:
2567         case OMAP_DSS_COLOR_RGBA16:
2568         case OMAP_DSS_COLOR_RGB12U:
2569         case OMAP_DSS_COLOR_ARGB16_1555:
2570         case OMAP_DSS_COLOR_XRGB16_1555:
2571         case OMAP_DSS_COLOR_RGBX16:
2572                 truncation = true;
2573                 break;
2574         default:
2575                 truncation = false;
2576                 break;
2577         }
2578
2579         /* setup extra DISPC_WB_ATTRIBUTES */
2580         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2581         l = FLD_MOD(l, truncation, 10, 10);     /* TRUNCATIONENABLE */
2582         l = FLD_MOD(l, mem_to_mem, 19, 19);     /* WRITEBACKMODE */
2583         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2584
2585         return r;