OMAPDSS: DISPC: cleanup lcd/digit enable/disable
[linux-omap-dss2:linux.git] / drivers / video / omap2 / dss / dss.h
1 /*
2  * linux/drivers/video/omap2/dss/dss.h
3  *
4  * Copyright (C) 2009 Nokia Corporation
5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6  *
7  * Some code and ideas taken from drivers/video/omap/ driver
8  * by Imre Deak.
9  *
10  * This program is free software; you can redistribute it and/or modify it
11  * under the terms of the GNU General Public License version 2 as published by
12  * the Free Software Foundation.
13  *
14  * This program is distributed in the hope that it will be useful, but WITHOUT
15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17  * more details.
18  *
19  * You should have received a copy of the GNU General Public License along with
20  * this program.  If not, see <http://www.gnu.org/licenses/>.
21  */
22
23 #ifndef __OMAP2_DSS_H
24 #define __OMAP2_DSS_H
25
26 #ifdef pr_fmt
27 #undef pr_fmt
28 #endif
29
30 #ifdef DSS_SUBSYS_NAME
31 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
32 #else
33 #define pr_fmt(fmt) fmt
34 #endif
35
36 #define DSSDBG(format, ...) \
37         pr_debug(format, ## __VA_ARGS__)
38
39 #ifdef DSS_SUBSYS_NAME
40 #define DSSERR(format, ...) \
41         printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
42         ## __VA_ARGS__)
43 #else
44 #define DSSERR(format, ...) \
45         printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
46 #endif
47
48 #ifdef DSS_SUBSYS_NAME
49 #define DSSINFO(format, ...) \
50         printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
51         ## __VA_ARGS__)
52 #else
53 #define DSSINFO(format, ...) \
54         printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
55 #endif
56
57 #ifdef DSS_SUBSYS_NAME
58 #define DSSWARN(format, ...) \
59         printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
60         ## __VA_ARGS__)
61 #else
62 #define DSSWARN(format, ...) \
63         printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
64 #endif
65
66 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
67    number. For example 7:0 */
68 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
69 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
70 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
71 #define FLD_MOD(orig, val, start, end) \
72         (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
73
74 enum dss_io_pad_mode {
75         DSS_IO_PAD_MODE_RESET,
76         DSS_IO_PAD_MODE_RFBI,
77         DSS_IO_PAD_MODE_BYPASS,
78 };
79
80 enum dss_hdmi_venc_clk_source_select {
81         DSS_VENC_TV_CLK = 0,
82         DSS_HDMI_M_PCLK = 1,
83 };
84
85 enum dss_dsi_content_type {
86         DSS_DSI_CONTENT_DCS,
87         DSS_DSI_CONTENT_GENERIC,
88 };
89
90 enum dss_writeback_channel {
91         DSS_WB_LCD1_MGR =       0,
92         DSS_WB_LCD2_MGR =       1,
93         DSS_WB_TV_MGR =         2,
94         DSS_WB_OVL0 =           3,
95         DSS_WB_OVL1 =           4,
96         DSS_WB_OVL2 =           5,
97         DSS_WB_OVL3 =           6,
98         DSS_WB_LCD3_MGR =       7,
99 };
100
101 struct dss_clock_info {
102         /* rates that we get with dividers below */
103         unsigned long fck;
104
105         /* dividers */
106         u16 fck_div;
107 };
108
109 struct dispc_clock_info {
110         /* rates that we get with dividers below */
111         unsigned long lck;
112         unsigned long pck;
113
114         /* dividers */
115         u16 lck_div;
116         u16 pck_div;
117 };
118
119 struct dsi_clock_info {
120         /* rates that we get with dividers below */
121         unsigned long fint;
122         unsigned long clkin4ddr;
123         unsigned long clkin;
124         unsigned long dsi_pll_hsdiv_dispc_clk;  /* OMAP3: DSI1_PLL_CLK
125                                                  * OMAP4: PLLx_CLK1 */
126         unsigned long dsi_pll_hsdiv_dsi_clk;    /* OMAP3: DSI2_PLL_CLK
127                                                  * OMAP4: PLLx_CLK2 */
128         unsigned long lp_clk;
129
130         /* dividers */
131         u16 regn;
132         u16 regm;
133         u16 regm_dispc; /* OMAP3: REGM3
134                          * OMAP4: REGM4 */
135         u16 regm_dsi;   /* OMAP3: REGM4
136                          * OMAP4: REGM5 */
137         u16 lp_clk_div;
138 };
139
140 struct reg_field {
141         u16 reg;
142         u8 high;
143         u8 low;
144 };
145
146 struct dss_lcd_mgr_config {
147         enum dss_io_pad_mode io_pad_mode;
148
149         bool stallmode;
150         bool fifohandcheck;
151
152         struct dispc_clock_info clock_info;
153
154         int video_port_width;
155
156         int lcden_sig_polarity;
157 };
158
159 struct seq_file;
160 struct platform_device;
161
162 /* core */
163 const char *dss_get_default_display_name(void);
164 struct bus_type *dss_get_bus(void);
165 struct regulator *dss_get_vdds_dsi(void);
166 struct regulator *dss_get_vdds_sdi(void);
167 int dss_get_ctx_loss_count(struct device *dev);
168 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
169 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
170 int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
171 int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));
172
173 struct omap_dss_device *dss_alloc_and_init_device(struct device *parent);
174 int dss_add_device(struct omap_dss_device *dssdev);
175 void dss_unregister_device(struct omap_dss_device *dssdev);
176 void dss_unregister_child_devices(struct device *parent);
177 void dss_put_device(struct omap_dss_device *dssdev);
178 void dss_copy_device_pdata(struct omap_dss_device *dst,
179                 const struct omap_dss_device *src);
180
181 /* apply */
182 void dss_apply_init(void);
183 int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr);
184 int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl);
185 void dss_mgr_start_update(struct omap_overlay_manager *mgr);
186 int omap_dss_mgr_apply(struct omap_overlay_manager *mgr);
187
188 int dss_mgr_enable(struct omap_overlay_manager *mgr);
189 void dss_mgr_disable(struct omap_overlay_manager *mgr);
190 int dss_mgr_set_info(struct omap_overlay_manager *mgr,
191                 struct omap_overlay_manager_info *info);
192 void dss_mgr_get_info(struct omap_overlay_manager *mgr,
193                 struct omap_overlay_manager_info *info);
194 int dss_mgr_set_output(struct omap_overlay_manager *mgr,
195                 struct omap_dss_output *output);
196 int dss_mgr_unset_output(struct omap_overlay_manager *mgr);
197 void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
198                 const struct omap_video_timings *timings);
199 void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
200                 const struct dss_lcd_mgr_config *config);
201 const struct omap_video_timings *dss_mgr_get_timings(struct omap_overlay_manager *mgr);
202
203 bool dss_ovl_is_enabled(struct omap_overlay *ovl);
204 int dss_ovl_enable(struct omap_overlay *ovl);
205 int dss_ovl_disable(struct omap_overlay *ovl);
206 int dss_ovl_set_info(struct omap_overlay *ovl,
207                 struct omap_overlay_info *info);
208 void dss_ovl_get_info(struct omap_overlay *ovl,
209                 struct omap_overlay_info *info);
210 int dss_ovl_set_manager(struct omap_overlay *ovl,
211                 struct omap_overlay_manager *mgr);
212 int dss_ovl_unset_manager(struct omap_overlay *ovl);
213
214 /* output */
215 void dss_register_output(struct omap_dss_output *out);
216 void dss_unregister_output(struct omap_dss_output *out);
217 struct omap_dss_output *omapdss_get_output_from_dssdev(struct omap_dss_device *dssdev);
218
219 /* display */
220 int dss_suspend_all_devices(void);
221 int dss_resume_all_devices(void);
222 void dss_disable_all_devices(void);
223
224 int dss_init_device(struct platform_device *pdev,
225                 struct omap_dss_device *dssdev);
226 void dss_uninit_device(struct platform_device *pdev,
227                 struct omap_dss_device *dssdev);
228
229 /* manager */
230 int dss_init_overlay_managers(struct platform_device *pdev);
231 void dss_uninit_overlay_managers(struct platform_device *pdev);
232 int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
233                 const struct omap_overlay_manager_info *info);
234 int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
235                 const struct omap_video_timings *timings);
236 int dss_mgr_check(struct omap_overlay_manager *mgr,
237                 struct omap_overlay_manager_info *info,
238                 const struct omap_video_timings *mgr_timings,
239                 const struct dss_lcd_mgr_config *config,
240                 struct omap_overlay_info **overlay_infos);
241
242 static inline bool dss_mgr_is_lcd(enum omap_channel id)
243 {
244         if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
245                         id == OMAP_DSS_CHANNEL_LCD3)
246                 return true;
247         else
248                 return false;
249 }
250
251 int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
252                 struct platform_device *pdev);
253 void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
254
255 /* overlay */
256 void dss_init_overlays(struct platform_device *pdev);
257 void dss_uninit_overlays(struct platform_device *pdev);
258 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
259 int dss_ovl_simple_check(struct omap_overlay *ovl,
260                 const struct omap_overlay_info *info);
261 int dss_ovl_check(struct omap_overlay *ovl, struct omap_overlay_info *info,
262                 const struct omap_video_timings *mgr_timings);
263 bool dss_ovl_use_replication(struct dss_lcd_mgr_config config,
264                 enum omap_color_mode mode);
265 int dss_overlay_kobj_init(struct omap_overlay *ovl,
266                 struct platform_device *pdev);
267 void dss_overlay_kobj_uninit(struct omap_overlay *ovl);
268
269 /* DSS */
270 int dss_init_platform_driver(void) __init;
271 void dss_uninit_platform_driver(void);
272
273 int dss_dpi_select_source(enum omap_channel channel);
274 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
275 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
276 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
277 void dss_dump_clocks(struct seq_file *s);
278
279 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
280 void dss_debug_dump_clocks(struct seq_file *s);
281 #endif
282
283 void dss_sdi_init(int datapairs);
284 int dss_sdi_enable(void);
285 void dss_sdi_disable(void);
286
287 void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src);
288 void dss_select_dsi_clk_source(int dsi_module,
289                 enum omap_dss_clk_source clk_src);
290 void dss_select_lcd_clk_source(enum omap_channel channel,
291                 enum omap_dss_clk_source clk_src);
292 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
293 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
294 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
295
296 void dss_set_venc_output(enum omap_dss_venc_type type);
297 void dss_set_dac_pwrdn_bgz(bool enable);
298
299 unsigned long dss_get_dpll4_rate(void);
300 int dss_set_clock_div(struct dss_clock_info *cinfo);
301 int dss_calc_clock_div(unsigned long req_pck, struct dss_clock_info *dss_cinfo,
302                 struct dispc_clock_info *dispc_cinfo);
303
304 /* SDI */
305 int sdi_init_platform_driver(void) __init;
306 void sdi_uninit_platform_driver(void) __exit;
307
308 /* DSI */
309 #ifdef CONFIG_OMAP2_DSS_DSI
310
311 struct dentry;
312 struct file_operations;
313
314 int dsi_init_platform_driver(void) __init;
315 void dsi_uninit_platform_driver(void) __exit;
316
317 int dsi_runtime_get(struct platform_device *dsidev);
318 void dsi_runtime_put(struct platform_device *dsidev);
319
320 void dsi_dump_clocks(struct seq_file *s);
321
322 void dsi_irq_handler(void);
323 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
324
325 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
326 int dsi_pll_set_clock_div(struct platform_device *dsidev,
327                 struct dsi_clock_info *cinfo);
328 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
329                 unsigned long req_pck, struct dsi_clock_info *cinfo,
330                 struct dispc_clock_info *dispc_cinfo);
331 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
332                 bool enable_hsdiv);
333 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
334 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
335 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
336 struct platform_device *dsi_get_dsidev_from_id(int module);
337 #else
338 static inline int dsi_runtime_get(struct platform_device *dsidev)
339 {
340         return 0;
341 }
342 static inline void dsi_runtime_put(struct platform_device *dsidev)
343 {
344 }
345 static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
346 {
347         WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__);
348         return 0;
349 }
350 static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
351 {
352         WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
353         return 0;
354 }
355 static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
356                 struct dsi_clock_info *cinfo)
357 {
358         WARN("%s: DSI not compiled in\n", __func__);
359         return -ENODEV;
360 }
361 static inline int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
362                 unsigned long req_pck,
363                 struct dsi_clock_info *dsi_cinfo,
364                 struct dispc_clock_info *dispc_cinfo)
365 {
366         WARN("%s: DSI not compiled in\n", __func__);
367         return -ENODEV;
368 }
369 static inline int dsi_pll_init(struct platform_device *dsidev,
370                 bool enable_hsclk, bool enable_hsdiv)
371 {
372         WARN("%s: DSI not compiled in\n", __func__);
373         return -ENODEV;
374 }
375 static inline void dsi_pll_uninit(struct platform_device *dsidev,
376                 bool disconnect_lanes)
377 {
378 }
379 static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
380 {
381 }
382 static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
383 {
384 }
385 static inline struct platform_device *dsi_get_dsidev_from_id(int module)
386 {
387         WARN("%s: DSI not compiled in, returning platform device as NULL\n",
388                         __func__);
389         return NULL;
390 }
391 #endif
392
393 /* DPI */
394 int dpi_init_platform_driver(void) __init;
395 void dpi_uninit_platform_driver(void) __exit;
396
397 /* DISPC */
398 int dispc_init_platform_driver(void) __init;
399 void dispc_uninit_platform_driver(void) __exit;
400 void dispc_dump_clocks(struct seq_file *s);
401 void dispc_irq_handler(void);
402
403 int dispc_runtime_get(void);
404 void dispc_runtime_put(void);
405
406 void dispc_enable_sidle(void);
407 void dispc_disable_sidle(void);
408
409 void dispc_lcd_enable_signal(bool enable);
410 void dispc_pck_free_enable(bool enable);
411 void dispc_enable_fifomerge(bool enable);
412 void dispc_enable_gamma_table(bool enable);
413 void dispc_set_loadmode(enum omap_dss_load_mode mode);
414
415 bool dispc_mgr_timings_ok(enum omap_channel channel,
416                 const struct omap_video_timings *timings);
417 unsigned long dispc_fclk_rate(void);
418 void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
419                 struct dispc_clock_info *cinfo);
420 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
421                 struct dispc_clock_info *cinfo);
422
423
424 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
425 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
426                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
427                 bool manual_update);
428 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
429                 bool replication, const struct omap_video_timings *mgr_timings,
430                 bool mem_to_mem);
431 int dispc_ovl_enable(enum omap_plane plane, bool enable);
432 void dispc_ovl_set_channel_out(enum omap_plane plane,
433                 enum omap_channel channel);
434
435 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
436 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
437 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
438 bool dispc_mgr_go_busy(enum omap_channel channel);
439 void dispc_mgr_go(enum omap_channel channel);
440 bool dispc_mgr_is_enabled(enum omap_channel channel);
441 void dispc_mgr_enable(enum omap_channel channel);
442 void dispc_mgr_disable(enum omap_channel channel);
443 bool dispc_mgr_is_channel_enabled(enum omap_channel channel);
444 void dispc_mgr_set_lcd_config(enum omap_channel channel,
445                 const struct dss_lcd_mgr_config *config);
446 void dispc_mgr_set_timings(enum omap_channel channel,
447                 const struct omap_video_timings *timings);
448 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
449 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
450 unsigned long dispc_core_clk_rate(void);
451 void dispc_mgr_set_clock_div(enum omap_channel channel,
452                 const struct dispc_clock_info *cinfo);
453 int dispc_mgr_get_clock_div(enum omap_channel channel,
454                 struct dispc_clock_info *cinfo);
455 void dispc_mgr_setup(enum omap_channel channel,
456                 const struct omap_overlay_manager_info *info);
457
458 u32 dispc_wb_get_framedone_irq(void);
459 bool dispc_wb_go_busy(void);
460 void dispc_wb_go(void);
461 void dispc_wb_enable(bool enable);
462 bool dispc_wb_is_enabled(void);
463 void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
464 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
465                 bool mem_to_mem, const struct omap_video_timings *timings);
466
467 /* VENC */
468 #ifdef CONFIG_OMAP2_DSS_VENC
469 int venc_init_platform_driver(void) __init;
470 void venc_uninit_platform_driver(void) __exit;
471 unsigned long venc_get_pixel_clock(void);
472 #else
473 static inline unsigned long venc_get_pixel_clock(void)
474 {
475         WARN("%s: VENC not compiled in, returning pclk as 0\n", __func__);
476         return 0;
477 }
478 #endif
479 int omapdss_venc_display_enable(struct omap_dss_device *dssdev);
480 void omapdss_venc_display_disable(struct omap_dss_device *dssdev);
481 void omapdss_venc_set_timings(struct omap_dss_device *dssdev,
482                 struct omap_video_timings *timings);
483 int omapdss_venc_check_timings(struct omap_dss_device *dssdev,
484                 struct omap_video_timings *timings);
485 u32 omapdss_venc_get_wss(struct omap_dss_device *dssdev);
486 int omapdss_venc_set_wss(struct omap_dss_device *dssdev, u32 wss);
487 void omapdss_venc_set_type(struct omap_dss_device *dssdev,
488                 enum omap_dss_venc_type type);
489 void omapdss_venc_invert_vid_out_polarity(struct omap_dss_device *dssdev,
490                 bool invert_polarity);
491 int venc_panel_init(void);
492 void venc_panel_exit(void);
493
494 /* HDMI */
495 #ifdef CONFIG_OMAP4_DSS_HDMI
496 int hdmi_init_platform_driver(void) __init;
497 void hdmi_uninit_platform_driver(void) __exit;
498 unsigned long hdmi_get_pixel_clock(void);
499 #else
500 static inline unsigned long hdmi_get_pixel_clock(void)
501 {
502         WARN("%s: HDMI not compiled in, returning pclk as 0\n", __func__);
503         return 0;
504 }
505 #endif
506 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev);
507 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev);
508 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev,
509                 struct omap_video_timings *timings);
510 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
511                                         struct omap_video_timings *timings);
512 int omapdss_hdmi_read_edid(u8 *buf, int len);
513 bool omapdss_hdmi_detect(void);
514 int hdmi_panel_init(void);
515 void hdmi_panel_exit(void);
516 #ifdef CONFIG_OMAP4_DSS_HDMI_AUDIO
517 int hdmi_audio_enable(void);
518 void hdmi_audio_disable(void);
519 int hdmi_audio_start(void);
520 void hdmi_audio_stop(void);
521 bool hdmi_mode_has_audio(void);
522 int hdmi_audio_config(struct omap_dss_audio *audio);
523 #endif
524
525 /* RFBI */
526 int rfbi_init_platform_driver(void) __init;
527 void rfbi_uninit_platform_driver(void) __exit;
528
529
530 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
531 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
532 {
533         int b;
534         for (b = 0; b < 32; ++b) {
535                 if (irqstatus & (1 << b))
536                         irq_arr[b]++;
537         }
538 }
539 #endif
540
541 #endif