OMAPDSS: HDMI: use omapdss_version
[linux-omap-dss2:linux.git] / drivers / video / omap2 / dss / hdmi.c
1 /*
2  * hdmi.c
3  *
4  * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6  * Authors: Yong Zhi
7  *      Mythri pk <mythripk@ti.com>
8  *
9  * This program is free software; you can redistribute it and/or modify it
10  * under the terms of the GNU General Public License version 2 as published by
11  * the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along with
19  * this program.  If not, see <http://www.gnu.org/licenses/>.
20  */
21
22 #define DSS_SUBSYS_NAME "HDMI"
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/err.h>
27 #include <linux/io.h>
28 #include <linux/interrupt.h>
29 #include <linux/mutex.h>
30 #include <linux/delay.h>
31 #include <linux/string.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/clk.h>
35 #include <linux/gpio.h>
36 #include <linux/regulator/consumer.h>
37 #include <video/omapdss.h>
38
39 #include "ti_hdmi.h"
40 #include "dss.h"
41 #include "dss_features.h"
42
43 #define HDMI_WP                 0x0
44 #define HDMI_CORE_SYS           0x400
45 #define HDMI_CORE_AV            0x900
46 #define HDMI_PLLCTRL            0x200
47 #define HDMI_PHY                0x300
48
49 /* HDMI EDID Length move this */
50 #define HDMI_EDID_MAX_LENGTH                    256
51 #define EDID_TIMING_DESCRIPTOR_SIZE             0x12
52 #define EDID_DESCRIPTOR_BLOCK0_ADDRESS          0x36
53 #define EDID_DESCRIPTOR_BLOCK1_ADDRESS          0x80
54 #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR      4
55 #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR      4
56
57 #define HDMI_DEFAULT_REGN 16
58 #define HDMI_DEFAULT_REGM2 1
59
60 static struct {
61         struct mutex lock;
62         struct platform_device *pdev;
63         struct hdmi_ip_data ip_data;
64
65         struct clk *sys_clk;
66         struct regulator *vdda_hdmi_dac_reg;
67
68         int ct_cp_hpd_gpio;
69         int ls_oe_gpio;
70         int hpd_gpio;
71
72         struct omap_dss_output output;
73 } hdmi;
74
75 /*
76  * Logic for the below structure :
77  * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
78  * There is a correspondence between CEA/VESA timing and code, please
79  * refer to section 6.3 in HDMI 1.3 specification for timing code.
80  *
81  * In the below structure, cea_vesa_timings corresponds to all OMAP4
82  * supported CEA and VESA timing values.code_cea corresponds to the CEA
83  * code, It is used to get the timing from cea_vesa_timing array.Similarly
84  * with code_vesa. Code_index is used for back mapping, that is once EDID
85  * is read from the TV, EDID is parsed to find the timing values and then
86  * map it to corresponding CEA or VESA index.
87  */
88
89 static const struct hdmi_config cea_timings[] = {
90         {
91                 { 640, 480, 25200, 96, 16, 48, 2, 10, 33,
92                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
93                         false, },
94                 { 1, HDMI_HDMI },
95         },
96         {
97                 { 720, 480, 27027, 62, 16, 60, 6, 9, 30,
98                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
99                         false, },
100                 { 2, HDMI_HDMI },
101         },
102         {
103                 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
104                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
105                         false, },
106                 { 4, HDMI_HDMI },
107         },
108         {
109                 { 1920, 540, 74250, 44, 88, 148, 5, 2, 15,
110                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
111                         true, },
112                 { 5, HDMI_HDMI },
113         },
114         {
115                 { 1440, 240, 27027, 124, 38, 114, 3, 4, 15,
116                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
117                         true, },
118                 { 6, HDMI_HDMI },
119         },
120         {
121                 { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36,
122                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
123                         false, },
124                 { 16, HDMI_HDMI },
125         },
126         {
127                 { 720, 576, 27000, 64, 12, 68, 5, 5, 39,
128                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
129                         false, },
130                 { 17, HDMI_HDMI },
131         },
132         {
133                 { 1280, 720, 74250, 40, 440, 220, 5, 5, 20,
134                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
135                         false, },
136                 { 19, HDMI_HDMI },
137         },
138         {
139                 { 1920, 540, 74250, 44, 528, 148, 5, 2, 15,
140                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
141                         true, },
142                 { 20, HDMI_HDMI },
143         },
144         {
145                 { 1440, 288, 27000, 126, 24, 138, 3, 2, 19,
146                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
147                         true, },
148                 { 21, HDMI_HDMI },
149         },
150         {
151                 { 1440, 576, 54000, 128, 24, 136, 5, 5, 39,
152                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
153                         false, },
154                 { 29, HDMI_HDMI },
155         },
156         {
157                 { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36,
158                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
159                         false, },
160                 { 31, HDMI_HDMI },
161         },
162         {
163                 { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36,
164                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
165                         false, },
166                 { 32, HDMI_HDMI },
167         },
168         {
169                 { 2880, 480, 108108, 248, 64, 240, 6, 9, 30,
170                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
171                         false, },
172                 { 35, HDMI_HDMI },
173         },
174         {
175                 { 2880, 576, 108000, 256, 48, 272, 5, 5, 39,
176                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
177                         false, },
178                 { 37, HDMI_HDMI },
179         },
180 };
181
182 static const struct hdmi_config vesa_timings[] = {
183 /* VESA From Here */
184         {
185                 { 640, 480, 25175, 96, 16, 48, 2, 11, 31,
186                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
187                         false, },
188                 { 4, HDMI_DVI },
189         },
190         {
191                 { 800, 600, 40000, 128, 40, 88, 4, 1, 23,
192                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
193                         false, },
194                 { 9, HDMI_DVI },
195         },
196         {
197                 { 848, 480, 33750, 112, 16, 112, 8, 6, 23,
198                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
199                         false, },
200                 { 0xE, HDMI_DVI },
201         },
202         {
203                 { 1280, 768, 79500, 128, 64, 192, 7, 3, 20,
204                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
205                         false, },
206                 { 0x17, HDMI_DVI },
207         },
208         {
209                 { 1280, 800, 83500, 128, 72, 200, 6, 3, 22,
210                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
211                         false, },
212                 { 0x1C, HDMI_DVI },
213         },
214         {
215                 { 1360, 768, 85500, 112, 64, 256, 6, 3, 18,
216                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
217                         false, },
218                 { 0x27, HDMI_DVI },
219         },
220         {
221                 { 1280, 960, 108000, 112, 96, 312, 3, 1, 36,
222                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
223                         false, },
224                 { 0x20, HDMI_DVI },
225         },
226         {
227                 { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38,
228                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
229                         false, },
230                 { 0x23, HDMI_DVI },
231         },
232         {
233                 { 1024, 768, 65000, 136, 24, 160, 6, 3, 29,
234                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
235                         false, },
236                 { 0x10, HDMI_DVI },
237         },
238         {
239                 { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32,
240                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
241                         false, },
242                 { 0x2A, HDMI_DVI },
243         },
244         {
245                 { 1440, 900, 106500, 152, 80, 232, 6, 3, 25,
246                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
247                         false, },
248                 { 0x2F, HDMI_DVI },
249         },
250         {
251                 { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30,
252                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
253                         false, },
254                 { 0x3A, HDMI_DVI },
255         },
256         {
257                 { 1366, 768, 85500, 143, 70, 213, 3, 3, 24,
258                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
259                         false, },
260                 { 0x51, HDMI_DVI },
261         },
262         {
263                 { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36,
264                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
265                         false, },
266                 { 0x52, HDMI_DVI },
267         },
268         {
269                 { 1280, 768, 68250, 32, 48, 80, 7, 3, 12,
270                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
271                         false, },
272                 { 0x16, HDMI_DVI },
273         },
274         {
275                 { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23,
276                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
277                         false, },
278                 { 0x29, HDMI_DVI },
279         },
280         {
281                 { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21,
282                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
283                         false, },
284                 { 0x39, HDMI_DVI },
285         },
286         {
287                 { 1280, 800, 79500, 32, 48, 80, 6, 3, 14,
288                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
289                         false, },
290                 { 0x1B, HDMI_DVI },
291         },
292         {
293                 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
294                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
295                         false, },
296                 { 0x55, HDMI_DVI },
297         },
298 };
299
300 static int hdmi_runtime_get(void)
301 {
302         int r;
303
304         DSSDBG("hdmi_runtime_get\n");
305
306         r = pm_runtime_get_sync(&hdmi.pdev->dev);
307         WARN_ON(r < 0);
308         if (r < 0)
309                 return r;
310
311         return 0;
312 }
313
314 static void hdmi_runtime_put(void)
315 {
316         int r;
317
318         DSSDBG("hdmi_runtime_put\n");
319
320         r = pm_runtime_put_sync(&hdmi.pdev->dev);
321         WARN_ON(r < 0 && r != -ENOSYS);
322 }
323
324 static int __init hdmi_init_display(struct omap_dss_device *dssdev)
325 {
326         struct omap_dss_board_info *pdata = hdmi.pdev->dev.platform_data;
327         int r;
328
329         struct gpio gpios[] = {
330                 { hdmi.ct_cp_hpd_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ct_cp_hpd" },
331                 { hdmi.ls_oe_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ls_oe" },
332                 { hdmi.hpd_gpio, GPIOF_DIR_IN, "hdmi_hpd" },
333         };
334
335         DSSDBG("init_display\n");
336
337         dss_init_hdmi_ip_ops(&hdmi.ip_data, pdata->version);
338
339         if (hdmi.vdda_hdmi_dac_reg == NULL) {
340                 struct regulator *reg;
341
342                 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac");
343
344                 if (IS_ERR(reg)) {
345                         DSSERR("can't get VDDA_HDMI_DAC regulator\n");
346                         return PTR_ERR(reg);
347                 }
348
349                 hdmi.vdda_hdmi_dac_reg = reg;
350         }
351
352         r = gpio_request_array(gpios, ARRAY_SIZE(gpios));
353         if (r)
354                 return r;
355
356         return 0;
357 }
358
359 static void __exit hdmi_uninit_display(struct omap_dss_device *dssdev)
360 {
361         DSSDBG("uninit_display\n");
362
363         gpio_free(hdmi.ct_cp_hpd_gpio);
364         gpio_free(hdmi.ls_oe_gpio);
365         gpio_free(hdmi.hpd_gpio);
366 }
367
368 static const struct hdmi_config *hdmi_find_timing(
369                                         const struct hdmi_config *timings_arr,
370                                         int len)
371 {
372         int i;
373
374         for (i = 0; i < len; i++) {
375                 if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code)
376                         return &timings_arr[i];
377         }
378         return NULL;
379 }
380
381 static const struct hdmi_config *hdmi_get_timings(void)
382 {
383        const struct hdmi_config *arr;
384        int len;
385
386        if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) {
387                arr = vesa_timings;
388                len = ARRAY_SIZE(vesa_timings);
389        } else {
390                arr = cea_timings;
391                len = ARRAY_SIZE(cea_timings);
392        }
393
394        return hdmi_find_timing(arr, len);
395 }
396
397 static bool hdmi_timings_compare(struct omap_video_timings *timing1,
398                                 const struct omap_video_timings *timing2)
399 {
400         int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
401
402         if ((timing2->pixel_clock == timing1->pixel_clock) &&
403                 (timing2->x_res == timing1->x_res) &&
404                 (timing2->y_res == timing1->y_res)) {
405
406                 timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
407                 timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
408                 timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
409                 timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
410
411                 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
412                         "timing2_hsync = %d timing2_vsync = %d\n",
413                         timing1_hsync, timing1_vsync,
414                         timing2_hsync, timing2_vsync);
415
416                 if ((timing1_hsync == timing2_hsync) &&
417                         (timing1_vsync == timing2_vsync)) {
418                         return true;
419                 }
420         }
421         return false;
422 }
423
424 static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
425 {
426         int i;
427         struct hdmi_cm cm = {-1};
428         DSSDBG("hdmi_get_code\n");
429
430         for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
431                 if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
432                         cm = cea_timings[i].cm;
433                         goto end;
434                 }
435         }
436         for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
437                 if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
438                         cm = vesa_timings[i].cm;
439                         goto end;
440                 }
441         }
442
443 end:    return cm;
444
445 }
446
447 unsigned long hdmi_get_pixel_clock(void)
448 {
449         /* HDMI Pixel Clock in Mhz */
450         return hdmi.ip_data.cfg.timings.pixel_clock * 1000;
451 }
452
453 static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
454                 struct hdmi_pll_info *pi)
455 {
456         unsigned long clkin, refclk;
457         u32 mf;
458
459         clkin = clk_get_rate(hdmi.sys_clk) / 10000;
460         /*
461          * Input clock is predivided by N + 1
462          * out put of which is reference clk
463          */
464         if (dssdev->clocks.hdmi.regn == 0)
465                 pi->regn = HDMI_DEFAULT_REGN;
466         else
467                 pi->regn = dssdev->clocks.hdmi.regn;
468
469         refclk = clkin / pi->regn;
470
471         if (dssdev->clocks.hdmi.regm2 == 0)
472                 pi->regm2 = HDMI_DEFAULT_REGM2;
473         else
474                 pi->regm2 = dssdev->clocks.hdmi.regm2;
475
476         /*
477          * multiplier is pixel_clk/ref_clk
478          * Multiplying by 100 to avoid fractional part removal
479          */
480         pi->regm = phy * pi->regm2 / refclk;
481
482         /*
483          * fractional multiplier is remainder of the difference between
484          * multiplier and actual phy(required pixel clock thus should be
485          * multiplied by 2^18(262144) divided by the reference clock
486          */
487         mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
488         pi->regmf = pi->regm2 * mf / refclk;
489
490         /*
491          * Dcofreq should be set to 1 if required pixel clock
492          * is greater than 1000MHz
493          */
494         pi->dcofreq = phy > 1000 * 100;
495         pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
496
497         /* Set the reference clock to sysclk reference */
498         pi->refsel = HDMI_REFSEL_SYSCLK;
499
500         DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
501         DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
502 }
503
504 static int hdmi_power_on(struct omap_dss_device *dssdev)
505 {
506         int r;
507         struct omap_video_timings *p;
508         struct omap_overlay_manager *mgr = dssdev->output->manager;
509         unsigned long phy;
510
511         gpio_set_value(hdmi.ct_cp_hpd_gpio, 1);
512         gpio_set_value(hdmi.ls_oe_gpio, 1);
513
514         /* wait 300us after CT_CP_HPD for the 5V power output to reach 90% */
515         udelay(300);
516
517         r = regulator_enable(hdmi.vdda_hdmi_dac_reg);
518         if (r)
519                 goto err_vdac_enable;
520
521         r = hdmi_runtime_get();
522         if (r)
523                 goto err_runtime_get;
524
525         dss_mgr_disable(mgr);
526
527         p = &hdmi.ip_data.cfg.timings;
528
529         DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
530
531         phy = p->pixel_clock;
532
533         hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
534
535         hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
536
537         /* config the PLL and PHY hdmi_set_pll_pwrfirst */
538         r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
539         if (r) {
540                 DSSDBG("Failed to lock PLL\n");
541                 goto err_pll_enable;
542         }
543
544         r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
545         if (r) {
546                 DSSDBG("Failed to start PHY\n");
547                 goto err_phy_enable;
548         }
549
550         hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
551
552         /* Make selection of HDMI in DSS */
553         dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
554
555         /* Select the dispc clock source as PRCM clock, to ensure that it is not
556          * DSI PLL source as the clock selected by DSI PLL might not be
557          * sufficient for the resolution selected / that can be changed
558          * dynamically by user. This can be moved to single location , say
559          * Boardfile.
560          */
561         dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
562
563         /* bypass TV gamma table */
564         dispc_enable_gamma_table(0);
565
566         /* tv size */
567         dss_mgr_set_timings(mgr, p);
568
569         r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data);
570         if (r)
571                 goto err_vid_enable;
572
573         r = dss_mgr_enable(mgr);
574         if (r)
575                 goto err_mgr_enable;
576
577         return 0;
578
579 err_mgr_enable:
580         hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
581 err_vid_enable:
582         hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
583 err_phy_enable:
584         hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
585 err_pll_enable:
586         hdmi_runtime_put();
587 err_runtime_get:
588         regulator_disable(hdmi.vdda_hdmi_dac_reg);
589 err_vdac_enable:
590         gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
591         gpio_set_value(hdmi.ls_oe_gpio, 0);
592         return -EIO;
593 }
594
595 static void hdmi_power_off(struct omap_dss_device *dssdev)
596 {
597         struct omap_overlay_manager *mgr = dssdev->output->manager;
598
599         dss_mgr_disable(mgr);
600
601         hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
602         hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
603         hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
604         hdmi_runtime_put();
605
606         regulator_disable(hdmi.vdda_hdmi_dac_reg);
607
608         gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
609         gpio_set_value(hdmi.ls_oe_gpio, 0);
610 }
611
612 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
613                                         struct omap_video_timings *timings)
614 {
615         struct hdmi_cm cm;
616
617         cm = hdmi_get_code(timings);
618         if (cm.code == -1) {
619                 return -EINVAL;
620         }
621
622         return 0;
623
624 }
625
626 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev,
627                 struct omap_video_timings *timings)
628 {
629         struct hdmi_cm cm;
630         const struct hdmi_config *t;
631
632         mutex_lock(&hdmi.lock);
633
634         cm = hdmi_get_code(timings);
635         hdmi.ip_data.cfg.cm = cm;
636
637         t = hdmi_get_timings();
638         if (t != NULL)
639                 hdmi.ip_data.cfg = *t;
640
641         mutex_unlock(&hdmi.lock);
642 }
643
644 static void hdmi_dump_regs(struct seq_file *s)
645 {
646         mutex_lock(&hdmi.lock);
647
648         if (hdmi_runtime_get())
649                 return;
650
651         hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);
652         hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
653         hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
654         hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
655
656         hdmi_runtime_put();
657         mutex_unlock(&hdmi.lock);
658 }
659
660 int omapdss_hdmi_read_edid(u8 *buf, int len)
661 {
662         int r;
663
664         mutex_lock(&hdmi.lock);
665
666         r = hdmi_runtime_get();
667         BUG_ON(r);
668
669         r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
670
671         hdmi_runtime_put();
672         mutex_unlock(&hdmi.lock);
673
674         return r;
675 }
676
677 bool omapdss_hdmi_detect(void)
678 {
679         int r;
680
681         mutex_lock(&hdmi.lock);
682
683         r = hdmi_runtime_get();
684         BUG_ON(r);
685
686         r = hdmi.ip_data.ops->detect(&hdmi.ip_data);
687
688         hdmi_runtime_put();
689         mutex_unlock(&hdmi.lock);
690
691         return r == 1;
692 }
693
694 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
695 {
696         struct omap_dss_output *out = dssdev->output;
697         int r = 0;
698
699         DSSDBG("ENTER hdmi_display_enable\n");
700
701         mutex_lock(&hdmi.lock);
702
703         if (out == NULL || out->manager == NULL) {
704                 DSSERR("failed to enable display: no output/manager\n");
705                 r = -ENODEV;
706                 goto err0;
707         }
708
709         hdmi.ip_data.hpd_gpio = hdmi.hpd_gpio;
710
711         r = omap_dss_start_device(dssdev);
712         if (r) {
713                 DSSERR("failed to start device\n");
714                 goto err0;
715         }
716
717         r = hdmi_power_on(dssdev);
718         if (r) {
719                 DSSERR("failed to power on device\n");
720                 goto err1;
721         }
722
723         mutex_unlock(&hdmi.lock);
724         return 0;
725
726 err1:
727         omap_dss_stop_device(dssdev);
728 err0:
729         mutex_unlock(&hdmi.lock);
730         return r;
731 }
732
733 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
734 {
735         DSSDBG("Enter hdmi_display_disable\n");
736
737         mutex_lock(&hdmi.lock);
738
739         hdmi_power_off(dssdev);
740
741         omap_dss_stop_device(dssdev);
742
743         mutex_unlock(&hdmi.lock);
744 }
745
746 static int hdmi_get_clocks(struct platform_device *pdev)
747 {
748         struct clk *clk;
749
750         clk = clk_get(&pdev->dev, "sys_clk");
751         if (IS_ERR(clk)) {
752                 DSSERR("can't get sys_clk\n");
753                 return PTR_ERR(clk);
754         }
755
756         hdmi.sys_clk = clk;
757
758         return 0;
759 }
760
761 static void hdmi_put_clocks(void)
762 {
763         if (hdmi.sys_clk)
764                 clk_put(hdmi.sys_clk);
765 }
766
767 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
768 int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts)
769 {
770         u32 deep_color;
771         bool deep_color_correct = false;
772         u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock;
773
774         if (n == NULL || cts == NULL)
775                 return -EINVAL;
776
777         /* TODO: When implemented, query deep color mode here. */
778         deep_color = 100;
779
780         /*
781          * When using deep color, the default N value (as in the HDMI
782          * specification) yields to an non-integer CTS. Hence, we
783          * modify it while keeping the restrictions described in
784          * section 7.2.1 of the HDMI 1.4a specification.
785          */
786         switch (sample_freq) {
787         case 32000:
788         case 48000:
789         case 96000:
790         case 192000:
791                 if (deep_color == 125)
792                         if (pclk == 27027 || pclk == 74250)
793                                 deep_color_correct = true;
794                 if (deep_color == 150)
795                         if (pclk == 27027)
796                                 deep_color_correct = true;
797                 break;
798         case 44100:
799         case 88200:
800         case 176400:
801                 if (deep_color == 125)
802                         if (pclk == 27027)
803                                 deep_color_correct = true;
804                 break;
805         default:
806                 return -EINVAL;
807         }
808
809         if (deep_color_correct) {
810                 switch (sample_freq) {
811                 case 32000:
812                         *n = 8192;
813                         break;
814                 case 44100:
815                         *n = 12544;
816                         break;
817                 case 48000:
818                         *n = 8192;
819                         break;
820                 case 88200:
821                         *n = 25088;
822                         break;
823                 case 96000:
824                         *n = 16384;
825                         break;
826                 case 176400:
827                         *n = 50176;
828                         break;
829                 case 192000:
830                         *n = 32768;
831                         break;
832                 default:
833                         return -EINVAL;
834                 }
835         } else {
836                 switch (sample_freq) {
837                 case 32000:
838                         *n = 4096;
839                         break;
840                 case 44100:
841                         *n = 6272;
842                         break;
843                 case 48000:
844                         *n = 6144;
845                         break;
846                 case 88200:
847                         *n = 12544;
848                         break;
849                 case 96000:
850                         *n = 12288;
851                         break;
852                 case 176400:
853                         *n = 25088;
854                         break;
855                 case 192000:
856                         *n = 24576;
857                         break;
858                 default:
859                         return -EINVAL;
860                 }
861         }
862         /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
863         *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
864
865         return 0;
866 }
867
868 int hdmi_audio_enable(void)
869 {
870         DSSDBG("audio_enable\n");
871
872         return hdmi.ip_data.ops->audio_enable(&hdmi.ip_data);
873 }
874
875 void hdmi_audio_disable(void)
876 {
877         DSSDBG("audio_disable\n");
878
879         hdmi.ip_data.ops->audio_disable(&hdmi.ip_data);
880 }
881
882 int hdmi_audio_start(void)
883 {
884         DSSDBG("audio_start\n");
885
886         return hdmi.ip_data.ops->audio_start(&hdmi.ip_data);
887 }
888
889 void hdmi_audio_stop(void)
890 {
891         DSSDBG("audio_stop\n");
892
893         hdmi.ip_data.ops->audio_stop(&hdmi.ip_data);
894 }
895
896 bool hdmi_mode_has_audio(void)
897 {
898         if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI)
899                 return true;
900         else
901                 return false;
902 }
903
904 int hdmi_audio_config(struct omap_dss_audio *audio)
905 {
906         return hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio);
907 }
908
909 #endif
910
911 static struct omap_dss_device * __init hdmi_find_dssdev(struct platform_device *pdev)
912 {
913         struct omap_dss_board_info *pdata = pdev->dev.platform_data;
914         const char *def_disp_name = dss_get_default_display_name();
915         struct omap_dss_device *def_dssdev;
916         int i;
917
918         def_dssdev = NULL;
919
920         for (i = 0; i < pdata->num_devices; ++i) {
921                 struct omap_dss_device *dssdev = pdata->devices[i];
922
923                 if (dssdev->type != OMAP_DISPLAY_TYPE_HDMI)
924                         continue;
925
926                 if (def_dssdev == NULL)
927                         def_dssdev = dssdev;
928
929                 if (def_disp_name != NULL &&
930                                 strcmp(dssdev->name, def_disp_name) == 0) {
931                         def_dssdev = dssdev;
932                         break;
933                 }
934         }
935
936         return def_dssdev;
937 }
938
939 static void __init hdmi_probe_pdata(struct platform_device *pdev)
940 {
941         struct omap_dss_device *plat_dssdev;
942         struct omap_dss_device *dssdev;
943         struct omap_dss_hdmi_data *priv;
944         int r;
945
946         plat_dssdev = hdmi_find_dssdev(pdev);
947
948         if (!plat_dssdev)
949                 return;
950
951         dssdev = dss_alloc_and_init_device(&pdev->dev);
952         if (!dssdev)
953                 return;
954
955         dss_copy_device_pdata(dssdev, plat_dssdev);
956
957         priv = dssdev->data;
958
959         hdmi.ct_cp_hpd_gpio = priv->ct_cp_hpd_gpio;
960         hdmi.ls_oe_gpio = priv->ls_oe_gpio;
961         hdmi.hpd_gpio = priv->hpd_gpio;
962
963         dssdev->channel = OMAP_DSS_CHANNEL_DIGIT;
964
965         r = hdmi_init_display(dssdev);
966         if (r) {
967                 DSSERR("device %s init failed: %d\n", dssdev->name, r);
968                 dss_put_device(dssdev);
969                 return;
970         }
971
972         r = dss_add_device(dssdev);
973         if (r) {
974                 DSSERR("device %s register failed: %d\n", dssdev->name, r);
975                 dss_put_device(dssdev);
976                 return;
977         }
978 }
979
980 static void __init hdmi_init_output(struct platform_device *pdev)
981 {
982         struct omap_dss_output *out = &hdmi.output;
983
984         out->pdev = pdev;
985         out->id = OMAP_DSS_OUTPUT_HDMI;
986         out->type = OMAP_DISPLAY_TYPE_HDMI;
987
988         dss_register_output(out);
989 }
990
991 static void __exit hdmi_uninit_output(struct platform_device *pdev)
992 {
993         struct omap_dss_output *out = &hdmi.output;
994
995         dss_unregister_output(out);
996 }
997
998 /* HDMI HW IP initialisation */
999 static int __init omapdss_hdmihw_probe(struct platform_device *pdev)
1000 {
1001         struct resource *hdmi_mem;
1002         int r;
1003
1004         hdmi.pdev = pdev;
1005
1006         mutex_init(&hdmi.lock);
1007
1008         hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
1009         if (!hdmi_mem) {
1010                 DSSERR("can't get IORESOURCE_MEM HDMI\n");
1011                 return -EINVAL;
1012         }
1013
1014         /* Base address taken from platform */
1015         hdmi.ip_data.base_wp = ioremap(hdmi_mem->start,
1016                                                 resource_size(hdmi_mem));
1017         if (!hdmi.ip_data.base_wp) {
1018                 DSSERR("can't ioremap WP\n");
1019                 return -ENOMEM;
1020         }
1021
1022         r = hdmi_get_clocks(pdev);
1023         if (r) {
1024                 iounmap(hdmi.ip_data.base_wp);
1025                 return r;
1026         }
1027
1028         pm_runtime_enable(&pdev->dev);
1029
1030         hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
1031         hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
1032         hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
1033         hdmi.ip_data.phy_offset = HDMI_PHY;
1034
1035         mutex_init(&hdmi.ip_data.lock);
1036
1037         hdmi_panel_init();
1038
1039         dss_debugfs_create_file("hdmi", hdmi_dump_regs);
1040
1041         hdmi_init_output(pdev);
1042
1043         hdmi_probe_pdata(pdev);
1044
1045         return 0;
1046 }
1047
1048 static int __exit hdmi_remove_child(struct device *dev, void *data)
1049 {
1050         struct omap_dss_device *dssdev = to_dss_device(dev);
1051         hdmi_uninit_display(dssdev);
1052         return 0;
1053 }
1054
1055 static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
1056 {
1057         device_for_each_child(&pdev->dev, NULL, hdmi_remove_child);
1058
1059         dss_unregister_child_devices(&pdev->dev);
1060
1061         hdmi_panel_exit();
1062
1063         hdmi_uninit_output(pdev);
1064
1065         pm_runtime_disable(&pdev->dev);
1066
1067         hdmi_put_clocks();
1068
1069         iounmap(hdmi.ip_data.base_wp);
1070
1071         return 0;
1072 }
1073
1074 static int hdmi_runtime_suspend(struct device *dev)
1075 {
1076         clk_disable_unprepare(hdmi.sys_clk);
1077
1078         dispc_runtime_put();
1079
1080         return 0;
1081 }
1082
1083 static int hdmi_runtime_resume(struct device *dev)
1084 {
1085         int r;
1086
1087         r = dispc_runtime_get();
1088         if (r < 0)
1089                 return r;
1090
1091         clk_prepare_enable(hdmi.sys_clk);
1092
1093         return 0;
1094 }
1095
1096 static const struct dev_pm_ops hdmi_pm_ops = {
1097         .runtime_suspend = hdmi_runtime_suspend,
1098         .runtime_resume = hdmi_runtime_resume,
1099 };
1100
1101 static struct platform_driver omapdss_hdmihw_driver = {
1102         .remove         = __exit_p(omapdss_hdmihw_remove),
1103         .driver         = {
1104                 .name   = "omapdss_hdmi",
1105                 .owner  = THIS_MODULE,
1106                 .pm     = &hdmi_pm_ops,
1107         },
1108 };
1109
1110 int __init hdmi_init_platform_driver(void)
1111 {
1112         return platform_driver_probe(&omapdss_hdmihw_driver, omapdss_hdmihw_probe);
1113 }
1114
1115 void __exit hdmi_uninit_platform_driver(void)
1116 {
1117         platform_driver_unregister(&omapdss_hdmihw_driver);
1118 }