drm/nouveau/pm: implement DDR2/DDR3/GDDR3/GDDR5 MR generation and validation
authorRoy Spliet <r.spliet@student.tudelft.nl>
Mon, 9 Jan 2012 05:23:07 +0000 (15:23 +1000)
committerMartin Peres <martin.peres@labri.fr>
Thu, 12 Jan 2012 14:10:28 +0000 (15:10 +0100)
commita2a96d0b0a168bc3aa6f0a5e315d4f1d17455cf6
treec0b6a8fe50dc0039c8410db5a7095bcca0a19c1f
parent21739a5dbd67a478d69fabf2f0515da34daace5b
drm/nouveau/pm: implement DDR2/DDR3/GDDR3/GDDR5 MR generation and validation

Roy Spliet:
- Implement according to specs
- Simplify
- Make array for mc latency registers

Martin Peres:
- squash and split all the commits from Roy
- rework following Ben Skeggs comments
- add a form of timings validation
- store the initial timings for later use

Ben Skeggs
- merge slightly modified tidy-up patch with this one

Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl>
Signed-off-by: Martin Peres <martin.peres@labri.fr>
drivers/gpu/drm/nouveau/nouveau_drv.h
drivers/gpu/drm/nouveau/nouveau_mem.c
drivers/gpu/drm/nouveau/nouveau_perf.c
drivers/gpu/drm/nouveau/nouveau_pm.c
drivers/gpu/drm/nouveau/nv50_vram.c