HDMIWA: Add a solution for excessive ACR packet reduction problem 1.10.01.03
authorDeepa Gowdru <deepa.gowdru@ti.com>
Fri, 3 Feb 2012 06:59:55 +0000 (12:29 +0530)
committerSuman Anna <s-anna@ti.com>
Thu, 23 Feb 2012 00:48:18 +0000 (18:48 -0600)
commit64cc513a1a36ce502078da2f06480a33c1f06ae2
tree26d353b82d9c37999a67a9fe7e0c775b481e09e9
parent5246dda1d3e4bbdec2ed7bdd66d9bbd5d30ad5e2
HDMIWA: Add a solution for excessive ACR packet reduction problem

A HW bug in OMAP4430 ES2.0, 2.1 & 2.2 will send excessive ACR Packets
than necessary and leads to AVR inter-op issues and to "CTS Interval"
compliance failures. A SW solution is implemented in Ducati code to
overcome this problem by controlling the ACR_CTRL register using
programmable timer interrupts. The solution is implemented on the BIOS
side due to much more promising interrupt latencies.

Signed-off-by: vamsi krishna k <x0093442@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Axel Castaneda Gonzalez <x0055901@ti.com>
Signed-off-by: Juan Gutierrez <jgutierrez@ti.com>
src/.gitignore
src/ti/configs/omap4430/DucatiCore0Hdmi.cfg [new file with mode: 0644]
src/ti/examples/srvmgr/package.bld
src/ti/examples/srvmgr/test_omx_core0_hdmi.cfg [new file with mode: 0644]
src/ti/hdmiwa/HdmiWa.c [new file with mode: 0644]
src/ti/hdmiwa/HdmiWa.xdc [new file with mode: 0644]
src/ti/hdmiwa/HdmiWa.xs [new file with mode: 0644]
src/ti/hdmiwa/package.bld [new file with mode: 0644]
src/ti/hdmiwa/package.xdc [new file with mode: 0644]
src/ti/hdmiwa/package.xs [new file with mode: 0644]