Utils: Remove the v1 firmware generator code
[gstreamer-omap:sysbios-rpmsg.git] / src / ti / resources / rsc_table.h.mmap
1 /*
2  *  ======== rsc_table.h ========
3  *
4  *  Include this table in each base image, which is read from remoteproc on
5  *  host side.
6  *
7  *  These values are currently very OMAP4 specific!
8  *
9  */
10
11
12 #ifndef _RSC_TABLE_H_
13 #define _RSC_TABLE_H_
14
15
16
17 /* Ducati Memory Map: */
18 #define L4_44XX_BASE            0x4a000000
19
20 #define L4_PERIPHERAL_L4CFG     (L4_44XX_BASE)
21 #define IPU_PERIPHERAL_L4CFG    0xAA000000
22
23 #define L4_PERIPHERAL_L4PER     0x48000000
24 #define IPU_PERIPHERAL_L4PER    0xA8000000
25
26 #define L4_PERIPHERAL_L4EMU     0x54000000
27 #define IPU_PERIPHERAL_L4EMU    0xB4000000
28
29 #define L3_IVAHD_CONFIG         0x5A000000
30 #define IPU_IVAHD_CONFIG        0xBA000000
31
32 #define L3_IVAHD_SL2            0x5B000000
33 #define IPU_IVAHD_SL2           0xBB000000
34
35 #define L3_TILER_MODE_0_1       0x60000000
36 #define IPU_TILER_MODE_0_1      0x60000000
37
38 #define L3_TILER_MODE_2         0x70000000
39 #define IPU_TILER_MODE_2        0x70000000
40
41 #define L3_TILER_MODE_3         0x78000000
42 #define IPU_TILER_MODE_3        0x78000000
43
44 #define L3_IVAHD_CONFIG         0x5A000000
45 #define IPU_IVAHD_CONFIG        0xBA000000
46
47 #define L3_IVAHD_SL2            0x5B000000
48 #define IPU_IVAHD_SL2           0xBB000000
49
50 #define IPU_MEM_TEXT            0x0
51
52 #define IPU_MEM_DATA            0x80000000
53
54 #define IPU_MEM_IPC             0xA0000000
55
56
57 /* Values taken from arch/arm/plat-omap/include/plat/iommu2.h */
58
59 #define MMU_RAM_ENDIAN_SHIFT    9
60 #define MMU_RAM_ENDIAN_LITTLE   (0 << MMU_RAM_ENDIAN_SHIFT)
61 #define MMU_RAM_ELSZ_SHIFT      7
62 #define MMU_RAM_ELSZ_NONE       (3 << MMU_RAM_ELSZ_SHIFT)
63
64 #define IPU_MEMORY_FLAGS   (MMU_RAM_ENDIAN_LITTLE | MMU_RAM_ELSZ_NONE)
65
66
67 /* TODO:
68  * Remove hardcoded RAM Addresses once we have the PA->VA lookup integrated.
69  * IPC region should not be hard-coded. Text area is also not hard-coded since
70  * VA to PA translation is not required. */
71 #define PHYS_MEM_DATA           0xB9800000
72
73 /* Size constants must match those used on host: include/asm-generic/sizes.h */
74 #define SZ_1M                           0x00100000
75 #define SZ_2M                           0x00200000
76 #define SZ_4M                           0x00400000
77 #define SZ_8M                           0x00800000
78 #define SZ_16M                          0x01000000
79 #define SZ_32M                          0x02000000
80 #define SZ_64M                          0x04000000
81 #define SZ_128M                         0x08000000
82 #define SZ_256M                         0x10000000
83 #define SZ_512M                         0x20000000
84
85 /* Resource info: Must match include/linux/remoteproc.h: */
86 #define TYPE_CARVEOUT    0
87 #define TYPE_DEVMEM      1
88 #define TYPE_DEVICE      2
89 #define TYPE_IRQ         3
90 #define TYPE_TRACE       4
91 #define TYPE_ENTRYPOINT  5
92
93 struct resource {
94     u32 type;
95     u32 da_low;       /* Device (Ducati virtual) Address */
96     u32 da_high;
97     u32 pa_low;       /* Physical Address */
98     u32 pa_high;
99     u32 size;
100     u32 flags;
101     char name[48];
102 };
103
104 #pragma DATA_SECTION(resources, ".resource_table")
105 #pragma DATA_ALIGN(resources, 4096)
106 struct resource resources[] = {
107     { TYPE_TRACE, 0, 0, 0, 0, 0x8000, IPU_MEMORY_FLAGS, "0" },
108     { TYPE_TRACE, 1, 0, 0, 0, 0x8000, IPU_MEMORY_FLAGS, "1" },
109     { TYPE_ENTRYPOINT, 0, 0, 0, 0, 0, IPU_MEMORY_FLAGS, "0" },
110     { TYPE_ENTRYPOINT, 1, 0, 0, 0, 0, IPU_MEMORY_FLAGS, "1" },
111     { TYPE_DEVMEM, IPU_TILER_MODE_0_1, 0, L3_TILER_MODE_0_1, 0, SZ_256M,
112        IPU_MEMORY_FLAGS, "IPU_TILER_MODE_0_1" },
113     { TYPE_DEVMEM, IPU_TILER_MODE_2, 0, L3_TILER_MODE_2, 0, SZ_128M,
114        IPU_MEMORY_FLAGS, "IPU_TILER_MODE_2" },
115     { TYPE_DEVMEM, IPU_TILER_MODE_3, 0, L3_TILER_MODE_3, 0, SZ_128M,
116        IPU_MEMORY_FLAGS, "IPU_TILER_MODE_3" },
117     { TYPE_CARVEOUT, IPU_MEM_DATA, 0, PHYS_MEM_DATA, 0, SZ_1M * 96,
118        IPU_MEMORY_FLAGS, "IPU_MEM_DATA" },
119     { TYPE_DEVMEM, IPU_PERIPHERAL_L4CFG, 0, L4_PERIPHERAL_L4CFG, 0, SZ_16M,
120        IPU_MEMORY_FLAGS, "IPU_PERIPHERAL_L4CFG" },
121     { TYPE_DEVMEM, IPU_PERIPHERAL_L4PER, 0, L4_PERIPHERAL_L4PER, 0, SZ_16M,
122        IPU_MEMORY_FLAGS,"IPU_PERIPHERAL_L4PER" },
123     { TYPE_DEVMEM, IPU_IVAHD_CONFIG, 0, L3_IVAHD_CONFIG, 0, SZ_16M,
124        IPU_MEMORY_FLAGS, "IPU_IVAHD_CONFIG" },
125     { TYPE_DEVMEM, IPU_IVAHD_SL2, 0, L3_IVAHD_SL2, 0, SZ_16M,
126        IPU_MEMORY_FLAGS, "IPU_IVAHD_SL2" },
127     { TYPE_CARVEOUT, IPU_MEM_TEXT, 0, 0, 0, SZ_4M, IPU_MEMORY_FLAGS, "IPU_MEM_TEXT" },
128     { TYPE_CARVEOUT, IPU_MEM_IPC,  0, 0, 0, SZ_1M, IPU_MEMORY_FLAGS, "IPU_MEM_IPC"  },
129 };
130
131 #endif // _RSC_TABLE_H_