b43/b43legacy: fix radio LED initialization
[daniel-s-linux-stuff:linux-kernel.git] / drivers / net / wireless / b43 / main.c
1 /*
2
3   Broadcom B43 wireless driver
4
5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6   Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7   Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
8   Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9   Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11   Some parts of the code in this file are derived from the ipw2200
12   driver  Copyright(c) 2003 - 2004 Intel Corporation.
13
14   This program is free software; you can redistribute it and/or modify
15   it under the terms of the GNU General Public License as published by
16   the Free Software Foundation; either version 2 of the License, or
17   (at your option) any later version.
18
19   This program is distributed in the hope that it will be useful,
20   but WITHOUT ANY WARRANTY; without even the implied warranty of
21   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22   GNU General Public License for more details.
23
24   You should have received a copy of the GNU General Public License
25   along with this program; see the file COPYING.  If not, write to
26   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27   Boston, MA 02110-1301, USA.
28
29 */
30
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/firmware.h>
37 #include <linux/wireless.h>
38 #include <linux/workqueue.h>
39 #include <linux/skbuff.h>
40 #include <linux/io.h>
41 #include <linux/dma-mapping.h>
42 #include <asm/unaligned.h>
43
44 #include "b43.h"
45 #include "main.h"
46 #include "debugfs.h"
47 #include "phy_common.h"
48 #include "phy_g.h"
49 #include "phy_n.h"
50 #include "dma.h"
51 #include "pio.h"
52 #include "sysfs.h"
53 #include "xmit.h"
54 #include "lo.h"
55 #include "pcmcia.h"
56
57 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
62
63 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
64
65
66 static int modparam_bad_frames_preempt;
67 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68 MODULE_PARM_DESC(bad_frames_preempt,
69                  "enable(1) / disable(0) Bad Frames Preemption");
70
71 static char modparam_fwpostfix[16];
72 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
74
75 static int modparam_hwpctl;
76 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
78
79 static int modparam_nohwcrypt;
80 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
82
83 static int modparam_qos = 1;
84 module_param_named(qos, modparam_qos, int, 0444);
85 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
86
87 static int modparam_btcoex = 1;
88 module_param_named(btcoex, modparam_btcoex, int, 0444);
89 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
90
91 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
92 module_param_named(verbose, b43_modparam_verbose, int, 0644);
93 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
94
95
96 static const struct ssb_device_id b43_ssb_tbl[] = {
97         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
98         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
99         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
100         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
101         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
102         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
103         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
104         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
105         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
106         SSB_DEVTABLE_END
107 };
108
109 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
110
111 /* Channel and ratetables are shared for all devices.
112  * They can't be const, because ieee80211 puts some precalculated
113  * data in there. This data is the same for all devices, so we don't
114  * get concurrency issues */
115 #define RATETAB_ENT(_rateid, _flags) \
116         {                                                               \
117                 .bitrate        = B43_RATE_TO_BASE100KBPS(_rateid),     \
118                 .hw_value       = (_rateid),                            \
119                 .flags          = (_flags),                             \
120         }
121
122 /*
123  * NOTE: When changing this, sync with xmit.c's
124  *       b43_plcp_get_bitrate_idx_* functions!
125  */
126 static struct ieee80211_rate __b43_ratetable[] = {
127         RATETAB_ENT(B43_CCK_RATE_1MB, 0),
128         RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
129         RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
130         RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
131         RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
132         RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
133         RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
134         RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
135         RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
136         RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
137         RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
138         RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
139 };
140
141 #define b43_a_ratetable         (__b43_ratetable + 4)
142 #define b43_a_ratetable_size    8
143 #define b43_b_ratetable         (__b43_ratetable + 0)
144 #define b43_b_ratetable_size    4
145 #define b43_g_ratetable         (__b43_ratetable + 0)
146 #define b43_g_ratetable_size    12
147
148 #define CHAN4G(_channel, _freq, _flags) {                       \
149         .band                   = IEEE80211_BAND_2GHZ,          \
150         .center_freq            = (_freq),                      \
151         .hw_value               = (_channel),                   \
152         .flags                  = (_flags),                     \
153         .max_antenna_gain       = 0,                            \
154         .max_power              = 30,                           \
155 }
156 static struct ieee80211_channel b43_2ghz_chantable[] = {
157         CHAN4G(1, 2412, 0),
158         CHAN4G(2, 2417, 0),
159         CHAN4G(3, 2422, 0),
160         CHAN4G(4, 2427, 0),
161         CHAN4G(5, 2432, 0),
162         CHAN4G(6, 2437, 0),
163         CHAN4G(7, 2442, 0),
164         CHAN4G(8, 2447, 0),
165         CHAN4G(9, 2452, 0),
166         CHAN4G(10, 2457, 0),
167         CHAN4G(11, 2462, 0),
168         CHAN4G(12, 2467, 0),
169         CHAN4G(13, 2472, 0),
170         CHAN4G(14, 2484, 0),
171 };
172 #undef CHAN4G
173
174 #define CHAN5G(_channel, _flags) {                              \
175         .band                   = IEEE80211_BAND_5GHZ,          \
176         .center_freq            = 5000 + (5 * (_channel)),      \
177         .hw_value               = (_channel),                   \
178         .flags                  = (_flags),                     \
179         .max_antenna_gain       = 0,                            \
180         .max_power              = 30,                           \
181 }
182 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
183         CHAN5G(32, 0),          CHAN5G(34, 0),
184         CHAN5G(36, 0),          CHAN5G(38, 0),
185         CHAN5G(40, 0),          CHAN5G(42, 0),
186         CHAN5G(44, 0),          CHAN5G(46, 0),
187         CHAN5G(48, 0),          CHAN5G(50, 0),
188         CHAN5G(52, 0),          CHAN5G(54, 0),
189         CHAN5G(56, 0),          CHAN5G(58, 0),
190         CHAN5G(60, 0),          CHAN5G(62, 0),
191         CHAN5G(64, 0),          CHAN5G(66, 0),
192         CHAN5G(68, 0),          CHAN5G(70, 0),
193         CHAN5G(72, 0),          CHAN5G(74, 0),
194         CHAN5G(76, 0),          CHAN5G(78, 0),
195         CHAN5G(80, 0),          CHAN5G(82, 0),
196         CHAN5G(84, 0),          CHAN5G(86, 0),
197         CHAN5G(88, 0),          CHAN5G(90, 0),
198         CHAN5G(92, 0),          CHAN5G(94, 0),
199         CHAN5G(96, 0),          CHAN5G(98, 0),
200         CHAN5G(100, 0),         CHAN5G(102, 0),
201         CHAN5G(104, 0),         CHAN5G(106, 0),
202         CHAN5G(108, 0),         CHAN5G(110, 0),
203         CHAN5G(112, 0),         CHAN5G(114, 0),
204         CHAN5G(116, 0),         CHAN5G(118, 0),
205         CHAN5G(120, 0),         CHAN5G(122, 0),
206         CHAN5G(124, 0),         CHAN5G(126, 0),
207         CHAN5G(128, 0),         CHAN5G(130, 0),
208         CHAN5G(132, 0),         CHAN5G(134, 0),
209         CHAN5G(136, 0),         CHAN5G(138, 0),
210         CHAN5G(140, 0),         CHAN5G(142, 0),
211         CHAN5G(144, 0),         CHAN5G(145, 0),
212         CHAN5G(146, 0),         CHAN5G(147, 0),
213         CHAN5G(148, 0),         CHAN5G(149, 0),
214         CHAN5G(150, 0),         CHAN5G(151, 0),
215         CHAN5G(152, 0),         CHAN5G(153, 0),
216         CHAN5G(154, 0),         CHAN5G(155, 0),
217         CHAN5G(156, 0),         CHAN5G(157, 0),
218         CHAN5G(158, 0),         CHAN5G(159, 0),
219         CHAN5G(160, 0),         CHAN5G(161, 0),
220         CHAN5G(162, 0),         CHAN5G(163, 0),
221         CHAN5G(164, 0),         CHAN5G(165, 0),
222         CHAN5G(166, 0),         CHAN5G(168, 0),
223         CHAN5G(170, 0),         CHAN5G(172, 0),
224         CHAN5G(174, 0),         CHAN5G(176, 0),
225         CHAN5G(178, 0),         CHAN5G(180, 0),
226         CHAN5G(182, 0),         CHAN5G(184, 0),
227         CHAN5G(186, 0),         CHAN5G(188, 0),
228         CHAN5G(190, 0),         CHAN5G(192, 0),
229         CHAN5G(194, 0),         CHAN5G(196, 0),
230         CHAN5G(198, 0),         CHAN5G(200, 0),
231         CHAN5G(202, 0),         CHAN5G(204, 0),
232         CHAN5G(206, 0),         CHAN5G(208, 0),
233         CHAN5G(210, 0),         CHAN5G(212, 0),
234         CHAN5G(214, 0),         CHAN5G(216, 0),
235         CHAN5G(218, 0),         CHAN5G(220, 0),
236         CHAN5G(222, 0),         CHAN5G(224, 0),
237         CHAN5G(226, 0),         CHAN5G(228, 0),
238 };
239
240 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
241         CHAN5G(34, 0),          CHAN5G(36, 0),
242         CHAN5G(38, 0),          CHAN5G(40, 0),
243         CHAN5G(42, 0),          CHAN5G(44, 0),
244         CHAN5G(46, 0),          CHAN5G(48, 0),
245         CHAN5G(52, 0),          CHAN5G(56, 0),
246         CHAN5G(60, 0),          CHAN5G(64, 0),
247         CHAN5G(100, 0),         CHAN5G(104, 0),
248         CHAN5G(108, 0),         CHAN5G(112, 0),
249         CHAN5G(116, 0),         CHAN5G(120, 0),
250         CHAN5G(124, 0),         CHAN5G(128, 0),
251         CHAN5G(132, 0),         CHAN5G(136, 0),
252         CHAN5G(140, 0),         CHAN5G(149, 0),
253         CHAN5G(153, 0),         CHAN5G(157, 0),
254         CHAN5G(161, 0),         CHAN5G(165, 0),
255         CHAN5G(184, 0),         CHAN5G(188, 0),
256         CHAN5G(192, 0),         CHAN5G(196, 0),
257         CHAN5G(200, 0),         CHAN5G(204, 0),
258         CHAN5G(208, 0),         CHAN5G(212, 0),
259         CHAN5G(216, 0),
260 };
261 #undef CHAN5G
262
263 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
264         .band           = IEEE80211_BAND_5GHZ,
265         .channels       = b43_5ghz_nphy_chantable,
266         .n_channels     = ARRAY_SIZE(b43_5ghz_nphy_chantable),
267         .bitrates       = b43_a_ratetable,
268         .n_bitrates     = b43_a_ratetable_size,
269 };
270
271 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
272         .band           = IEEE80211_BAND_5GHZ,
273         .channels       = b43_5ghz_aphy_chantable,
274         .n_channels     = ARRAY_SIZE(b43_5ghz_aphy_chantable),
275         .bitrates       = b43_a_ratetable,
276         .n_bitrates     = b43_a_ratetable_size,
277 };
278
279 static struct ieee80211_supported_band b43_band_2GHz = {
280         .band           = IEEE80211_BAND_2GHZ,
281         .channels       = b43_2ghz_chantable,
282         .n_channels     = ARRAY_SIZE(b43_2ghz_chantable),
283         .bitrates       = b43_g_ratetable,
284         .n_bitrates     = b43_g_ratetable_size,
285 };
286
287 static void b43_wireless_core_exit(struct b43_wldev *dev);
288 static int b43_wireless_core_init(struct b43_wldev *dev);
289 static void b43_wireless_core_stop(struct b43_wldev *dev);
290 static int b43_wireless_core_start(struct b43_wldev *dev);
291
292 static int b43_ratelimit(struct b43_wl *wl)
293 {
294         if (!wl || !wl->current_dev)
295                 return 1;
296         if (b43_status(wl->current_dev) < B43_STAT_STARTED)
297                 return 1;
298         /* We are up and running.
299          * Ratelimit the messages to avoid DoS over the net. */
300         return net_ratelimit();
301 }
302
303 void b43info(struct b43_wl *wl, const char *fmt, ...)
304 {
305         va_list args;
306
307         if (b43_modparam_verbose < B43_VERBOSITY_INFO)
308                 return;
309         if (!b43_ratelimit(wl))
310                 return;
311         va_start(args, fmt);
312         printk(KERN_INFO "b43-%s: ",
313                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
314         vprintk(fmt, args);
315         va_end(args);
316 }
317
318 void b43err(struct b43_wl *wl, const char *fmt, ...)
319 {
320         va_list args;
321
322         if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
323                 return;
324         if (!b43_ratelimit(wl))
325                 return;
326         va_start(args, fmt);
327         printk(KERN_ERR "b43-%s ERROR: ",
328                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
329         vprintk(fmt, args);
330         va_end(args);
331 }
332
333 void b43warn(struct b43_wl *wl, const char *fmt, ...)
334 {
335         va_list args;
336
337         if (b43_modparam_verbose < B43_VERBOSITY_WARN)
338                 return;
339         if (!b43_ratelimit(wl))
340                 return;
341         va_start(args, fmt);
342         printk(KERN_WARNING "b43-%s warning: ",
343                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
344         vprintk(fmt, args);
345         va_end(args);
346 }
347
348 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
349 {
350         va_list args;
351
352         if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
353                 return;
354         va_start(args, fmt);
355         printk(KERN_DEBUG "b43-%s debug: ",
356                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
357         vprintk(fmt, args);
358         va_end(args);
359 }
360
361 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
362 {
363         u32 macctl;
364
365         B43_WARN_ON(offset % 4 != 0);
366
367         macctl = b43_read32(dev, B43_MMIO_MACCTL);
368         if (macctl & B43_MACCTL_BE)
369                 val = swab32(val);
370
371         b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
372         mmiowb();
373         b43_write32(dev, B43_MMIO_RAM_DATA, val);
374 }
375
376 static inline void b43_shm_control_word(struct b43_wldev *dev,
377                                         u16 routing, u16 offset)
378 {
379         u32 control;
380
381         /* "offset" is the WORD offset. */
382         control = routing;
383         control <<= 16;
384         control |= offset;
385         b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
386 }
387
388 u32 __b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
389 {
390         u32 ret;
391
392         if (routing == B43_SHM_SHARED) {
393                 B43_WARN_ON(offset & 0x0001);
394                 if (offset & 0x0003) {
395                         /* Unaligned access */
396                         b43_shm_control_word(dev, routing, offset >> 2);
397                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
398                         ret <<= 16;
399                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
400                         ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
401
402                         goto out;
403                 }
404                 offset >>= 2;
405         }
406         b43_shm_control_word(dev, routing, offset);
407         ret = b43_read32(dev, B43_MMIO_SHM_DATA);
408 out:
409         return ret;
410 }
411
412 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
413 {
414         struct b43_wl *wl = dev->wl;
415         unsigned long flags;
416         u32 ret;
417
418         spin_lock_irqsave(&wl->shm_lock, flags);
419         ret = __b43_shm_read32(dev, routing, offset);
420         spin_unlock_irqrestore(&wl->shm_lock, flags);
421
422         return ret;
423 }
424
425 u16 __b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
426 {
427         u16 ret;
428
429         if (routing == B43_SHM_SHARED) {
430                 B43_WARN_ON(offset & 0x0001);
431                 if (offset & 0x0003) {
432                         /* Unaligned access */
433                         b43_shm_control_word(dev, routing, offset >> 2);
434                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
435
436                         goto out;
437                 }
438                 offset >>= 2;
439         }
440         b43_shm_control_word(dev, routing, offset);
441         ret = b43_read16(dev, B43_MMIO_SHM_DATA);
442 out:
443         return ret;
444 }
445
446 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
447 {
448         struct b43_wl *wl = dev->wl;
449         unsigned long flags;
450         u16 ret;
451
452         spin_lock_irqsave(&wl->shm_lock, flags);
453         ret = __b43_shm_read16(dev, routing, offset);
454         spin_unlock_irqrestore(&wl->shm_lock, flags);
455
456         return ret;
457 }
458
459 void __b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
460 {
461         if (routing == B43_SHM_SHARED) {
462                 B43_WARN_ON(offset & 0x0001);
463                 if (offset & 0x0003) {
464                         /* Unaligned access */
465                         b43_shm_control_word(dev, routing, offset >> 2);
466                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
467                                     (value >> 16) & 0xffff);
468                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
469                         b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
470                         return;
471                 }
472                 offset >>= 2;
473         }
474         b43_shm_control_word(dev, routing, offset);
475         b43_write32(dev, B43_MMIO_SHM_DATA, value);
476 }
477
478 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
479 {
480         struct b43_wl *wl = dev->wl;
481         unsigned long flags;
482
483         spin_lock_irqsave(&wl->shm_lock, flags);
484         __b43_shm_write32(dev, routing, offset, value);
485         spin_unlock_irqrestore(&wl->shm_lock, flags);
486 }
487
488 void __b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
489 {
490         if (routing == B43_SHM_SHARED) {
491                 B43_WARN_ON(offset & 0x0001);
492                 if (offset & 0x0003) {
493                         /* Unaligned access */
494                         b43_shm_control_word(dev, routing, offset >> 2);
495                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
496                         return;
497                 }
498                 offset >>= 2;
499         }
500         b43_shm_control_word(dev, routing, offset);
501         b43_write16(dev, B43_MMIO_SHM_DATA, value);
502 }
503
504 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
505 {
506         struct b43_wl *wl = dev->wl;
507         unsigned long flags;
508
509         spin_lock_irqsave(&wl->shm_lock, flags);
510         __b43_shm_write16(dev, routing, offset, value);
511         spin_unlock_irqrestore(&wl->shm_lock, flags);
512 }
513
514 /* Read HostFlags */
515 u64 b43_hf_read(struct b43_wldev *dev)
516 {
517         u64 ret;
518
519         ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
520         ret <<= 16;
521         ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
522         ret <<= 16;
523         ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
524
525         return ret;
526 }
527
528 /* Write HostFlags */
529 void b43_hf_write(struct b43_wldev *dev, u64 value)
530 {
531         u16 lo, mi, hi;
532
533         lo = (value & 0x00000000FFFFULL);
534         mi = (value & 0x0000FFFF0000ULL) >> 16;
535         hi = (value & 0xFFFF00000000ULL) >> 32;
536         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
537         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
538         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
539 }
540
541 /* Read the firmware capabilities bitmask (Opensource firmware only) */
542 static u16 b43_fwcapa_read(struct b43_wldev *dev)
543 {
544         B43_WARN_ON(!dev->fw.opensource);
545         return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
546 }
547
548 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
549 {
550         u32 low, high;
551
552         B43_WARN_ON(dev->dev->id.revision < 3);
553
554         /* The hardware guarantees us an atomic read, if we
555          * read the low register first. */
556         low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
557         high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
558
559         *tsf = high;
560         *tsf <<= 32;
561         *tsf |= low;
562 }
563
564 static void b43_time_lock(struct b43_wldev *dev)
565 {
566         u32 macctl;
567
568         macctl = b43_read32(dev, B43_MMIO_MACCTL);
569         macctl |= B43_MACCTL_TBTTHOLD;
570         b43_write32(dev, B43_MMIO_MACCTL, macctl);
571         /* Commit the write */
572         b43_read32(dev, B43_MMIO_MACCTL);
573 }
574
575 static void b43_time_unlock(struct b43_wldev *dev)
576 {
577         u32 macctl;
578
579         macctl = b43_read32(dev, B43_MMIO_MACCTL);
580         macctl &= ~B43_MACCTL_TBTTHOLD;
581         b43_write32(dev, B43_MMIO_MACCTL, macctl);
582         /* Commit the write */
583         b43_read32(dev, B43_MMIO_MACCTL);
584 }
585
586 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
587 {
588         u32 low, high;
589
590         B43_WARN_ON(dev->dev->id.revision < 3);
591
592         low = tsf;
593         high = (tsf >> 32);
594         /* The hardware guarantees us an atomic write, if we
595          * write the low register first. */
596         b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
597         mmiowb();
598         b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
599         mmiowb();
600 }
601
602 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
603 {
604         b43_time_lock(dev);
605         b43_tsf_write_locked(dev, tsf);
606         b43_time_unlock(dev);
607 }
608
609 static
610 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
611 {
612         static const u8 zero_addr[ETH_ALEN] = { 0 };
613         u16 data;
614
615         if (!mac)
616                 mac = zero_addr;
617
618         offset |= 0x0020;
619         b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
620
621         data = mac[0];
622         data |= mac[1] << 8;
623         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
624         data = mac[2];
625         data |= mac[3] << 8;
626         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
627         data = mac[4];
628         data |= mac[5] << 8;
629         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
630 }
631
632 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
633 {
634         const u8 *mac;
635         const u8 *bssid;
636         u8 mac_bssid[ETH_ALEN * 2];
637         int i;
638         u32 tmp;
639
640         bssid = dev->wl->bssid;
641         mac = dev->wl->mac_addr;
642
643         b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
644
645         memcpy(mac_bssid, mac, ETH_ALEN);
646         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
647
648         /* Write our MAC address and BSSID to template ram */
649         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
650                 tmp = (u32) (mac_bssid[i + 0]);
651                 tmp |= (u32) (mac_bssid[i + 1]) << 8;
652                 tmp |= (u32) (mac_bssid[i + 2]) << 16;
653                 tmp |= (u32) (mac_bssid[i + 3]) << 24;
654                 b43_ram_write(dev, 0x20 + i, tmp);
655         }
656 }
657
658 static void b43_upload_card_macaddress(struct b43_wldev *dev)
659 {
660         b43_write_mac_bssid_templates(dev);
661         b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
662 }
663
664 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
665 {
666         /* slot_time is in usec. */
667         if (dev->phy.type != B43_PHYTYPE_G)
668                 return;
669         b43_write16(dev, 0x684, 510 + slot_time);
670         b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
671 }
672
673 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
674 {
675         b43_set_slot_time(dev, 9);
676 }
677
678 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
679 {
680         b43_set_slot_time(dev, 20);
681 }
682
683 /* Synchronize IRQ top- and bottom-half.
684  * IRQs must be masked before calling this.
685  * This must not be called with the irq_lock held.
686  */
687 static void b43_synchronize_irq(struct b43_wldev *dev)
688 {
689         synchronize_irq(dev->dev->irq);
690         tasklet_kill(&dev->isr_tasklet);
691 }
692
693 /* DummyTransmission function, as documented on
694  * http://bcm-specs.sipsolutions.net/DummyTransmission
695  */
696 void b43_dummy_transmission(struct b43_wldev *dev)
697 {
698         struct b43_wl *wl = dev->wl;
699         struct b43_phy *phy = &dev->phy;
700         unsigned int i, max_loop;
701         u16 value;
702         u32 buffer[5] = {
703                 0x00000000,
704                 0x00D40000,
705                 0x00000000,
706                 0x01000000,
707                 0x00000000,
708         };
709
710         switch (phy->type) {
711         case B43_PHYTYPE_A:
712                 max_loop = 0x1E;
713                 buffer[0] = 0x000201CC;
714                 break;
715         case B43_PHYTYPE_B:
716         case B43_PHYTYPE_G:
717                 max_loop = 0xFA;
718                 buffer[0] = 0x000B846E;
719                 break;
720         default:
721                 B43_WARN_ON(1);
722                 return;
723         }
724
725         spin_lock_irq(&wl->irq_lock);
726         write_lock(&wl->tx_lock);
727
728         for (i = 0; i < 5; i++)
729                 b43_ram_write(dev, i * 4, buffer[i]);
730
731         /* Commit writes */
732         b43_read32(dev, B43_MMIO_MACCTL);
733
734         b43_write16(dev, 0x0568, 0x0000);
735         b43_write16(dev, 0x07C0, 0x0000);
736         value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
737         b43_write16(dev, 0x050C, value);
738         b43_write16(dev, 0x0508, 0x0000);
739         b43_write16(dev, 0x050A, 0x0000);
740         b43_write16(dev, 0x054C, 0x0000);
741         b43_write16(dev, 0x056A, 0x0014);
742         b43_write16(dev, 0x0568, 0x0826);
743         b43_write16(dev, 0x0500, 0x0000);
744         b43_write16(dev, 0x0502, 0x0030);
745
746         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
747                 b43_radio_write16(dev, 0x0051, 0x0017);
748         for (i = 0x00; i < max_loop; i++) {
749                 value = b43_read16(dev, 0x050E);
750                 if (value & 0x0080)
751                         break;
752                 udelay(10);
753         }
754         for (i = 0x00; i < 0x0A; i++) {
755                 value = b43_read16(dev, 0x050E);
756                 if (value & 0x0400)
757                         break;
758                 udelay(10);
759         }
760         for (i = 0x00; i < 0x19; i++) {
761                 value = b43_read16(dev, 0x0690);
762                 if (!(value & 0x0100))
763                         break;
764                 udelay(10);
765         }
766         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
767                 b43_radio_write16(dev, 0x0051, 0x0037);
768
769         write_unlock(&wl->tx_lock);
770         spin_unlock_irq(&wl->irq_lock);
771 }
772
773 static void key_write(struct b43_wldev *dev,
774                       u8 index, u8 algorithm, const u8 *key)
775 {
776         unsigned int i;
777         u32 offset;
778         u16 value;
779         u16 kidx;
780
781         /* Key index/algo block */
782         kidx = b43_kidx_to_fw(dev, index);
783         value = ((kidx << 4) | algorithm);
784         b43_shm_write16(dev, B43_SHM_SHARED,
785                         B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
786
787         /* Write the key to the Key Table Pointer offset */
788         offset = dev->ktp + (index * B43_SEC_KEYSIZE);
789         for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
790                 value = key[i];
791                 value |= (u16) (key[i + 1]) << 8;
792                 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
793         }
794 }
795
796 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
797 {
798         u32 addrtmp[2] = { 0, 0, };
799         u8 per_sta_keys_start = 8;
800
801         if (b43_new_kidx_api(dev))
802                 per_sta_keys_start = 4;
803
804         B43_WARN_ON(index < per_sta_keys_start);
805         /* We have two default TX keys and possibly two default RX keys.
806          * Physical mac 0 is mapped to physical key 4 or 8, depending
807          * on the firmware version.
808          * So we must adjust the index here.
809          */
810         index -= per_sta_keys_start;
811
812         if (addr) {
813                 addrtmp[0] = addr[0];
814                 addrtmp[0] |= ((u32) (addr[1]) << 8);
815                 addrtmp[0] |= ((u32) (addr[2]) << 16);
816                 addrtmp[0] |= ((u32) (addr[3]) << 24);
817                 addrtmp[1] = addr[4];
818                 addrtmp[1] |= ((u32) (addr[5]) << 8);
819         }
820
821         if (dev->dev->id.revision >= 5) {
822                 /* Receive match transmitter address mechanism */
823                 b43_shm_write32(dev, B43_SHM_RCMTA,
824                                 (index * 2) + 0, addrtmp[0]);
825                 b43_shm_write16(dev, B43_SHM_RCMTA,
826                                 (index * 2) + 1, addrtmp[1]);
827         } else {
828                 /* RXE (Receive Engine) and
829                  * PSM (Programmable State Machine) mechanism
830                  */
831                 if (index < 8) {
832                         /* TODO write to RCM 16, 19, 22 and 25 */
833                 } else {
834                         b43_shm_write32(dev, B43_SHM_SHARED,
835                                         B43_SHM_SH_PSM + (index * 6) + 0,
836                                         addrtmp[0]);
837                         b43_shm_write16(dev, B43_SHM_SHARED,
838                                         B43_SHM_SH_PSM + (index * 6) + 4,
839                                         addrtmp[1]);
840                 }
841         }
842 }
843
844 static void do_key_write(struct b43_wldev *dev,
845                          u8 index, u8 algorithm,
846                          const u8 *key, size_t key_len, const u8 *mac_addr)
847 {
848         u8 buf[B43_SEC_KEYSIZE] = { 0, };
849         u8 per_sta_keys_start = 8;
850
851         if (b43_new_kidx_api(dev))
852                 per_sta_keys_start = 4;
853
854         B43_WARN_ON(index >= dev->max_nr_keys);
855         B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
856
857         if (index >= per_sta_keys_start)
858                 keymac_write(dev, index, NULL); /* First zero out mac. */
859         if (key)
860                 memcpy(buf, key, key_len);
861         key_write(dev, index, algorithm, buf);
862         if (index >= per_sta_keys_start)
863                 keymac_write(dev, index, mac_addr);
864
865         dev->key[index].algorithm = algorithm;
866 }
867
868 static int b43_key_write(struct b43_wldev *dev,
869                          int index, u8 algorithm,
870                          const u8 *key, size_t key_len,
871                          const u8 *mac_addr,
872                          struct ieee80211_key_conf *keyconf)
873 {
874         int i;
875         int sta_keys_start;
876
877         if (key_len > B43_SEC_KEYSIZE)
878                 return -EINVAL;
879         for (i = 0; i < dev->max_nr_keys; i++) {
880                 /* Check that we don't already have this key. */
881                 B43_WARN_ON(dev->key[i].keyconf == keyconf);
882         }
883         if (index < 0) {
884                 /* Pairwise key. Get an empty slot for the key. */
885                 if (b43_new_kidx_api(dev))
886                         sta_keys_start = 4;
887                 else
888                         sta_keys_start = 8;
889                 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
890                         if (!dev->key[i].keyconf) {
891                                 /* found empty */
892                                 index = i;
893                                 break;
894                         }
895                 }
896                 if (index < 0) {
897                         b43warn(dev->wl, "Out of hardware key memory\n");
898                         return -ENOSPC;
899                 }
900         } else
901                 B43_WARN_ON(index > 3);
902
903         do_key_write(dev, index, algorithm, key, key_len, mac_addr);
904         if ((index <= 3) && !b43_new_kidx_api(dev)) {
905                 /* Default RX key */
906                 B43_WARN_ON(mac_addr);
907                 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
908         }
909         keyconf->hw_key_idx = index;
910         dev->key[index].keyconf = keyconf;
911
912         return 0;
913 }
914
915 static int b43_key_clear(struct b43_wldev *dev, int index)
916 {
917         if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
918                 return -EINVAL;
919         do_key_write(dev, index, B43_SEC_ALGO_NONE,
920                      NULL, B43_SEC_KEYSIZE, NULL);
921         if ((index <= 3) && !b43_new_kidx_api(dev)) {
922                 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
923                              NULL, B43_SEC_KEYSIZE, NULL);
924         }
925         dev->key[index].keyconf = NULL;
926
927         return 0;
928 }
929
930 static void b43_clear_keys(struct b43_wldev *dev)
931 {
932         int i;
933
934         for (i = 0; i < dev->max_nr_keys; i++)
935                 b43_key_clear(dev, i);
936 }
937
938 static void b43_dump_keymemory(struct b43_wldev *dev)
939 {
940         unsigned int i, index, offset;
941         DECLARE_MAC_BUF(macbuf);
942         u8 mac[ETH_ALEN];
943         u16 algo;
944         u32 rcmta0;
945         u16 rcmta1;
946         u64 hf;
947         struct b43_key *key;
948
949         if (!b43_debug(dev, B43_DBG_KEYS))
950                 return;
951
952         hf = b43_hf_read(dev);
953         b43dbg(dev->wl, "Hardware key memory dump:  USEDEFKEYS=%u\n",
954                !!(hf & B43_HF_USEDEFKEYS));
955         for (index = 0; index < dev->max_nr_keys; index++) {
956                 key = &(dev->key[index]);
957                 printk(KERN_DEBUG "Key slot %02u: %s",
958                        index, (key->keyconf == NULL) ? " " : "*");
959                 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
960                 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
961                         u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
962                         printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
963                 }
964
965                 algo = b43_shm_read16(dev, B43_SHM_SHARED,
966                                       B43_SHM_SH_KEYIDXBLOCK + (index * 2));
967                 printk("   Algo: %04X/%02X", algo, key->algorithm);
968
969                 if (index >= 4) {
970                         rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
971                                                 ((index - 4) * 2) + 0);
972                         rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
973                                                 ((index - 4) * 2) + 1);
974                         *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
975                         *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
976                         printk("   MAC: %s",
977                                print_mac(macbuf, mac));
978                 } else
979                         printk("   DEFAULT KEY");
980                 printk("\n");
981         }
982 }
983
984 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
985 {
986         u32 macctl;
987         u16 ucstat;
988         bool hwps;
989         bool awake;
990         int i;
991
992         B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
993                     (ps_flags & B43_PS_DISABLED));
994         B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
995
996         if (ps_flags & B43_PS_ENABLED) {
997                 hwps = 1;
998         } else if (ps_flags & B43_PS_DISABLED) {
999                 hwps = 0;
1000         } else {
1001                 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1002                 //      and thus is not an AP and we are associated, set bit 25
1003         }
1004         if (ps_flags & B43_PS_AWAKE) {
1005                 awake = 1;
1006         } else if (ps_flags & B43_PS_ASLEEP) {
1007                 awake = 0;
1008         } else {
1009                 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1010                 //      or we are associated, or FIXME, or the latest PS-Poll packet sent was
1011                 //      successful, set bit26
1012         }
1013
1014 /* FIXME: For now we force awake-on and hwps-off */
1015         hwps = 0;
1016         awake = 1;
1017
1018         macctl = b43_read32(dev, B43_MMIO_MACCTL);
1019         if (hwps)
1020                 macctl |= B43_MACCTL_HWPS;
1021         else
1022                 macctl &= ~B43_MACCTL_HWPS;
1023         if (awake)
1024                 macctl |= B43_MACCTL_AWAKE;
1025         else
1026                 macctl &= ~B43_MACCTL_AWAKE;
1027         b43_write32(dev, B43_MMIO_MACCTL, macctl);
1028         /* Commit write */
1029         b43_read32(dev, B43_MMIO_MACCTL);
1030         if (awake && dev->dev->id.revision >= 5) {
1031                 /* Wait for the microcode to wake up. */
1032                 for (i = 0; i < 100; i++) {
1033                         ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1034                                                 B43_SHM_SH_UCODESTAT);
1035                         if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1036                                 break;
1037                         udelay(10);
1038                 }
1039         }
1040 }
1041
1042 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1043 {
1044         u32 tmslow;
1045         u32 macctl;
1046
1047         flags |= B43_TMSLOW_PHYCLKEN;
1048         flags |= B43_TMSLOW_PHYRESET;
1049         ssb_device_enable(dev->dev, flags);
1050         msleep(2);              /* Wait for the PLL to turn on. */
1051
1052         /* Now take the PHY out of Reset again */
1053         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1054         tmslow |= SSB_TMSLOW_FGC;
1055         tmslow &= ~B43_TMSLOW_PHYRESET;
1056         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1057         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
1058         msleep(1);
1059         tmslow &= ~SSB_TMSLOW_FGC;
1060         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1061         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
1062         msleep(1);
1063
1064         /* Turn Analog ON, but only if we already know the PHY-type.
1065          * This protects against very early setup where we don't know the
1066          * PHY-type, yet. wireless_core_reset will be called once again later,
1067          * when we know the PHY-type. */
1068         if (dev->phy.ops)
1069                 dev->phy.ops->switch_analog(dev, 1);
1070
1071         macctl = b43_read32(dev, B43_MMIO_MACCTL);
1072         macctl &= ~B43_MACCTL_GMODE;
1073         if (flags & B43_TMSLOW_GMODE)
1074                 macctl |= B43_MACCTL_GMODE;
1075         macctl |= B43_MACCTL_IHR_ENABLED;
1076         b43_write32(dev, B43_MMIO_MACCTL, macctl);
1077 }
1078
1079 static void handle_irq_transmit_status(struct b43_wldev *dev)
1080 {
1081         u32 v0, v1;
1082         u16 tmp;
1083         struct b43_txstatus stat;
1084
1085         while (1) {
1086                 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1087                 if (!(v0 & 0x00000001))
1088                         break;
1089                 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1090
1091                 stat.cookie = (v0 >> 16);
1092                 stat.seq = (v1 & 0x0000FFFF);
1093                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1094                 tmp = (v0 & 0x0000FFFF);
1095                 stat.frame_count = ((tmp & 0xF000) >> 12);
1096                 stat.rts_count = ((tmp & 0x0F00) >> 8);
1097                 stat.supp_reason = ((tmp & 0x001C) >> 2);
1098                 stat.pm_indicated = !!(tmp & 0x0080);
1099                 stat.intermediate = !!(tmp & 0x0040);
1100                 stat.for_ampdu = !!(tmp & 0x0020);
1101                 stat.acked = !!(tmp & 0x0002);
1102
1103                 b43_handle_txstatus(dev, &stat);
1104         }
1105 }
1106
1107 static void drain_txstatus_queue(struct b43_wldev *dev)
1108 {
1109         u32 dummy;
1110
1111         if (dev->dev->id.revision < 5)
1112                 return;
1113         /* Read all entries from the microcode TXstatus FIFO
1114          * and throw them away.
1115          */
1116         while (1) {
1117                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1118                 if (!(dummy & 0x00000001))
1119                         break;
1120                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1121         }
1122 }
1123
1124 static u32 b43_jssi_read(struct b43_wldev *dev)
1125 {
1126         u32 val = 0;
1127
1128         val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1129         val <<= 16;
1130         val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1131
1132         return val;
1133 }
1134
1135 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1136 {
1137         b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1138         b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1139 }
1140
1141 static void b43_generate_noise_sample(struct b43_wldev *dev)
1142 {
1143         b43_jssi_write(dev, 0x7F7F7F7F);
1144         b43_write32(dev, B43_MMIO_MACCMD,
1145                     b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1146 }
1147
1148 static void b43_calculate_link_quality(struct b43_wldev *dev)
1149 {
1150         /* Top half of Link Quality calculation. */
1151
1152         if (dev->phy.type != B43_PHYTYPE_G)
1153                 return;
1154         if (dev->noisecalc.calculation_running)
1155                 return;
1156         dev->noisecalc.calculation_running = 1;
1157         dev->noisecalc.nr_samples = 0;
1158
1159         b43_generate_noise_sample(dev);
1160 }
1161
1162 static void handle_irq_noise(struct b43_wldev *dev)
1163 {
1164         struct b43_phy_g *phy = dev->phy.g;
1165         u16 tmp;
1166         u8 noise[4];
1167         u8 i, j;
1168         s32 average;
1169
1170         /* Bottom half of Link Quality calculation. */
1171
1172         if (dev->phy.type != B43_PHYTYPE_G)
1173                 return;
1174
1175         /* Possible race condition: It might be possible that the user
1176          * changed to a different channel in the meantime since we
1177          * started the calculation. We ignore that fact, since it's
1178          * not really that much of a problem. The background noise is
1179          * an estimation only anyway. Slightly wrong results will get damped
1180          * by the averaging of the 8 sample rounds. Additionally the
1181          * value is shortlived. So it will be replaced by the next noise
1182          * calculation round soon. */
1183
1184         B43_WARN_ON(!dev->noisecalc.calculation_running);
1185         *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1186         if (noise[0] == 0x7F || noise[1] == 0x7F ||
1187             noise[2] == 0x7F || noise[3] == 0x7F)
1188                 goto generate_new;
1189
1190         /* Get the noise samples. */
1191         B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1192         i = dev->noisecalc.nr_samples;
1193         noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1194         noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1195         noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1196         noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1197         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1198         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1199         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1200         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1201         dev->noisecalc.nr_samples++;
1202         if (dev->noisecalc.nr_samples == 8) {
1203                 /* Calculate the Link Quality by the noise samples. */
1204                 average = 0;
1205                 for (i = 0; i < 8; i++) {
1206                         for (j = 0; j < 4; j++)
1207                                 average += dev->noisecalc.samples[i][j];
1208                 }
1209                 average /= (8 * 4);
1210                 average *= 125;
1211                 average += 64;
1212                 average /= 128;
1213                 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1214                 tmp = (tmp / 128) & 0x1F;
1215                 if (tmp >= 8)
1216                         average += 2;
1217                 else
1218                         average -= 25;
1219                 if (tmp == 8)
1220                         average -= 72;
1221                 else
1222                         average -= 48;
1223
1224                 dev->stats.link_noise = average;
1225                 dev->noisecalc.calculation_running = 0;
1226                 return;
1227         }
1228 generate_new:
1229         b43_generate_noise_sample(dev);
1230 }
1231
1232 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1233 {
1234         if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1235                 ///TODO: PS TBTT
1236         } else {
1237                 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1238                         b43_power_saving_ctl_bits(dev, 0);
1239         }
1240         if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1241                 dev->dfq_valid = 1;
1242 }
1243
1244 static void handle_irq_atim_end(struct b43_wldev *dev)
1245 {
1246         if (dev->dfq_valid) {
1247                 b43_write32(dev, B43_MMIO_MACCMD,
1248                             b43_read32(dev, B43_MMIO_MACCMD)
1249                             | B43_MACCMD_DFQ_VALID);
1250                 dev->dfq_valid = 0;
1251         }
1252 }
1253
1254 static void handle_irq_pmq(struct b43_wldev *dev)
1255 {
1256         u32 tmp;
1257
1258         //TODO: AP mode.
1259
1260         while (1) {
1261                 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1262                 if (!(tmp & 0x00000008))
1263                         break;
1264         }
1265         /* 16bit write is odd, but correct. */
1266         b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1267 }
1268
1269 static void b43_write_template_common(struct b43_wldev *dev,
1270                                       const u8 *data, u16 size,
1271                                       u16 ram_offset,
1272                                       u16 shm_size_offset, u8 rate)
1273 {
1274         u32 i, tmp;
1275         struct b43_plcp_hdr4 plcp;
1276
1277         plcp.data = 0;
1278         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1279         b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1280         ram_offset += sizeof(u32);
1281         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1282          * So leave the first two bytes of the next write blank.
1283          */
1284         tmp = (u32) (data[0]) << 16;
1285         tmp |= (u32) (data[1]) << 24;
1286         b43_ram_write(dev, ram_offset, tmp);
1287         ram_offset += sizeof(u32);
1288         for (i = 2; i < size; i += sizeof(u32)) {
1289                 tmp = (u32) (data[i + 0]);
1290                 if (i + 1 < size)
1291                         tmp |= (u32) (data[i + 1]) << 8;
1292                 if (i + 2 < size)
1293                         tmp |= (u32) (data[i + 2]) << 16;
1294                 if (i + 3 < size)
1295                         tmp |= (u32) (data[i + 3]) << 24;
1296                 b43_ram_write(dev, ram_offset + i - 2, tmp);
1297         }
1298         b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1299                         size + sizeof(struct b43_plcp_hdr6));
1300 }
1301
1302 /* Check if the use of the antenna that ieee80211 told us to
1303  * use is possible. This will fall back to DEFAULT.
1304  * "antenna_nr" is the antenna identifier we got from ieee80211. */
1305 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1306                                   u8 antenna_nr)
1307 {
1308         u8 antenna_mask;
1309
1310         if (antenna_nr == 0) {
1311                 /* Zero means "use default antenna". That's always OK. */
1312                 return 0;
1313         }
1314
1315         /* Get the mask of available antennas. */
1316         if (dev->phy.gmode)
1317                 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1318         else
1319                 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1320
1321         if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1322                 /* This antenna is not available. Fall back to default. */
1323                 return 0;
1324         }
1325
1326         return antenna_nr;
1327 }
1328
1329 /* Convert a b43 antenna number value to the PHY TX control value. */
1330 static u16 b43_antenna_to_phyctl(int antenna)
1331 {
1332         switch (antenna) {
1333         case B43_ANTENNA0:
1334                 return B43_TXH_PHY_ANT0;
1335         case B43_ANTENNA1:
1336                 return B43_TXH_PHY_ANT1;
1337         case B43_ANTENNA2:
1338                 return B43_TXH_PHY_ANT2;
1339         case B43_ANTENNA3:
1340                 return B43_TXH_PHY_ANT3;
1341         case B43_ANTENNA_AUTO:
1342                 return B43_TXH_PHY_ANT01AUTO;
1343         }
1344         B43_WARN_ON(1);
1345         return 0;
1346 }
1347
1348 static void b43_write_beacon_template(struct b43_wldev *dev,
1349                                       u16 ram_offset,
1350                                       u16 shm_size_offset)
1351 {
1352         unsigned int i, len, variable_len;
1353         const struct ieee80211_mgmt *bcn;
1354         const u8 *ie;
1355         bool tim_found = 0;
1356         unsigned int rate;
1357         u16 ctl;
1358         int antenna;
1359         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1360
1361         bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1362         len = min((size_t) dev->wl->current_beacon->len,
1363                   0x200 - sizeof(struct b43_plcp_hdr6));
1364         rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1365
1366         b43_write_template_common(dev, (const u8 *)bcn,
1367                                   len, ram_offset, shm_size_offset, rate);
1368
1369         /* Write the PHY TX control parameters. */
1370         antenna = B43_ANTENNA_DEFAULT;
1371         antenna = b43_antenna_to_phyctl(antenna);
1372         ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1373         /* We can't send beacons with short preamble. Would get PHY errors. */
1374         ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1375         ctl &= ~B43_TXH_PHY_ANT;
1376         ctl &= ~B43_TXH_PHY_ENC;
1377         ctl |= antenna;
1378         if (b43_is_cck_rate(rate))
1379                 ctl |= B43_TXH_PHY_ENC_CCK;
1380         else
1381                 ctl |= B43_TXH_PHY_ENC_OFDM;
1382         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1383
1384         /* Find the position of the TIM and the DTIM_period value
1385          * and write them to SHM. */
1386         ie = bcn->u.beacon.variable;
1387         variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1388         for (i = 0; i < variable_len - 2; ) {
1389                 uint8_t ie_id, ie_len;
1390
1391                 ie_id = ie[i];
1392                 ie_len = ie[i + 1];
1393                 if (ie_id == 5) {
1394                         u16 tim_position;
1395                         u16 dtim_period;
1396                         /* This is the TIM Information Element */
1397
1398                         /* Check whether the ie_len is in the beacon data range. */
1399                         if (variable_len < ie_len + 2 + i)
1400                                 break;
1401                         /* A valid TIM is at least 4 bytes long. */
1402                         if (ie_len < 4)
1403                                 break;
1404                         tim_found = 1;
1405
1406                         tim_position = sizeof(struct b43_plcp_hdr6);
1407                         tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1408                         tim_position += i;
1409
1410                         dtim_period = ie[i + 3];
1411
1412                         b43_shm_write16(dev, B43_SHM_SHARED,
1413                                         B43_SHM_SH_TIMBPOS, tim_position);
1414                         b43_shm_write16(dev, B43_SHM_SHARED,
1415                                         B43_SHM_SH_DTIMPER, dtim_period);
1416                         break;
1417                 }
1418                 i += ie_len + 2;
1419         }
1420         if (!tim_found) {
1421                 /*
1422                  * If ucode wants to modify TIM do it behind the beacon, this
1423                  * will happen, for example, when doing mesh networking.
1424                  */
1425                 b43_shm_write16(dev, B43_SHM_SHARED,
1426                                 B43_SHM_SH_TIMBPOS,
1427                                 len + sizeof(struct b43_plcp_hdr6));
1428                 b43_shm_write16(dev, B43_SHM_SHARED,
1429                                 B43_SHM_SH_DTIMPER, 0);
1430         }
1431         b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1432 }
1433
1434 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1435                                       u16 shm_offset, u16 size,
1436                                       struct ieee80211_rate *rate)
1437 {
1438         struct b43_plcp_hdr4 plcp;
1439         u32 tmp;
1440         __le16 dur;
1441
1442         plcp.data = 0;
1443         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1444         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1445                                                dev->wl->vif, size,
1446                                                rate);
1447         /* Write PLCP in two parts and timing for packet transfer */
1448         tmp = le32_to_cpu(plcp.data);
1449         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1450         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1451         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1452 }
1453
1454 /* Instead of using custom probe response template, this function
1455  * just patches custom beacon template by:
1456  * 1) Changing packet type
1457  * 2) Patching duration field
1458  * 3) Stripping TIM
1459  */
1460 static const u8 *b43_generate_probe_resp(struct b43_wldev *dev,
1461                                          u16 *dest_size,
1462                                          struct ieee80211_rate *rate)
1463 {
1464         const u8 *src_data;
1465         u8 *dest_data;
1466         u16 src_size, elem_size, src_pos, dest_pos;
1467         __le16 dur;
1468         struct ieee80211_hdr *hdr;
1469         size_t ie_start;
1470
1471         src_size = dev->wl->current_beacon->len;
1472         src_data = (const u8 *)dev->wl->current_beacon->data;
1473
1474         /* Get the start offset of the variable IEs in the packet. */
1475         ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1476         B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1477
1478         if (B43_WARN_ON(src_size < ie_start))
1479                 return NULL;
1480
1481         dest_data = kmalloc(src_size, GFP_ATOMIC);
1482         if (unlikely(!dest_data))
1483                 return NULL;
1484
1485         /* Copy the static data and all Information Elements, except the TIM. */
1486         memcpy(dest_data, src_data, ie_start);
1487         src_pos = ie_start;
1488         dest_pos = ie_start;
1489         for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1490                 elem_size = src_data[src_pos + 1] + 2;
1491                 if (src_data[src_pos] == 5) {
1492                         /* This is the TIM. */
1493                         continue;
1494                 }
1495                 memcpy(dest_data + dest_pos, src_data + src_pos,
1496                        elem_size);
1497                 dest_pos += elem_size;
1498         }
1499         *dest_size = dest_pos;
1500         hdr = (struct ieee80211_hdr *)dest_data;
1501
1502         /* Set the frame control. */
1503         hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1504                                          IEEE80211_STYPE_PROBE_RESP);
1505         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1506                                                dev->wl->vif, *dest_size,
1507                                                rate);
1508         hdr->duration_id = dur;
1509
1510         return dest_data;
1511 }
1512
1513 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1514                                           u16 ram_offset,
1515                                           u16 shm_size_offset,
1516                                           struct ieee80211_rate *rate)
1517 {
1518         const u8 *probe_resp_data;
1519         u16 size;
1520
1521         size = dev->wl->current_beacon->len;
1522         probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1523         if (unlikely(!probe_resp_data))
1524                 return;
1525
1526         /* Looks like PLCP headers plus packet timings are stored for
1527          * all possible basic rates
1528          */
1529         b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1530         b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1531         b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1532         b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
1533
1534         size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1535         b43_write_template_common(dev, probe_resp_data,
1536                                   size, ram_offset, shm_size_offset,
1537                                   rate->hw_value);
1538         kfree(probe_resp_data);
1539 }
1540
1541 static void b43_upload_beacon0(struct b43_wldev *dev)
1542 {
1543         struct b43_wl *wl = dev->wl;
1544
1545         if (wl->beacon0_uploaded)
1546                 return;
1547         b43_write_beacon_template(dev, 0x68, 0x18);
1548         /* FIXME: Probe resp upload doesn't really belong here,
1549          *        but we don't use that feature anyway. */
1550         b43_write_probe_resp_template(dev, 0x268, 0x4A,
1551                                       &__b43_ratetable[3]);
1552         wl->beacon0_uploaded = 1;
1553 }
1554
1555 static void b43_upload_beacon1(struct b43_wldev *dev)
1556 {
1557         struct b43_wl *wl = dev->wl;
1558
1559         if (wl->beacon1_uploaded)
1560                 return;
1561         b43_write_beacon_template(dev, 0x468, 0x1A);
1562         wl->beacon1_uploaded = 1;
1563 }
1564
1565 static void handle_irq_beacon(struct b43_wldev *dev)
1566 {
1567         struct b43_wl *wl = dev->wl;
1568         u32 cmd, beacon0_valid, beacon1_valid;
1569
1570         if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1571             !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
1572                 return;
1573
1574         /* This is the bottom half of the asynchronous beacon update. */
1575
1576         /* Ignore interrupt in the future. */
1577         dev->irq_mask &= ~B43_IRQ_BEACON;
1578
1579         cmd = b43_read32(dev, B43_MMIO_MACCMD);
1580         beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1581         beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1582
1583         /* Schedule interrupt manually, if busy. */
1584         if (beacon0_valid && beacon1_valid) {
1585                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1586                 dev->irq_mask |= B43_IRQ_BEACON;
1587                 return;
1588         }
1589
1590         if (unlikely(wl->beacon_templates_virgin)) {
1591                 /* We never uploaded a beacon before.
1592                  * Upload both templates now, but only mark one valid. */
1593                 wl->beacon_templates_virgin = 0;
1594                 b43_upload_beacon0(dev);
1595                 b43_upload_beacon1(dev);
1596                 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1597                 cmd |= B43_MACCMD_BEACON0_VALID;
1598                 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1599         } else {
1600                 if (!beacon0_valid) {
1601                         b43_upload_beacon0(dev);
1602                         cmd = b43_read32(dev, B43_MMIO_MACCMD);
1603                         cmd |= B43_MACCMD_BEACON0_VALID;
1604                         b43_write32(dev, B43_MMIO_MACCMD, cmd);
1605                 } else if (!beacon1_valid) {
1606                         b43_upload_beacon1(dev);
1607                         cmd = b43_read32(dev, B43_MMIO_MACCMD);
1608                         cmd |= B43_MACCMD_BEACON1_VALID;
1609                         b43_write32(dev, B43_MMIO_MACCMD, cmd);
1610                 }
1611         }
1612 }
1613
1614 static void b43_beacon_update_trigger_work(struct work_struct *work)
1615 {
1616         struct b43_wl *wl = container_of(work, struct b43_wl,
1617                                          beacon_update_trigger);
1618         struct b43_wldev *dev;
1619
1620         mutex_lock(&wl->mutex);
1621         dev = wl->current_dev;
1622         if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1623                 spin_lock_irq(&wl->irq_lock);
1624                 /* update beacon right away or defer to irq */
1625                 handle_irq_beacon(dev);
1626                 /* The handler might have updated the IRQ mask. */
1627                 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1628                 mmiowb();
1629                 spin_unlock_irq(&wl->irq_lock);
1630         }
1631         mutex_unlock(&wl->mutex);
1632 }
1633
1634 /* Asynchronously update the packet templates in template RAM.
1635  * Locking: Requires wl->irq_lock to be locked. */
1636 static void b43_update_templates(struct b43_wl *wl)
1637 {
1638         struct sk_buff *beacon;
1639
1640         /* This is the top half of the ansynchronous beacon update.
1641          * The bottom half is the beacon IRQ.
1642          * Beacon update must be asynchronous to avoid sending an
1643          * invalid beacon. This can happen for example, if the firmware
1644          * transmits a beacon while we are updating it. */
1645
1646         /* We could modify the existing beacon and set the aid bit in
1647          * the TIM field, but that would probably require resizing and
1648          * moving of data within the beacon template.
1649          * Simply request a new beacon and let mac80211 do the hard work. */
1650         beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1651         if (unlikely(!beacon))
1652                 return;
1653
1654         if (wl->current_beacon)
1655                 dev_kfree_skb_any(wl->current_beacon);
1656         wl->current_beacon = beacon;
1657         wl->beacon0_uploaded = 0;
1658         wl->beacon1_uploaded = 0;
1659         queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
1660 }
1661
1662 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1663 {
1664         b43_time_lock(dev);
1665         if (dev->dev->id.revision >= 3) {
1666                 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1667                 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1668         } else {
1669                 b43_write16(dev, 0x606, (beacon_int >> 6));
1670                 b43_write16(dev, 0x610, beacon_int);
1671         }
1672         b43_time_unlock(dev);
1673         b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1674 }
1675
1676 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1677 {
1678         u16 reason;
1679
1680         /* Read the register that contains the reason code for the panic. */
1681         reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1682         b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1683
1684         switch (reason) {
1685         default:
1686                 b43dbg(dev->wl, "The panic reason is unknown.\n");
1687                 /* fallthrough */
1688         case B43_FWPANIC_DIE:
1689                 /* Do not restart the controller or firmware.
1690                  * The device is nonfunctional from now on.
1691                  * Restarting would result in this panic to trigger again,
1692                  * so we avoid that recursion. */
1693                 break;
1694         case B43_FWPANIC_RESTART:
1695                 b43_controller_restart(dev, "Microcode panic");
1696                 break;
1697         }
1698 }
1699
1700 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1701 {
1702         unsigned int i, cnt;
1703         u16 reason, marker_id, marker_line;
1704         __le16 *buf;
1705
1706         /* The proprietary firmware doesn't have this IRQ. */
1707         if (!dev->fw.opensource)
1708                 return;
1709
1710         /* Read the register that contains the reason code for this IRQ. */
1711         reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1712
1713         switch (reason) {
1714         case B43_DEBUGIRQ_PANIC:
1715                 b43_handle_firmware_panic(dev);
1716                 break;
1717         case B43_DEBUGIRQ_DUMP_SHM:
1718                 if (!B43_DEBUG)
1719                         break; /* Only with driver debugging enabled. */
1720                 buf = kmalloc(4096, GFP_ATOMIC);
1721                 if (!buf) {
1722                         b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1723                         goto out;
1724                 }
1725                 for (i = 0; i < 4096; i += 2) {
1726                         u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1727                         buf[i / 2] = cpu_to_le16(tmp);
1728                 }
1729                 b43info(dev->wl, "Shared memory dump:\n");
1730                 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1731                                16, 2, buf, 4096, 1);
1732                 kfree(buf);
1733                 break;
1734         case B43_DEBUGIRQ_DUMP_REGS:
1735                 if (!B43_DEBUG)
1736                         break; /* Only with driver debugging enabled. */
1737                 b43info(dev->wl, "Microcode register dump:\n");
1738                 for (i = 0, cnt = 0; i < 64; i++) {
1739                         u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1740                         if (cnt == 0)
1741                                 printk(KERN_INFO);
1742                         printk("r%02u: 0x%04X  ", i, tmp);
1743                         cnt++;
1744                         if (cnt == 6) {
1745                                 printk("\n");
1746                                 cnt = 0;
1747                         }
1748                 }
1749                 printk("\n");
1750                 break;
1751         case B43_DEBUGIRQ_MARKER:
1752                 if (!B43_DEBUG)
1753                         break; /* Only with driver debugging enabled. */
1754                 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1755                                            B43_MARKER_ID_REG);
1756                 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1757                                              B43_MARKER_LINE_REG);
1758                 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1759                         "at line number %u\n",
1760                         marker_id, marker_line);
1761                 break;
1762         default:
1763                 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1764                        reason);
1765         }
1766 out:
1767         /* Acknowledge the debug-IRQ, so the firmware can continue. */
1768         b43_shm_write16(dev, B43_SHM_SCRATCH,
1769                         B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1770 }
1771
1772 /* Interrupt handler bottom-half */
1773 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1774 {
1775         u32 reason;
1776         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1777         u32 merged_dma_reason = 0;
1778         int i;
1779         unsigned long flags;
1780
1781         spin_lock_irqsave(&dev->wl->irq_lock, flags);
1782
1783         B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1784
1785         reason = dev->irq_reason;
1786         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1787                 dma_reason[i] = dev->dma_reason[i];
1788                 merged_dma_reason |= dma_reason[i];
1789         }
1790
1791         if (unlikely(reason & B43_IRQ_MAC_TXERR))
1792                 b43err(dev->wl, "MAC transmission error\n");
1793
1794         if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1795                 b43err(dev->wl, "PHY transmission error\n");
1796                 rmb();
1797                 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1798                         atomic_set(&dev->phy.txerr_cnt,
1799                                    B43_PHY_TX_BADNESS_LIMIT);
1800                         b43err(dev->wl, "Too many PHY TX errors, "
1801                                         "restarting the controller\n");
1802                         b43_controller_restart(dev, "PHY TX errors");
1803                 }
1804         }
1805
1806         if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1807                                           B43_DMAIRQ_NONFATALMASK))) {
1808                 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1809                         b43err(dev->wl, "Fatal DMA error: "
1810                                "0x%08X, 0x%08X, 0x%08X, "
1811                                "0x%08X, 0x%08X, 0x%08X\n",
1812                                dma_reason[0], dma_reason[1],
1813                                dma_reason[2], dma_reason[3],
1814                                dma_reason[4], dma_reason[5]);
1815                         b43_controller_restart(dev, "DMA error");
1816                         mmiowb();
1817                         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1818                         return;
1819                 }
1820                 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1821                         b43err(dev->wl, "DMA error: "
1822                                "0x%08X, 0x%08X, 0x%08X, "
1823                                "0x%08X, 0x%08X, 0x%08X\n",
1824                                dma_reason[0], dma_reason[1],
1825                                dma_reason[2], dma_reason[3],
1826                                dma_reason[4], dma_reason[5]);
1827                 }
1828         }
1829
1830         if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1831                 handle_irq_ucode_debug(dev);
1832         if (reason & B43_IRQ_TBTT_INDI)
1833                 handle_irq_tbtt_indication(dev);
1834         if (reason & B43_IRQ_ATIM_END)
1835                 handle_irq_atim_end(dev);
1836         if (reason & B43_IRQ_BEACON)
1837                 handle_irq_beacon(dev);
1838         if (reason & B43_IRQ_PMQ)
1839                 handle_irq_pmq(dev);
1840         if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1841                 ;/* TODO */
1842         if (reason & B43_IRQ_NOISESAMPLE_OK)
1843                 handle_irq_noise(dev);
1844
1845         /* Check the DMA reason registers for received data. */
1846         if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1847                 if (b43_using_pio_transfers(dev))
1848                         b43_pio_rx(dev->pio.rx_queue);
1849                 else
1850                         b43_dma_rx(dev->dma.rx_ring);
1851         }
1852         B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1853         B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1854         B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1855         B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1856         B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1857
1858         if (reason & B43_IRQ_TX_OK)
1859                 handle_irq_transmit_status(dev);
1860
1861         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1862         mmiowb();
1863         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1864 }
1865
1866 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1867 {
1868         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1869
1870         b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1871         b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1872         b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1873         b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1874         b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1875 /* Unused ring
1876         b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1877 */
1878 }
1879
1880 /* Interrupt handler top-half */
1881 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1882 {
1883         irqreturn_t ret = IRQ_NONE;
1884         struct b43_wldev *dev = dev_id;
1885         u32 reason;
1886
1887         B43_WARN_ON(!dev);
1888
1889         spin_lock(&dev->wl->irq_lock);
1890
1891         if (unlikely(b43_status(dev) < B43_STAT_STARTED)) {
1892                 /* This can only happen on shared IRQ lines. */
1893                 goto out;
1894         }
1895         reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1896         if (reason == 0xffffffff)       /* shared IRQ */
1897                 goto out;
1898         ret = IRQ_HANDLED;
1899         reason &= dev->irq_mask;
1900         if (!reason)
1901                 goto out;
1902
1903         dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1904             & 0x0001DC00;
1905         dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1906             & 0x0000DC00;
1907         dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1908             & 0x0000DC00;
1909         dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1910             & 0x0001DC00;
1911         dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1912             & 0x0000DC00;
1913 /* Unused ring
1914         dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1915             & 0x0000DC00;
1916 */
1917
1918         b43_interrupt_ack(dev, reason);
1919         /* disable all IRQs. They are enabled again in the bottom half. */
1920         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
1921         /* save the reason code and call our bottom half. */
1922         dev->irq_reason = reason;
1923         tasklet_schedule(&dev->isr_tasklet);
1924 out:
1925         mmiowb();
1926         spin_unlock(&dev->wl->irq_lock);
1927
1928         return ret;
1929 }
1930
1931 void b43_do_release_fw(struct b43_firmware_file *fw)
1932 {
1933         release_firmware(fw->data);
1934         fw->data = NULL;
1935         fw->filename = NULL;
1936 }
1937
1938 static void b43_release_firmware(struct b43_wldev *dev)
1939 {
1940         b43_do_release_fw(&dev->fw.ucode);
1941         b43_do_release_fw(&dev->fw.pcm);
1942         b43_do_release_fw(&dev->fw.initvals);
1943         b43_do_release_fw(&dev->fw.initvals_band);
1944 }
1945
1946 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1947 {
1948         const char text[] =
1949                 "You must go to " \
1950                 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
1951                 "and download the correct firmware for this driver version. " \
1952                 "Please carefully read all instructions on this website.\n";
1953
1954         if (error)
1955                 b43err(wl, text);
1956         else
1957                 b43warn(wl, text);
1958 }
1959
1960 int b43_do_request_fw(struct b43_request_fw_context *ctx,
1961                       const char *name,
1962                       struct b43_firmware_file *fw)
1963 {
1964         const struct firmware *blob;
1965         struct b43_fw_header *hdr;
1966         u32 size;
1967         int err;
1968
1969         if (!name) {
1970                 /* Don't fetch anything. Free possibly cached firmware. */
1971                 /* FIXME: We should probably keep it anyway, to save some headache
1972                  * on suspend/resume with multiband devices. */
1973                 b43_do_release_fw(fw);
1974                 return 0;
1975         }
1976         if (fw->filename) {
1977                 if ((fw->type == ctx->req_type) &&
1978                     (strcmp(fw->filename, name) == 0))
1979                         return 0; /* Already have this fw. */
1980                 /* Free the cached firmware first. */
1981                 /* FIXME: We should probably do this later after we successfully
1982                  * got the new fw. This could reduce headache with multiband devices.
1983                  * We could also redesign this to cache the firmware for all possible
1984                  * bands all the time. */
1985                 b43_do_release_fw(fw);
1986         }
1987
1988         switch (ctx->req_type) {
1989         case B43_FWTYPE_PROPRIETARY:
1990                 snprintf(ctx->fwname, sizeof(ctx->fwname),
1991                          "b43%s/%s.fw",
1992                          modparam_fwpostfix, name);
1993                 break;
1994         case B43_FWTYPE_OPENSOURCE:
1995                 snprintf(ctx->fwname, sizeof(ctx->fwname),
1996                          "b43-open%s/%s.fw",
1997                          modparam_fwpostfix, name);
1998                 break;
1999         default:
2000                 B43_WARN_ON(1);
2001                 return -ENOSYS;
2002         }
2003         err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
2004         if (err == -ENOENT) {
2005                 snprintf(ctx->errors[ctx->req_type],
2006                          sizeof(ctx->errors[ctx->req_type]),
2007                          "Firmware file \"%s\" not found\n", ctx->fwname);
2008                 return err;
2009         } else if (err) {
2010                 snprintf(ctx->errors[ctx->req_type],
2011                          sizeof(ctx->errors[ctx->req_type]),
2012                          "Firmware file \"%s\" request failed (err=%d)\n",
2013                          ctx->fwname, err);
2014                 return err;
2015         }
2016         if (blob->size < sizeof(struct b43_fw_header))
2017                 goto err_format;
2018         hdr = (struct b43_fw_header *)(blob->data);
2019         switch (hdr->type) {
2020         case B43_FW_TYPE_UCODE:
2021         case B43_FW_TYPE_PCM:
2022                 size = be32_to_cpu(hdr->size);
2023                 if (size != blob->size - sizeof(struct b43_fw_header))
2024                         goto err_format;
2025                 /* fallthrough */
2026         case B43_FW_TYPE_IV:
2027                 if (hdr->ver != 1)
2028                         goto err_format;
2029                 break;
2030         default:
2031                 goto err_format;
2032         }
2033
2034         fw->data = blob;
2035         fw->filename = name;
2036         fw->type = ctx->req_type;
2037
2038         return 0;
2039
2040 err_format:
2041         snprintf(ctx->errors[ctx->req_type],
2042                  sizeof(ctx->errors[ctx->req_type]),
2043                  "Firmware file \"%s\" format error.\n", ctx->fwname);
2044         release_firmware(blob);
2045
2046         return -EPROTO;
2047 }
2048
2049 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2050 {
2051         struct b43_wldev *dev = ctx->dev;
2052         struct b43_firmware *fw = &ctx->dev->fw;
2053         const u8 rev = ctx->dev->dev->id.revision;
2054         const char *filename;
2055         u32 tmshigh;
2056         int err;
2057
2058         /* Get microcode */
2059         tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
2060         if ((rev >= 5) && (rev <= 10))
2061                 filename = "ucode5";
2062         else if ((rev >= 11) && (rev <= 12))
2063                 filename = "ucode11";
2064         else if (rev >= 13)
2065                 filename = "ucode13";
2066         else
2067                 goto err_no_ucode;
2068         err = b43_do_request_fw(ctx, filename, &fw->ucode);
2069         if (err)
2070                 goto err_load;
2071
2072         /* Get PCM code */
2073         if ((rev >= 5) && (rev <= 10))
2074                 filename = "pcm5";
2075         else if (rev >= 11)
2076                 filename = NULL;
2077         else
2078                 goto err_no_pcm;
2079         fw->pcm_request_failed = 0;
2080         err = b43_do_request_fw(ctx, filename, &fw->pcm);
2081         if (err == -ENOENT) {
2082                 /* We did not find a PCM file? Not fatal, but
2083                  * core rev <= 10 must do without hwcrypto then. */
2084                 fw->pcm_request_failed = 1;
2085         } else if (err)
2086                 goto err_load;
2087
2088         /* Get initvals */
2089         switch (dev->phy.type) {
2090         case B43_PHYTYPE_A:
2091                 if ((rev >= 5) && (rev <= 10)) {
2092                         if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2093                                 filename = "a0g1initvals5";
2094                         else
2095                                 filename = "a0g0initvals5";
2096                 } else
2097                         goto err_no_initvals;
2098                 break;
2099         case B43_PHYTYPE_G:
2100                 if ((rev >= 5) && (rev <= 10))
2101                         filename = "b0g0initvals5";
2102                 else if (rev >= 13)
2103                         filename = "b0g0initvals13";
2104                 else
2105                         goto err_no_initvals;
2106                 break;
2107         case B43_PHYTYPE_N:
2108                 if ((rev >= 11) && (rev <= 12))
2109                         filename = "n0initvals11";
2110                 else
2111                         goto err_no_initvals;
2112                 break;
2113         default:
2114                 goto err_no_initvals;
2115         }
2116         err = b43_do_request_fw(ctx, filename, &fw->initvals);
2117         if (err)
2118                 goto err_load;
2119
2120         /* Get bandswitch initvals */
2121         switch (dev->phy.type) {
2122         case B43_PHYTYPE_A:
2123                 if ((rev >= 5) && (rev <= 10)) {
2124                         if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2125                                 filename = "a0g1bsinitvals5";
2126                         else
2127                                 filename = "a0g0bsinitvals5";
2128                 } else if (rev >= 11)
2129                         filename = NULL;
2130                 else
2131                         goto err_no_initvals;
2132                 break;
2133         case B43_PHYTYPE_G:
2134                 if ((rev >= 5) && (rev <= 10))
2135                         filename = "b0g0bsinitvals5";
2136                 else if (rev >= 11)
2137                         filename = NULL;
2138                 else
2139                         goto err_no_initvals;
2140                 break;
2141         case B43_PHYTYPE_N:
2142                 if ((rev >= 11) && (rev <= 12))
2143                         filename = "n0bsinitvals11";
2144                 else
2145                         goto err_no_initvals;
2146                 break;
2147         default:
2148                 goto err_no_initvals;
2149         }
2150         err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
2151         if (err)
2152                 goto err_load;
2153
2154         return 0;
2155
2156 err_no_ucode:
2157         err = ctx->fatal_failure = -EOPNOTSUPP;
2158         b43err(dev->wl, "The driver does not know which firmware (ucode) "
2159                "is required for your device (wl-core rev %u)\n", rev);
2160         goto error;
2161
2162 err_no_pcm:
2163         err = ctx->fatal_failure = -EOPNOTSUPP;
2164         b43err(dev->wl, "The driver does not know which firmware (PCM) "
2165                "is required for your device (wl-core rev %u)\n", rev);
2166         goto error;
2167
2168 err_no_initvals:
2169         err = ctx->fatal_failure = -EOPNOTSUPP;
2170         b43err(dev->wl, "The driver does not know which firmware (initvals) "
2171                "is required for your device (wl-core rev %u)\n", rev);
2172         goto error;
2173
2174 err_load:
2175         /* We failed to load this firmware image. The error message
2176          * already is in ctx->errors. Return and let our caller decide
2177          * what to do. */
2178         goto error;
2179
2180 error:
2181         b43_release_firmware(dev);
2182         return err;
2183 }
2184
2185 static int b43_request_firmware(struct b43_wldev *dev)
2186 {
2187         struct b43_request_fw_context *ctx;
2188         unsigned int i;
2189         int err;
2190         const char *errmsg;
2191
2192         ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2193         if (!ctx)
2194                 return -ENOMEM;
2195         ctx->dev = dev;
2196
2197         ctx->req_type = B43_FWTYPE_PROPRIETARY;
2198         err = b43_try_request_fw(ctx);
2199         if (!err)
2200                 goto out; /* Successfully loaded it. */
2201         err = ctx->fatal_failure;
2202         if (err)
2203                 goto out;
2204
2205         ctx->req_type = B43_FWTYPE_OPENSOURCE;
2206         err = b43_try_request_fw(ctx);
2207         if (!err)
2208                 goto out; /* Successfully loaded it. */
2209         err = ctx->fatal_failure;
2210         if (err)
2211                 goto out;
2212
2213         /* Could not find a usable firmware. Print the errors. */
2214         for (i = 0; i < B43_NR_FWTYPES; i++) {
2215                 errmsg = ctx->errors[i];
2216                 if (strlen(errmsg))
2217                         b43err(dev->wl, errmsg);
2218         }
2219         b43_print_fw_helptext(dev->wl, 1);
2220         err = -ENOENT;
2221
2222 out:
2223         kfree(ctx);
2224         return err;
2225 }
2226
2227 static int b43_upload_microcode(struct b43_wldev *dev)
2228 {
2229         const size_t hdr_len = sizeof(struct b43_fw_header);
2230         const __be32 *data;
2231         unsigned int i, len;
2232         u16 fwrev, fwpatch, fwdate, fwtime;
2233         u32 tmp, macctl;
2234         int err = 0;
2235
2236         /* Jump the microcode PSM to offset 0 */
2237         macctl = b43_read32(dev, B43_MMIO_MACCTL);
2238         B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2239         macctl |= B43_MACCTL_PSM_JMP0;
2240         b43_write32(dev, B43_MMIO_MACCTL, macctl);
2241         /* Zero out all microcode PSM registers and shared memory. */
2242         for (i = 0; i < 64; i++)
2243                 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2244         for (i = 0; i < 4096; i += 2)
2245                 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2246
2247         /* Upload Microcode. */
2248         data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2249         len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2250         b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2251         for (i = 0; i < len; i++) {
2252                 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2253                 udelay(10);
2254         }
2255
2256         if (dev->fw.pcm.data) {
2257                 /* Upload PCM data. */
2258                 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2259                 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2260                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2261                 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2262                 /* No need for autoinc bit in SHM_HW */
2263                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2264                 for (i = 0; i < len; i++) {
2265                         b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2266                         udelay(10);
2267                 }
2268         }
2269
2270         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2271
2272         /* Start the microcode PSM */
2273         macctl = b43_read32(dev, B43_MMIO_MACCTL);
2274         macctl &= ~B43_MACCTL_PSM_JMP0;
2275         macctl |= B43_MACCTL_PSM_RUN;
2276         b43_write32(dev, B43_MMIO_MACCTL, macctl);
2277
2278         /* Wait for the microcode to load and respond */
2279         i = 0;
2280         while (1) {
2281                 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2282                 if (tmp == B43_IRQ_MAC_SUSPENDED)
2283                         break;
2284                 i++;
2285                 if (i >= 20) {
2286                         b43err(dev->wl, "Microcode not responding\n");
2287                         b43_print_fw_helptext(dev->wl, 1);
2288                         err = -ENODEV;
2289                         goto error;
2290                 }
2291                 msleep_interruptible(50);
2292                 if (signal_pending(current)) {
2293                         err = -EINTR;
2294                         goto error;
2295                 }
2296         }
2297         b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);       /* dummy read */
2298
2299         /* Get and check the revisions. */
2300         fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2301         fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2302         fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2303         fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2304
2305         if (fwrev <= 0x128) {
2306                 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2307                        "binary drivers older than version 4.x is unsupported. "
2308                        "You must upgrade your firmware files.\n");
2309                 b43_print_fw_helptext(dev->wl, 1);
2310                 err = -EOPNOTSUPP;
2311                 goto error;
2312         }
2313         dev->fw.rev = fwrev;
2314         dev->fw.patch = fwpatch;
2315         dev->fw.opensource = (fwdate == 0xFFFF);
2316
2317         /* Default to use-all-queues. */
2318         dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2319         dev->qos_enabled = !!modparam_qos;
2320         /* Default to firmware/hardware crypto acceleration. */
2321         dev->hwcrypto_enabled = 1;
2322
2323         if (dev->fw.opensource) {
2324                 u16 fwcapa;
2325
2326                 /* Patchlevel info is encoded in the "time" field. */
2327                 dev->fw.patch = fwtime;
2328                 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2329                         dev->fw.rev, dev->fw.patch);
2330
2331                 fwcapa = b43_fwcapa_read(dev);
2332                 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2333                         b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2334                         /* Disable hardware crypto and fall back to software crypto. */
2335                         dev->hwcrypto_enabled = 0;
2336                 }
2337                 if (!(fwcapa & B43_FWCAPA_QOS)) {
2338                         b43info(dev->wl, "QoS not supported by firmware\n");
2339                         /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2340                          * ieee80211_unregister to make sure the networking core can
2341                          * properly free possible resources. */
2342                         dev->wl->hw->queues = 1;
2343                         dev->qos_enabled = 0;
2344                 }
2345         } else {
2346                 b43info(dev->wl, "Loading firmware version %u.%u "
2347                         "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2348                         fwrev, fwpatch,
2349                         (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2350                         (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2351                 if (dev->fw.pcm_request_failed) {
2352                         b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2353                                 "Hardware accelerated cryptography is disabled.\n");
2354                         b43_print_fw_helptext(dev->wl, 0);
2355                 }
2356         }
2357
2358         if (b43_is_old_txhdr_format(dev)) {
2359                 /* We're over the deadline, but we keep support for old fw
2360                  * until it turns out to be in major conflict with something new. */
2361                 b43warn(dev->wl, "You are using an old firmware image. "
2362                         "Support for old firmware will be removed soon "
2363                         "(official deadline was July 2008).\n");
2364                 b43_print_fw_helptext(dev->wl, 0);
2365         }
2366
2367         return 0;
2368
2369 error:
2370         macctl = b43_read32(dev, B43_MMIO_MACCTL);
2371         macctl &= ~B43_MACCTL_PSM_RUN;
2372         macctl |= B43_MACCTL_PSM_JMP0;
2373         b43_write32(dev, B43_MMIO_MACCTL, macctl);
2374
2375         return err;
2376 }
2377
2378 static int b43_write_initvals(struct b43_wldev *dev,
2379                               const struct b43_iv *ivals,
2380                               size_t count,
2381                               size_t array_size)
2382 {
2383         const struct b43_iv *iv;
2384         u16 offset;
2385         size_t i;
2386         bool bit32;
2387
2388         BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2389         iv = ivals;
2390         for (i = 0; i < count; i++) {
2391                 if (array_size < sizeof(iv->offset_size))
2392                         goto err_format;
2393                 array_size -= sizeof(iv->offset_size);
2394                 offset = be16_to_cpu(iv->offset_size);
2395                 bit32 = !!(offset & B43_IV_32BIT);
2396                 offset &= B43_IV_OFFSET_MASK;
2397                 if (offset >= 0x1000)
2398                         goto err_format;
2399                 if (bit32) {
2400                         u32 value;
2401
2402                         if (array_size < sizeof(iv->data.d32))
2403                                 goto err_format;
2404                         array_size -= sizeof(iv->data.d32);
2405
2406                         value = get_unaligned_be32(&iv->data.d32);
2407                         b43_write32(dev, offset, value);
2408
2409                         iv = (const struct b43_iv *)((const uint8_t *)iv +
2410                                                         sizeof(__be16) +
2411                                                         sizeof(__be32));
2412                 } else {
2413                         u16 value;
2414
2415                         if (array_size < sizeof(iv->data.d16))
2416                                 goto err_format;
2417                         array_size -= sizeof(iv->data.d16);
2418
2419                         value = be16_to_cpu(iv->data.d16);
2420                         b43_write16(dev, offset, value);
2421
2422                         iv = (const struct b43_iv *)((const uint8_t *)iv +
2423                                                         sizeof(__be16) +
2424                                                         sizeof(__be16));
2425                 }
2426         }
2427         if (array_size)
2428                 goto err_format;
2429
2430         return 0;
2431
2432 err_format:
2433         b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2434         b43_print_fw_helptext(dev->wl, 1);
2435
2436         return -EPROTO;
2437 }
2438
2439 static int b43_upload_initvals(struct b43_wldev *dev)
2440 {
2441         const size_t hdr_len = sizeof(struct b43_fw_header);
2442         const struct b43_fw_header *hdr;
2443         struct b43_firmware *fw = &dev->fw;
2444         const struct b43_iv *ivals;