gianfar: Fix build.
[daniel-s-linux-stuff:linux-kernel.git] / drivers / net / gianfar.c
1 /*
2  * drivers/net/gianfar.c
3  *
4  * Gianfar Ethernet Driver
5  * This driver is designed for the non-CPM ethernet controllers
6  * on the 85xx and 83xx family of integrated processors
7  * Based on 8260_io/fcc_enet.c
8  *
9  * Author: Andy Fleming
10  * Maintainer: Kumar Gala
11  *
12  * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13  * Copyright (c) 2007 MontaVista Software, Inc.
14  *
15  * This program is free software; you can redistribute  it and/or modify it
16  * under  the terms of  the GNU General  Public License as published by the
17  * Free Software Foundation;  either version 2 of the  License, or (at your
18  * option) any later version.
19  *
20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
21  *  RA 11 31 24.2
22  *  Dec +69 19 52
23  *  V 3.84
24  *  B-V +1.62
25  *
26  *  Theory of operation
27  *
28  *  The driver is initialized through of_device. Configuration information
29  *  is therefore conveyed through an OF-style device tree.
30  *
31  *  The Gianfar Ethernet Controller uses a ring of buffer
32  *  descriptors.  The beginning is indicated by a register
33  *  pointing to the physical address of the start of the ring.
34  *  The end is determined by a "wrap" bit being set in the
35  *  last descriptor of the ring.
36  *
37  *  When a packet is received, the RXF bit in the
38  *  IEVENT register is set, triggering an interrupt when the
39  *  corresponding bit in the IMASK register is also set (if
40  *  interrupt coalescing is active, then the interrupt may not
41  *  happen immediately, but will wait until either a set number
42  *  of frames or amount of time have passed).  In NAPI, the
43  *  interrupt handler will signal there is work to be done, and
44  *  exit. This method will start at the last known empty
45  *  descriptor, and process every subsequent descriptor until there
46  *  are none left with data (NAPI will stop after a set number of
47  *  packets to give time to other tasks, but will eventually
48  *  process all the packets).  The data arrives inside a
49  *  pre-allocated skb, and so after the skb is passed up to the
50  *  stack, a new skb must be allocated, and the address field in
51  *  the buffer descriptor must be updated to indicate this new
52  *  skb.
53  *
54  *  When the kernel requests that a packet be transmitted, the
55  *  driver starts where it left off last time, and points the
56  *  descriptor at the buffer which was passed in.  The driver
57  *  then informs the DMA engine that there are packets ready to
58  *  be transmitted.  Once the controller is finished transmitting
59  *  the packet, an interrupt may be triggered (under the same
60  *  conditions as for reception, but depending on the TXF bit).
61  *  The driver then cleans up the buffer.
62  */
63
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
77 #include <linux/mm.h>
78 #include <linux/of_mdio.h>
79 #include <linux/of_platform.h>
80 #include <linux/ip.h>
81 #include <linux/tcp.h>
82 #include <linux/udp.h>
83 #include <linux/in.h>
84
85 #include <asm/io.h>
86 #include <asm/irq.h>
87 #include <asm/uaccess.h>
88 #include <linux/module.h>
89 #include <linux/dma-mapping.h>
90 #include <linux/crc32.h>
91 #include <linux/mii.h>
92 #include <linux/phy.h>
93 #include <linux/phy_fixed.h>
94 #include <linux/of.h>
95
96 #include "gianfar.h"
97 #include "fsl_pq_mdio.h"
98
99 #define TX_TIMEOUT      (1*HZ)
100 #undef BRIEF_GFAR_ERRORS
101 #undef VERBOSE_GFAR_ERRORS
102
103 const char gfar_driver_name[] = "Gianfar Ethernet";
104 const char gfar_driver_version[] = "1.3";
105
106 static int gfar_enet_open(struct net_device *dev);
107 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
108 static void gfar_reset_task(struct work_struct *work);
109 static void gfar_timeout(struct net_device *dev);
110 static int gfar_close(struct net_device *dev);
111 struct sk_buff *gfar_new_skb(struct net_device *dev);
112 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
113                 struct sk_buff *skb);
114 static int gfar_set_mac_address(struct net_device *dev);
115 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
116 static irqreturn_t gfar_error(int irq, void *dev_id);
117 static irqreturn_t gfar_transmit(int irq, void *dev_id);
118 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
119 static void adjust_link(struct net_device *dev);
120 static void init_registers(struct net_device *dev);
121 static int init_phy(struct net_device *dev);
122 static int gfar_probe(struct of_device *ofdev,
123                 const struct of_device_id *match);
124 static int gfar_remove(struct of_device *ofdev);
125 static void free_skb_resources(struct gfar_private *priv);
126 static void gfar_set_multi(struct net_device *dev);
127 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
128 static void gfar_configure_serdes(struct net_device *dev);
129 static int gfar_poll(struct napi_struct *napi, int budget);
130 #ifdef CONFIG_NET_POLL_CONTROLLER
131 static void gfar_netpoll(struct net_device *dev);
132 #endif
133 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
134 static int gfar_clean_tx_ring(struct net_device *dev);
135 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
136                               int amount_pull);
137 static void gfar_vlan_rx_register(struct net_device *netdev,
138                                 struct vlan_group *grp);
139 void gfar_halt(struct net_device *dev);
140 static void gfar_halt_nodisable(struct net_device *dev);
141 void gfar_start(struct net_device *dev);
142 static void gfar_clear_exact_match(struct net_device *dev);
143 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
145
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
149
150 static const struct net_device_ops gfar_netdev_ops = {
151         .ndo_open = gfar_enet_open,
152         .ndo_start_xmit = gfar_start_xmit,
153         .ndo_stop = gfar_close,
154         .ndo_change_mtu = gfar_change_mtu,
155         .ndo_set_multicast_list = gfar_set_multi,
156         .ndo_tx_timeout = gfar_timeout,
157         .ndo_do_ioctl = gfar_ioctl,
158         .ndo_vlan_rx_register = gfar_vlan_rx_register,
159         .ndo_set_mac_address = eth_mac_addr,
160         .ndo_validate_addr = eth_validate_addr,
161 #ifdef CONFIG_NET_POLL_CONTROLLER
162         .ndo_poll_controller = gfar_netpoll,
163 #endif
164 };
165
166 /* Returns 1 if incoming frames use an FCB */
167 static inline int gfar_uses_fcb(struct gfar_private *priv)
168 {
169         return priv->vlgrp || priv->rx_csum_enable;
170 }
171
172 static int gfar_of_init(struct net_device *dev)
173 {
174         const char *model;
175         const char *ctype;
176         const void *mac_addr;
177         u64 addr, size;
178         int err = 0;
179         struct gfar_private *priv = netdev_priv(dev);
180         struct device_node *np = priv->node;
181         const u32 *stash;
182         const u32 *stash_len;
183         const u32 *stash_idx;
184
185         if (!np || !of_device_is_available(np))
186                 return -ENODEV;
187
188         /* get a pointer to the register memory */
189         addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
190         priv->regs = ioremap(addr, size);
191
192         if (priv->regs == NULL)
193                 return -ENOMEM;
194
195         priv->interruptTransmit = irq_of_parse_and_map(np, 0);
196
197         model = of_get_property(np, "model", NULL);
198
199         /* If we aren't the FEC we have multiple interrupts */
200         if (model && strcasecmp(model, "FEC")) {
201                 priv->interruptReceive = irq_of_parse_and_map(np, 1);
202
203                 priv->interruptError = irq_of_parse_and_map(np, 2);
204
205                 if (priv->interruptTransmit < 0 ||
206                                 priv->interruptReceive < 0 ||
207                                 priv->interruptError < 0) {
208                         err = -EINVAL;
209                         goto err_out;
210                 }
211         }
212
213         stash = of_get_property(np, "bd-stash", NULL);
214
215         if(stash) {
216                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
217                 priv->bd_stash_en = 1;
218         }
219
220         stash_len = of_get_property(np, "rx-stash-len", NULL);
221
222         if (stash_len)
223                 priv->rx_stash_size = *stash_len;
224
225         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
226
227         if (stash_idx)
228                 priv->rx_stash_index = *stash_idx;
229
230         if (stash_len || stash_idx)
231                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
232
233         mac_addr = of_get_mac_address(np);
234         if (mac_addr)
235                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
236
237         if (model && !strcasecmp(model, "TSEC"))
238                 priv->device_flags =
239                         FSL_GIANFAR_DEV_HAS_GIGABIT |
240                         FSL_GIANFAR_DEV_HAS_COALESCE |
241                         FSL_GIANFAR_DEV_HAS_RMON |
242                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
243         if (model && !strcasecmp(model, "eTSEC"))
244                 priv->device_flags =
245                         FSL_GIANFAR_DEV_HAS_GIGABIT |
246                         FSL_GIANFAR_DEV_HAS_COALESCE |
247                         FSL_GIANFAR_DEV_HAS_RMON |
248                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
249                         FSL_GIANFAR_DEV_HAS_PADDING |
250                         FSL_GIANFAR_DEV_HAS_CSUM |
251                         FSL_GIANFAR_DEV_HAS_VLAN |
252                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
253                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
254
255         ctype = of_get_property(np, "phy-connection-type", NULL);
256
257         /* We only care about rgmii-id.  The rest are autodetected */
258         if (ctype && !strcmp(ctype, "rgmii-id"))
259                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
260         else
261                 priv->interface = PHY_INTERFACE_MODE_MII;
262
263         if (of_get_property(np, "fsl,magic-packet", NULL))
264                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
265
266         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
267
268         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
269         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
270
271         return 0;
272
273 err_out:
274         iounmap(priv->regs);
275         return err;
276 }
277
278 /* Ioctl MII Interface */
279 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
280 {
281         struct gfar_private *priv = netdev_priv(dev);
282
283         if (!netif_running(dev))
284                 return -EINVAL;
285
286         if (!priv->phydev)
287                 return -ENODEV;
288
289         return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
290 }
291
292 /* Set up the ethernet device structure, private data,
293  * and anything else we need before we start */
294 static int gfar_probe(struct of_device *ofdev,
295                 const struct of_device_id *match)
296 {
297         u32 tempval;
298         struct net_device *dev = NULL;
299         struct gfar_private *priv = NULL;
300         DECLARE_MAC_BUF(mac);
301         int err = 0;
302         int len_devname;
303
304         /* Create an ethernet device instance */
305         dev = alloc_etherdev(sizeof (*priv));
306
307         if (NULL == dev)
308                 return -ENOMEM;
309
310         priv = netdev_priv(dev);
311         priv->ndev = dev;
312         priv->ofdev = ofdev;
313         priv->node = ofdev->node;
314         SET_NETDEV_DEV(dev, &ofdev->dev);
315
316         err = gfar_of_init(dev);
317
318         if (err)
319                 goto regs_fail;
320
321         spin_lock_init(&priv->txlock);
322         spin_lock_init(&priv->rxlock);
323         spin_lock_init(&priv->bflock);
324         INIT_WORK(&priv->reset_task, gfar_reset_task);
325
326         dev_set_drvdata(&ofdev->dev, priv);
327
328         /* Stop the DMA engine now, in case it was running before */
329         /* (The firmware could have used it, and left it running). */
330         gfar_halt(dev);
331
332         /* Reset MAC layer */
333         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
334
335         /* We need to delay at least 3 TX clocks */
336         udelay(2);
337
338         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
339         gfar_write(&priv->regs->maccfg1, tempval);
340
341         /* Initialize MACCFG2. */
342         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
343
344         /* Initialize ECNTRL */
345         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
346
347         /* Set the dev->base_addr to the gfar reg region */
348         dev->base_addr = (unsigned long) (priv->regs);
349
350         SET_NETDEV_DEV(dev, &ofdev->dev);
351
352         /* Fill in the dev structure */
353         dev->watchdog_timeo = TX_TIMEOUT;
354         netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
355         dev->mtu = 1500;
356
357         dev->netdev_ops = &gfar_netdev_ops;
358         dev->ethtool_ops = &gfar_ethtool_ops;
359
360         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
361                 priv->rx_csum_enable = 1;
362                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
363         } else
364                 priv->rx_csum_enable = 0;
365
366         priv->vlgrp = NULL;
367
368         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
369                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
370
371         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
372                 priv->extended_hash = 1;
373                 priv->hash_width = 9;
374
375                 priv->hash_regs[0] = &priv->regs->igaddr0;
376                 priv->hash_regs[1] = &priv->regs->igaddr1;
377                 priv->hash_regs[2] = &priv->regs->igaddr2;
378                 priv->hash_regs[3] = &priv->regs->igaddr3;
379                 priv->hash_regs[4] = &priv->regs->igaddr4;
380                 priv->hash_regs[5] = &priv->regs->igaddr5;
381                 priv->hash_regs[6] = &priv->regs->igaddr6;
382                 priv->hash_regs[7] = &priv->regs->igaddr7;
383                 priv->hash_regs[8] = &priv->regs->gaddr0;
384                 priv->hash_regs[9] = &priv->regs->gaddr1;
385                 priv->hash_regs[10] = &priv->regs->gaddr2;
386                 priv->hash_regs[11] = &priv->regs->gaddr3;
387                 priv->hash_regs[12] = &priv->regs->gaddr4;
388                 priv->hash_regs[13] = &priv->regs->gaddr5;
389                 priv->hash_regs[14] = &priv->regs->gaddr6;
390                 priv->hash_regs[15] = &priv->regs->gaddr7;
391
392         } else {
393                 priv->extended_hash = 0;
394                 priv->hash_width = 8;
395
396                 priv->hash_regs[0] = &priv->regs->gaddr0;
397                 priv->hash_regs[1] = &priv->regs->gaddr1;
398                 priv->hash_regs[2] = &priv->regs->gaddr2;
399                 priv->hash_regs[3] = &priv->regs->gaddr3;
400                 priv->hash_regs[4] = &priv->regs->gaddr4;
401                 priv->hash_regs[5] = &priv->regs->gaddr5;
402                 priv->hash_regs[6] = &priv->regs->gaddr6;
403                 priv->hash_regs[7] = &priv->regs->gaddr7;
404         }
405
406         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
407                 priv->padding = DEFAULT_PADDING;
408         else
409                 priv->padding = 0;
410
411         if (dev->features & NETIF_F_IP_CSUM)
412                 dev->hard_header_len += GMAC_FCB_LEN;
413
414         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
415         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
416         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
417         priv->num_txbdfree = DEFAULT_TX_RING_SIZE;
418
419         priv->txcoalescing = DEFAULT_TX_COALESCE;
420         priv->txic = DEFAULT_TXIC;
421         priv->rxcoalescing = DEFAULT_RX_COALESCE;
422         priv->rxic = DEFAULT_RXIC;
423
424         /* Enable most messages by default */
425         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
426
427         /* Carrier starts down, phylib will bring it up */
428         netif_carrier_off(dev);
429
430         err = register_netdev(dev);
431
432         if (err) {
433                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
434                                 dev->name);
435                 goto register_fail;
436         }
437
438         device_init_wakeup(&dev->dev,
439                 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
440
441         /* fill out IRQ number and name fields */
442         len_devname = strlen(dev->name);
443         strncpy(&priv->int_name_tx[0], dev->name, len_devname);
444         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
445                 strncpy(&priv->int_name_tx[len_devname],
446                         "_tx", sizeof("_tx") + 1);
447
448                 strncpy(&priv->int_name_rx[0], dev->name, len_devname);
449                 strncpy(&priv->int_name_rx[len_devname],
450                         "_rx", sizeof("_rx") + 1);
451
452                 strncpy(&priv->int_name_er[0], dev->name, len_devname);
453                 strncpy(&priv->int_name_er[len_devname],
454                         "_er", sizeof("_er") + 1);
455         } else
456                 priv->int_name_tx[len_devname] = '\0';
457
458         /* Create all the sysfs files */
459         gfar_init_sysfs(dev);
460
461         /* Print out the device info */
462         printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
463
464         /* Even more device info helps when determining which kernel */
465         /* provided which set of benchmarks. */
466         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
467         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
468                dev->name, priv->rx_ring_size, priv->tx_ring_size);
469
470         return 0;
471
472 register_fail:
473         iounmap(priv->regs);
474 regs_fail:
475         if (priv->phy_node)
476                 of_node_put(priv->phy_node);
477         if (priv->tbi_node)
478                 of_node_put(priv->tbi_node);
479         free_netdev(dev);
480         return err;
481 }
482
483 static int gfar_remove(struct of_device *ofdev)
484 {
485         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
486
487         if (priv->phy_node)
488                 of_node_put(priv->phy_node);
489         if (priv->tbi_node)
490                 of_node_put(priv->tbi_node);
491
492         dev_set_drvdata(&ofdev->dev, NULL);
493
494         unregister_netdev(priv->ndev);
495         iounmap(priv->regs);
496         free_netdev(priv->ndev);
497
498         return 0;
499 }
500
501 #ifdef CONFIG_PM
502 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
503 {
504         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
505         struct net_device *dev = priv->ndev;
506         unsigned long flags;
507         u32 tempval;
508
509         int magic_packet = priv->wol_en &&
510                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
511
512         netif_device_detach(dev);
513
514         if (netif_running(dev)) {
515                 spin_lock_irqsave(&priv->txlock, flags);
516                 spin_lock(&priv->rxlock);
517
518                 gfar_halt_nodisable(dev);
519
520                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
521                 tempval = gfar_read(&priv->regs->maccfg1);
522
523                 tempval &= ~MACCFG1_TX_EN;
524
525                 if (!magic_packet)
526                         tempval &= ~MACCFG1_RX_EN;
527
528                 gfar_write(&priv->regs->maccfg1, tempval);
529
530                 spin_unlock(&priv->rxlock);
531                 spin_unlock_irqrestore(&priv->txlock, flags);
532
533                 napi_disable(&priv->napi);
534
535                 if (magic_packet) {
536                         /* Enable interrupt on Magic Packet */
537                         gfar_write(&priv->regs->imask, IMASK_MAG);
538
539                         /* Enable Magic Packet mode */
540                         tempval = gfar_read(&priv->regs->maccfg2);
541                         tempval |= MACCFG2_MPEN;
542                         gfar_write(&priv->regs->maccfg2, tempval);
543                 } else {
544                         phy_stop(priv->phydev);
545                 }
546         }
547
548         return 0;
549 }
550
551 static int gfar_resume(struct of_device *ofdev)
552 {
553         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
554         struct net_device *dev = priv->ndev;
555         unsigned long flags;
556         u32 tempval;
557         int magic_packet = priv->wol_en &&
558                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
559
560         if (!netif_running(dev)) {
561                 netif_device_attach(dev);
562                 return 0;
563         }
564
565         if (!magic_packet && priv->phydev)
566                 phy_start(priv->phydev);
567
568         /* Disable Magic Packet mode, in case something
569          * else woke us up.
570          */
571
572         spin_lock_irqsave(&priv->txlock, flags);
573         spin_lock(&priv->rxlock);
574
575         tempval = gfar_read(&priv->regs->maccfg2);
576         tempval &= ~MACCFG2_MPEN;
577         gfar_write(&priv->regs->maccfg2, tempval);
578
579         gfar_start(dev);
580
581         spin_unlock(&priv->rxlock);
582         spin_unlock_irqrestore(&priv->txlock, flags);
583
584         netif_device_attach(dev);
585
586         napi_enable(&priv->napi);
587
588         return 0;
589 }
590 #else
591 #define gfar_suspend NULL
592 #define gfar_resume NULL
593 #endif
594
595 /* Reads the controller's registers to determine what interface
596  * connects it to the PHY.
597  */
598 static phy_interface_t gfar_get_interface(struct net_device *dev)
599 {
600         struct gfar_private *priv = netdev_priv(dev);
601         u32 ecntrl = gfar_read(&priv->regs->ecntrl);
602
603         if (ecntrl & ECNTRL_SGMII_MODE)
604                 return PHY_INTERFACE_MODE_SGMII;
605
606         if (ecntrl & ECNTRL_TBI_MODE) {
607                 if (ecntrl & ECNTRL_REDUCED_MODE)
608                         return PHY_INTERFACE_MODE_RTBI;
609                 else
610                         return PHY_INTERFACE_MODE_TBI;
611         }
612
613         if (ecntrl & ECNTRL_REDUCED_MODE) {
614                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
615                         return PHY_INTERFACE_MODE_RMII;
616                 else {
617                         phy_interface_t interface = priv->interface;
618
619                         /*
620                          * This isn't autodetected right now, so it must
621                          * be set by the device tree or platform code.
622                          */
623                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
624                                 return PHY_INTERFACE_MODE_RGMII_ID;
625
626                         return PHY_INTERFACE_MODE_RGMII;
627                 }
628         }
629
630         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
631                 return PHY_INTERFACE_MODE_GMII;
632
633         return PHY_INTERFACE_MODE_MII;
634 }
635
636
637 /* Initializes driver's PHY state, and attaches to the PHY.
638  * Returns 0 on success.
639  */
640 static int init_phy(struct net_device *dev)
641 {
642         struct gfar_private *priv = netdev_priv(dev);
643         uint gigabit_support =
644                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
645                 SUPPORTED_1000baseT_Full : 0;
646         phy_interface_t interface;
647
648         priv->oldlink = 0;
649         priv->oldspeed = 0;
650         priv->oldduplex = -1;
651
652         interface = gfar_get_interface(dev);
653
654         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
655                                       interface);
656         if (!priv->phydev)
657                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
658                                                          interface);
659         if (!priv->phydev) {
660                 dev_err(&dev->dev, "could not attach to PHY\n");
661                 return -ENODEV;
662         }
663
664         if (interface == PHY_INTERFACE_MODE_SGMII)
665                 gfar_configure_serdes(dev);
666
667         /* Remove any features not supported by the controller */
668         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
669         priv->phydev->advertising = priv->phydev->supported;
670
671         return 0;
672 }
673
674 /*
675  * Initialize TBI PHY interface for communicating with the
676  * SERDES lynx PHY on the chip.  We communicate with this PHY
677  * through the MDIO bus on each controller, treating it as a
678  * "normal" PHY at the address found in the TBIPA register.  We assume
679  * that the TBIPA register is valid.  Either the MDIO bus code will set
680  * it to a value that doesn't conflict with other PHYs on the bus, or the
681  * value doesn't matter, as there are no other PHYs on the bus.
682  */
683 static void gfar_configure_serdes(struct net_device *dev)
684 {
685         struct gfar_private *priv = netdev_priv(dev);
686         struct phy_device *tbiphy;
687
688         if (!priv->tbi_node) {
689                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
690                                     "device tree specify a tbi-handle\n");
691                 return;
692         }
693
694         tbiphy = of_phy_find_device(priv->tbi_node);
695         if (!tbiphy) {
696                 dev_err(&dev->dev, "error: Could not get TBI device\n");
697                 return;
698         }
699
700         /*
701          * If the link is already up, we must already be ok, and don't need to
702          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
703          * everything for us?  Resetting it takes the link down and requires
704          * several seconds for it to come back.
705          */
706         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
707                 return;
708
709         /* Single clk mode, mii mode off(for serdes communication) */
710         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
711
712         phy_write(tbiphy, MII_ADVERTISE,
713                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
714                         ADVERTISE_1000XPSE_ASYM);
715
716         phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
717                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
718 }
719
720 static void init_registers(struct net_device *dev)
721 {
722         struct gfar_private *priv = netdev_priv(dev);
723
724         /* Clear IEVENT */
725         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
726
727         /* Initialize IMASK */
728         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
729
730         /* Init hash registers to zero */
731         gfar_write(&priv->regs->igaddr0, 0);
732         gfar_write(&priv->regs->igaddr1, 0);
733         gfar_write(&priv->regs->igaddr2, 0);
734         gfar_write(&priv->regs->igaddr3, 0);
735         gfar_write(&priv->regs->igaddr4, 0);
736         gfar_write(&priv->regs->igaddr5, 0);
737         gfar_write(&priv->regs->igaddr6, 0);
738         gfar_write(&priv->regs->igaddr7, 0);
739
740         gfar_write(&priv->regs->gaddr0, 0);
741         gfar_write(&priv->regs->gaddr1, 0);
742         gfar_write(&priv->regs->gaddr2, 0);
743         gfar_write(&priv->regs->gaddr3, 0);
744         gfar_write(&priv->regs->gaddr4, 0);
745         gfar_write(&priv->regs->gaddr5, 0);
746         gfar_write(&priv->regs->gaddr6, 0);
747         gfar_write(&priv->regs->gaddr7, 0);
748
749         /* Zero out the rmon mib registers if it has them */
750         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
751                 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
752
753                 /* Mask off the CAM interrupts */
754                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
755                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
756         }
757
758         /* Initialize the max receive buffer length */
759         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
760
761         /* Initialize the Minimum Frame Length Register */
762         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
763 }
764
765
766 /* Halt the receive and transmit queues */
767 static void gfar_halt_nodisable(struct net_device *dev)
768 {
769         struct gfar_private *priv = netdev_priv(dev);
770         struct gfar __iomem *regs = priv->regs;
771         u32 tempval;
772
773         /* Mask all interrupts */
774         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
775
776         /* Clear all interrupts */
777         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
778
779         /* Stop the DMA, and wait for it to stop */
780         tempval = gfar_read(&priv->regs->dmactrl);
781         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
782             != (DMACTRL_GRS | DMACTRL_GTS)) {
783                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
784                 gfar_write(&priv->regs->dmactrl, tempval);
785
786                 while (!(gfar_read(&priv->regs->ievent) &
787                          (IEVENT_GRSC | IEVENT_GTSC)))
788                         cpu_relax();
789         }
790 }
791
792 /* Halt the receive and transmit queues */
793 void gfar_halt(struct net_device *dev)
794 {
795         struct gfar_private *priv = netdev_priv(dev);
796         struct gfar __iomem *regs = priv->regs;
797         u32 tempval;
798
799         gfar_halt_nodisable(dev);
800
801         /* Disable Rx and Tx */
802         tempval = gfar_read(&regs->maccfg1);
803         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
804         gfar_write(&regs->maccfg1, tempval);
805 }
806
807 void stop_gfar(struct net_device *dev)
808 {
809         struct gfar_private *priv = netdev_priv(dev);
810         struct gfar __iomem *regs = priv->regs;
811         unsigned long flags;
812
813         phy_stop(priv->phydev);
814
815         /* Lock it down */
816         spin_lock_irqsave(&priv->txlock, flags);
817         spin_lock(&priv->rxlock);
818
819         gfar_halt(dev);
820
821         spin_unlock(&priv->rxlock);
822         spin_unlock_irqrestore(&priv->txlock, flags);
823
824         /* Free the IRQs */
825         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
826                 free_irq(priv->interruptError, dev);
827                 free_irq(priv->interruptTransmit, dev);
828                 free_irq(priv->interruptReceive, dev);
829         } else {
830                 free_irq(priv->interruptTransmit, dev);
831         }
832
833         free_skb_resources(priv);
834
835         dma_free_coherent(&priv->ofdev->dev,
836                         sizeof(struct txbd8)*priv->tx_ring_size
837                         + sizeof(struct rxbd8)*priv->rx_ring_size,
838                         priv->tx_bd_base,
839                         gfar_read(&regs->tbase0));
840 }
841
842 /* If there are any tx skbs or rx skbs still around, free them.
843  * Then free tx_skbuff and rx_skbuff */
844 static void free_skb_resources(struct gfar_private *priv)
845 {
846         struct rxbd8 *rxbdp;
847         struct txbd8 *txbdp;
848         int i, j;
849
850         /* Go through all the buffer descriptors and free their data buffers */
851         txbdp = priv->tx_bd_base;
852
853         for (i = 0; i < priv->tx_ring_size; i++) {
854                 if (!priv->tx_skbuff[i])
855                         continue;
856
857                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
858                                 txbdp->length, DMA_TO_DEVICE);
859                 txbdp->lstatus = 0;
860                 for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) {
861                         txbdp++;
862                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
863                                         txbdp->length, DMA_TO_DEVICE);
864                 }
865                 txbdp++;
866                 dev_kfree_skb_any(priv->tx_skbuff[i]);
867                 priv->tx_skbuff[i] = NULL;
868         }
869
870         kfree(priv->tx_skbuff);
871
872         rxbdp = priv->rx_bd_base;
873
874         /* rx_skbuff is not guaranteed to be allocated, so only
875          * free it and its contents if it is allocated */
876         if(priv->rx_skbuff != NULL) {
877                 for (i = 0; i < priv->rx_ring_size; i++) {
878                         if (priv->rx_skbuff[i]) {
879                                 dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr,
880                                                 priv->rx_buffer_size,
881                                                 DMA_FROM_DEVICE);
882
883                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
884                                 priv->rx_skbuff[i] = NULL;
885                         }
886
887                         rxbdp->lstatus = 0;
888                         rxbdp->bufPtr = 0;
889
890                         rxbdp++;
891                 }
892
893                 kfree(priv->rx_skbuff);
894         }
895 }
896
897 void gfar_start(struct net_device *dev)
898 {
899         struct gfar_private *priv = netdev_priv(dev);
900         struct gfar __iomem *regs = priv->regs;
901         u32 tempval;
902
903         /* Enable Rx and Tx in MACCFG1 */
904         tempval = gfar_read(&regs->maccfg1);
905         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
906         gfar_write(&regs->maccfg1, tempval);
907
908         /* Initialize DMACTRL to have WWR and WOP */
909         tempval = gfar_read(&priv->regs->dmactrl);
910         tempval |= DMACTRL_INIT_SETTINGS;
911         gfar_write(&priv->regs->dmactrl, tempval);
912
913         /* Make sure we aren't stopped */
914         tempval = gfar_read(&priv->regs->dmactrl);
915         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
916         gfar_write(&priv->regs->dmactrl, tempval);
917
918         /* Clear THLT/RHLT, so that the DMA starts polling now */
919         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
920         gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
921
922         /* Unmask the interrupts we look for */
923         gfar_write(&regs->imask, IMASK_DEFAULT);
924
925         dev->trans_start = jiffies;
926 }
927
928 /* Bring the controller up and running */
929 int startup_gfar(struct net_device *dev)
930 {
931         struct txbd8 *txbdp;
932         struct rxbd8 *rxbdp;
933         dma_addr_t addr = 0;
934         unsigned long vaddr;
935         int i;
936         struct gfar_private *priv = netdev_priv(dev);
937         struct gfar __iomem *regs = priv->regs;
938         int err = 0;
939         u32 rctrl = 0;
940         u32 tctrl = 0;
941         u32 attrs = 0;
942
943         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
944
945         /* Allocate memory for the buffer descriptors */
946         vaddr = (unsigned long) dma_alloc_coherent(&priv->ofdev->dev,
947                         sizeof (struct txbd8) * priv->tx_ring_size +
948                         sizeof (struct rxbd8) * priv->rx_ring_size,
949                         &addr, GFP_KERNEL);
950
951         if (vaddr == 0) {
952                 if (netif_msg_ifup(priv))
953                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
954                                         dev->name);
955                 return -ENOMEM;
956         }
957
958         priv->tx_bd_base = (struct txbd8 *) vaddr;
959
960         /* enet DMA only understands physical addresses */
961         gfar_write(&regs->tbase0, addr);
962
963         /* Start the rx descriptor ring where the tx ring leaves off */
964         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
965         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
966         priv->rx_bd_base = (struct rxbd8 *) vaddr;
967         gfar_write(&regs->rbase0, addr);
968
969         /* Setup the skbuff rings */
970         priv->tx_skbuff =
971             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
972                                         priv->tx_ring_size, GFP_KERNEL);
973
974         if (NULL == priv->tx_skbuff) {
975                 if (netif_msg_ifup(priv))
976                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
977                                         dev->name);
978                 err = -ENOMEM;
979                 goto tx_skb_fail;
980         }
981
982         for (i = 0; i < priv->tx_ring_size; i++)
983                 priv->tx_skbuff[i] = NULL;
984
985         priv->rx_skbuff =
986             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
987                                         priv->rx_ring_size, GFP_KERNEL);
988
989         if (NULL == priv->rx_skbuff) {
990                 if (netif_msg_ifup(priv))
991                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
992                                         dev->name);
993                 err = -ENOMEM;
994                 goto rx_skb_fail;
995         }
996
997         for (i = 0; i < priv->rx_ring_size; i++)
998                 priv->rx_skbuff[i] = NULL;
999
1000         /* Initialize some variables in our dev structure */
1001         priv->num_txbdfree = priv->tx_ring_size;
1002         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
1003         priv->cur_rx = priv->rx_bd_base;
1004         priv->skb_curtx = priv->skb_dirtytx = 0;
1005         priv->skb_currx = 0;
1006
1007         /* Initialize Transmit Descriptor Ring */
1008         txbdp = priv->tx_bd_base;
1009         for (i = 0; i < priv->tx_ring_size; i++) {
1010                 txbdp->lstatus = 0;
1011                 txbdp->bufPtr = 0;
1012                 txbdp++;
1013         }
1014
1015         /* Set the last descriptor in the ring to indicate wrap */
1016         txbdp--;
1017         txbdp->status |= TXBD_WRAP;
1018
1019         rxbdp = priv->rx_bd_base;
1020         for (i = 0; i < priv->rx_ring_size; i++) {
1021                 struct sk_buff *skb;
1022
1023                 skb = gfar_new_skb(dev);
1024
1025                 if (!skb) {
1026                         printk(KERN_ERR "%s: Can't allocate RX buffers\n",
1027                                         dev->name);
1028
1029                         goto err_rxalloc_fail;
1030                 }
1031
1032                 priv->rx_skbuff[i] = skb;
1033
1034                 gfar_new_rxbdp(dev, rxbdp, skb);
1035
1036                 rxbdp++;
1037         }
1038
1039         /* Set the last descriptor in the ring to wrap */
1040         rxbdp--;
1041         rxbdp->status |= RXBD_WRAP;
1042
1043         /* If the device has multiple interrupts, register for
1044          * them.  Otherwise, only register for the one */
1045         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1046                 /* Install our interrupt handlers for Error,
1047                  * Transmit, and Receive */
1048                 if (request_irq(priv->interruptError, gfar_error,
1049                                 0, priv->int_name_er, dev) < 0) {
1050                         if (netif_msg_intr(priv))
1051                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1052                                         dev->name, priv->interruptError);
1053
1054                         err = -1;
1055                         goto err_irq_fail;
1056                 }
1057
1058                 if (request_irq(priv->interruptTransmit, gfar_transmit,
1059                                 0, priv->int_name_tx, dev) < 0) {
1060                         if (netif_msg_intr(priv))
1061                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1062                                         dev->name, priv->interruptTransmit);
1063
1064                         err = -1;
1065
1066                         goto tx_irq_fail;
1067                 }
1068
1069                 if (request_irq(priv->interruptReceive, gfar_receive,
1070                                 0, priv->int_name_rx, dev) < 0) {
1071                         if (netif_msg_intr(priv))
1072                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
1073                                                 dev->name, priv->interruptReceive);
1074
1075                         err = -1;
1076                         goto rx_irq_fail;
1077                 }
1078         } else {
1079                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
1080                                 0, priv->int_name_tx, dev) < 0) {
1081                         if (netif_msg_intr(priv))
1082                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1083                                         dev->name, priv->interruptTransmit);
1084
1085                         err = -1;
1086                         goto err_irq_fail;
1087                 }
1088         }
1089
1090         phy_start(priv->phydev);
1091
1092         /* Configure the coalescing support */
1093         gfar_write(&regs->txic, 0);
1094         if (priv->txcoalescing)
1095                 gfar_write(&regs->txic, priv->txic);
1096
1097         gfar_write(&regs->rxic, 0);
1098         if (priv->rxcoalescing)
1099                 gfar_write(&regs->rxic, priv->rxic);
1100
1101         if (priv->rx_csum_enable)
1102                 rctrl |= RCTRL_CHECKSUMMING;
1103
1104         if (priv->extended_hash) {
1105                 rctrl |= RCTRL_EXTHASH;
1106
1107                 gfar_clear_exact_match(dev);
1108                 rctrl |= RCTRL_EMEN;
1109         }
1110
1111         if (priv->padding) {
1112                 rctrl &= ~RCTRL_PAL_MASK;
1113                 rctrl |= RCTRL_PADDING(priv->padding);
1114         }
1115
1116         /* keep vlan related bits if it's enabled */
1117         if (priv->vlgrp) {
1118                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
1119                 tctrl |= TCTRL_VLINS;
1120         }
1121
1122         /* Init rctrl based on our settings */
1123         gfar_write(&priv->regs->rctrl, rctrl);
1124
1125         if (dev->features & NETIF_F_IP_CSUM)
1126                 tctrl |= TCTRL_INIT_CSUM;
1127
1128         gfar_write(&priv->regs->tctrl, tctrl);
1129
1130         /* Set the extraction length and index */
1131         attrs = ATTRELI_EL(priv->rx_stash_size) |
1132                 ATTRELI_EI(priv->rx_stash_index);
1133
1134         gfar_write(&priv->regs->attreli, attrs);
1135
1136         /* Start with defaults, and add stashing or locking
1137          * depending on the approprate variables */
1138         attrs = ATTR_INIT_SETTINGS;
1139
1140         if (priv->bd_stash_en)
1141                 attrs |= ATTR_BDSTASH;
1142
1143         if (priv->rx_stash_size != 0)
1144                 attrs |= ATTR_BUFSTASH;
1145
1146         gfar_write(&priv->regs->attr, attrs);
1147
1148         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1149         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1150         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1151
1152         /* Start the controller */
1153         gfar_start(dev);
1154
1155         return 0;
1156
1157 rx_irq_fail:
1158         free_irq(priv->interruptTransmit, dev);
1159 tx_irq_fail:
1160         free_irq(priv->interruptError, dev);
1161 err_irq_fail:
1162 err_rxalloc_fail:
1163 rx_skb_fail:
1164         free_skb_resources(priv);
1165 tx_skb_fail:
1166         dma_free_coherent(&priv->ofdev->dev,
1167                         sizeof(struct txbd8)*priv->tx_ring_size
1168                         + sizeof(struct rxbd8)*priv->rx_ring_size,
1169                         priv->tx_bd_base,
1170                         gfar_read(&regs->tbase0));
1171
1172         return err;
1173 }
1174
1175 /* Called when something needs to use the ethernet device */
1176 /* Returns 0 for success. */
1177 static int gfar_enet_open(struct net_device *dev)
1178 {
1179         struct gfar_private *priv = netdev_priv(dev);
1180         int err;
1181
1182         napi_enable(&priv->napi);
1183
1184         skb_queue_head_init(&priv->rx_recycle);
1185
1186         /* Initialize a bunch of registers */
1187         init_registers(dev);
1188
1189         gfar_set_mac_address(dev);
1190
1191         err = init_phy(dev);
1192
1193         if(err) {
1194                 napi_disable(&priv->napi);
1195                 return err;
1196         }
1197
1198         err = startup_gfar(dev);
1199         if (err) {
1200                 napi_disable(&priv->napi);
1201                 return err;
1202         }
1203
1204         netif_start_queue(dev);
1205
1206         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1207
1208         return err;
1209 }
1210
1211 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1212 {
1213         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1214
1215         memset(fcb, 0, GMAC_FCB_LEN);
1216
1217         return fcb;
1218 }
1219
1220 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1221 {
1222         u8 flags = 0;
1223
1224         /* If we're here, it's a IP packet with a TCP or UDP
1225          * payload.  We set it to checksum, using a pseudo-header
1226          * we provide
1227          */
1228         flags = TXFCB_DEFAULT;
1229
1230         /* Tell the controller what the protocol is */
1231         /* And provide the already calculated phcs */
1232         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1233                 flags |= TXFCB_UDP;
1234                 fcb->phcs = udp_hdr(skb)->check;
1235         } else
1236                 fcb->phcs = tcp_hdr(skb)->check;
1237
1238         /* l3os is the distance between the start of the
1239          * frame (skb->data) and the start of the IP hdr.
1240          * l4os is the distance between the start of the
1241          * l3 hdr and the l4 hdr */
1242         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1243         fcb->l4os = skb_network_header_len(skb);
1244
1245         fcb->flags = flags;
1246 }
1247
1248 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1249 {
1250         fcb->flags |= TXFCB_VLN;
1251         fcb->vlctl = vlan_tx_tag_get(skb);
1252 }
1253
1254 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1255                                struct txbd8 *base, int ring_size)
1256 {
1257         struct txbd8 *new_bd = bdp + stride;
1258
1259         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1260 }
1261
1262 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1263                 int ring_size)
1264 {
1265         return skip_txbd(bdp, 1, base, ring_size);
1266 }
1267
1268 /* This is called by the kernel when a frame is ready for transmission. */
1269 /* It is pointed to by the dev->hard_start_xmit function pointer */
1270 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1271 {
1272         struct gfar_private *priv = netdev_priv(dev);
1273         struct txfcb *fcb = NULL;
1274         struct txbd8 *txbdp, *txbdp_start, *base;
1275         u32 lstatus;
1276         int i;
1277         u32 bufaddr;
1278         unsigned long flags;
1279         unsigned int nr_frags, length;
1280
1281         base = priv->tx_bd_base;
1282
1283         /* make space for additional header when fcb is needed */
1284         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
1285                         (priv->vlgrp && vlan_tx_tag_present(skb))) &&
1286                         (skb_headroom(skb) < GMAC_FCB_LEN)) {
1287                 struct sk_buff *skb_new;
1288
1289                 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1290                 if (!skb_new) {
1291                         dev->stats.tx_errors++;
1292                         kfree_skb(skb);
1293                         return NETDEV_TX_OK;
1294                 }
1295                 kfree_skb(skb);
1296                 skb = skb_new;
1297         }
1298
1299         /* total number of fragments in the SKB */
1300         nr_frags = skb_shinfo(skb)->nr_frags;
1301
1302         spin_lock_irqsave(&priv->txlock, flags);
1303
1304         /* check if there is space to queue this packet */
1305         if ((nr_frags+1) > priv->num_txbdfree) {
1306                 /* no space, stop the queue */
1307                 netif_stop_queue(dev);
1308                 dev->stats.tx_fifo_errors++;
1309                 spin_unlock_irqrestore(&priv->txlock, flags);
1310                 return NETDEV_TX_BUSY;
1311         }
1312
1313         /* Update transmit stats */
1314         dev->stats.tx_bytes += skb->len;
1315
1316         txbdp = txbdp_start = priv->cur_tx;
1317
1318         if (nr_frags == 0) {
1319                 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1320         } else {
1321                 /* Place the fragment addresses and lengths into the TxBDs */
1322                 for (i = 0; i < nr_frags; i++) {
1323                         /* Point at the next BD, wrapping as needed */
1324                         txbdp = next_txbd(txbdp, base, priv->tx_ring_size);
1325
1326                         length = skb_shinfo(skb)->frags[i].size;
1327
1328                         lstatus = txbdp->lstatus | length |
1329                                 BD_LFLAG(TXBD_READY);
1330
1331                         /* Handle the last BD specially */
1332                         if (i == nr_frags - 1)
1333                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1334
1335                         bufaddr = dma_map_page(&priv->ofdev->dev,
1336                                         skb_shinfo(skb)->frags[i].page,
1337                                         skb_shinfo(skb)->frags[i].page_offset,
1338                                         length,
1339                                         DMA_TO_DEVICE);
1340
1341                         /* set the TxBD length and buffer pointer */
1342                         txbdp->bufPtr = bufaddr;
1343                         txbdp->lstatus = lstatus;
1344                 }
1345
1346                 lstatus = txbdp_start->lstatus;
1347         }
1348
1349         /* Set up checksumming */
1350         if (CHECKSUM_PARTIAL == skb->ip_summed) {
1351                 fcb = gfar_add_fcb(skb);
1352                 lstatus |= BD_LFLAG(TXBD_TOE);
1353                 gfar_tx_checksum(skb, fcb);
1354         }
1355
1356         if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1357                 if (unlikely(NULL == fcb)) {
1358                         fcb = gfar_add_fcb(skb);
1359                         lstatus |= BD_LFLAG(TXBD_TOE);
1360                 }
1361
1362                 gfar_tx_vlan(skb, fcb);
1363         }
1364
1365         /* setup the TxBD length and buffer pointer for the first BD */
1366         priv->tx_skbuff[priv->skb_curtx] = skb;
1367         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1368                         skb_headlen(skb), DMA_TO_DEVICE);
1369
1370         lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1371
1372         /*
1373          * The powerpc-specific eieio() is used, as wmb() has too strong
1374          * semantics (it requires synchronization between cacheable and
1375          * uncacheable mappings, which eieio doesn't provide and which we
1376          * don't need), thus requiring a more expensive sync instruction.  At
1377          * some point, the set of architecture-independent barrier functions
1378          * should be expanded to include weaker barriers.
1379          */
1380         eieio();
1381
1382         txbdp_start->lstatus = lstatus;
1383
1384         /* Update the current skb pointer to the next entry we will use
1385          * (wrapping if necessary) */
1386         priv->skb_curtx = (priv->skb_curtx + 1) &
1387                 TX_RING_MOD_MASK(priv->tx_ring_size);
1388
1389         priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size);
1390
1391         /* reduce TxBD free count */
1392         priv->num_txbdfree -= (nr_frags + 1);
1393
1394         dev->trans_start = jiffies;
1395
1396         /* If the next BD still needs to be cleaned up, then the bds
1397            are full.  We need to tell the kernel to stop sending us stuff. */
1398         if (!priv->num_txbdfree) {
1399                 netif_stop_queue(dev);
1400
1401                 dev->stats.tx_fifo_errors++;
1402         }
1403
1404         /* Tell the DMA to go go go */
1405         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1406
1407         /* Unlock priv */
1408         spin_unlock_irqrestore(&priv->txlock, flags);
1409
1410         return NETDEV_TX_OK;
1411 }
1412
1413 /* Stops the kernel queue, and halts the controller */
1414 static int gfar_close(struct net_device *dev)
1415 {
1416         struct gfar_private *priv = netdev_priv(dev);
1417
1418         napi_disable(&priv->napi);
1419
1420         skb_queue_purge(&priv->rx_recycle);
1421         cancel_work_sync(&priv->reset_task);
1422         stop_gfar(dev);
1423
1424         /* Disconnect from the PHY */
1425         phy_disconnect(priv->phydev);
1426         priv->phydev = NULL;
1427
1428         netif_stop_queue(dev);
1429
1430         return 0;
1431 }
1432
1433 /* Changes the mac address if the controller is not running. */
1434 static int gfar_set_mac_address(struct net_device *dev)
1435 {
1436         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1437
1438         return 0;
1439 }
1440
1441
1442 /* Enables and disables VLAN insertion/extraction */
1443 static void gfar_vlan_rx_register(struct net_device *dev,
1444                 struct vlan_group *grp)
1445 {
1446         struct gfar_private *priv = netdev_priv(dev);
1447         unsigned long flags;
1448         u32 tempval;
1449
1450         spin_lock_irqsave(&priv->rxlock, flags);
1451
1452         priv->vlgrp = grp;
1453
1454         if (grp) {
1455                 /* Enable VLAN tag insertion */
1456                 tempval = gfar_read(&priv->regs->tctrl);
1457                 tempval |= TCTRL_VLINS;
1458
1459                 gfar_write(&priv->regs->tctrl, tempval);
1460
1461                 /* Enable VLAN tag extraction */
1462                 tempval = gfar_read(&priv->regs->rctrl);
1463                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1464                 gfar_write(&priv->regs->rctrl, tempval);
1465         } else {
1466                 /* Disable VLAN tag insertion */
1467                 tempval = gfar_read(&priv->regs->tctrl);
1468                 tempval &= ~TCTRL_VLINS;
1469                 gfar_write(&priv->regs->tctrl, tempval);
1470
1471                 /* Disable VLAN tag extraction */
1472                 tempval = gfar_read(&priv->regs->rctrl);
1473                 tempval &= ~RCTRL_VLEX;
1474                 /* If parse is no longer required, then disable parser */
1475                 if (tempval & RCTRL_REQ_PARSER)
1476                         tempval |= RCTRL_PRSDEP_INIT;
1477                 else
1478                         tempval &= ~RCTRL_PRSDEP_INIT;
1479                 gfar_write(&priv->regs->rctrl, tempval);
1480         }
1481
1482         gfar_change_mtu(dev, dev->mtu);
1483
1484         spin_unlock_irqrestore(&priv->rxlock, flags);
1485 }
1486
1487 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1488 {
1489         int tempsize, tempval;
1490         struct gfar_private *priv = netdev_priv(dev);
1491         int oldsize = priv->rx_buffer_size;
1492         int frame_size = new_mtu + ETH_HLEN;
1493
1494         if (priv->vlgrp)
1495                 frame_size += VLAN_HLEN;
1496
1497         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1498                 if (netif_msg_drv(priv))
1499                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1500                                         dev->name);
1501                 return -EINVAL;
1502         }
1503
1504         if (gfar_uses_fcb(priv))
1505                 frame_size += GMAC_FCB_LEN;
1506
1507         frame_size += priv->padding;
1508
1509         tempsize =
1510             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1511             INCREMENTAL_BUFFER_SIZE;
1512
1513         /* Only stop and start the controller if it isn't already
1514          * stopped, and we changed something */
1515         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1516                 stop_gfar(dev);
1517
1518         priv->rx_buffer_size = tempsize;
1519
1520         dev->mtu = new_mtu;
1521
1522         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1523         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1524
1525         /* If the mtu is larger than the max size for standard
1526          * ethernet frames (ie, a jumbo frame), then set maccfg2
1527          * to allow huge frames, and to check the length */
1528         tempval = gfar_read(&priv->regs->maccfg2);
1529
1530         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1531                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1532         else
1533                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1534
1535         gfar_write(&priv->regs->maccfg2, tempval);
1536
1537         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1538                 startup_gfar(dev);
1539
1540         return 0;
1541 }
1542
1543 /* gfar_reset_task gets scheduled when a packet has not been
1544  * transmitted after a set amount of time.
1545  * For now, assume that clearing out all the structures, and
1546  * starting over will fix the problem.
1547  */
1548 static void gfar_reset_task(struct work_struct *work)
1549 {
1550         struct gfar_private *priv = container_of(work, struct gfar_private,
1551                         reset_task);
1552         struct net_device *dev = priv->ndev;
1553
1554         if (dev->flags & IFF_UP) {
1555                 netif_stop_queue(dev);
1556                 stop_gfar(dev);
1557                 startup_gfar(dev);
1558                 netif_start_queue(dev);
1559         }
1560
1561         netif_tx_schedule_all(dev);
1562 }
1563
1564 static void gfar_timeout(struct net_device *dev)
1565 {
1566         struct gfar_private *priv = netdev_priv(dev);
1567
1568         dev->stats.tx_errors++;
1569         schedule_work(&priv->reset_task);
1570 }
1571
1572 /* Interrupt Handler for Transmit complete */
1573 static int gfar_clean_tx_ring(struct net_device *dev)
1574 {
1575         struct gfar_private *priv = netdev_priv(dev);
1576         struct txbd8 *bdp;
1577         struct txbd8 *lbdp = NULL;
1578         struct txbd8 *base = priv->tx_bd_base;
1579         struct sk_buff *skb;
1580         int skb_dirtytx;
1581         int tx_ring_size = priv->tx_ring_size;
1582         int frags = 0;
1583         int i;
1584         int howmany = 0;
1585         u32 lstatus;
1586
1587         bdp = priv->dirty_tx;
1588         skb_dirtytx = priv->skb_dirtytx;
1589
1590         while ((skb = priv->tx_skbuff[skb_dirtytx])) {
1591                 frags = skb_shinfo(skb)->nr_frags;
1592                 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1593
1594                 lstatus = lbdp->lstatus;
1595
1596                 /* Only clean completed frames */
1597                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1598                                 (lstatus & BD_LENGTH_MASK))
1599                         break;
1600
1601                 dma_unmap_single(&priv->ofdev->dev,
1602                                 bdp->bufPtr,
1603                                 bdp->length,
1604                                 DMA_TO_DEVICE);
1605
1606                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1607                 bdp = next_txbd(bdp, base, tx_ring_size);
1608
1609                 for (i = 0; i < frags; i++) {
1610                         dma_unmap_page(&priv->ofdev->dev,
1611                                         bdp->bufPtr,
1612                                         bdp->length,
1613                                         DMA_TO_DEVICE);
1614                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1615                         bdp = next_txbd(bdp, base, tx_ring_size);
1616                 }
1617
1618                 /*
1619                  * If there's room in the queue (limit it to rx_buffer_size)
1620                  * we add this skb back into the pool, if it's the right size
1621                  */
1622                 if (skb_queue_len(&priv->rx_recycle) < priv->rx_ring_size &&
1623                                 skb_recycle_check(skb, priv->rx_buffer_size +
1624                                         RXBUF_ALIGNMENT))
1625                         __skb_queue_head(&priv->rx_recycle, skb);
1626                 else
1627                         dev_kfree_skb_any(skb);
1628
1629                 priv->tx_skbuff[skb_dirtytx] = NULL;
1630
1631                 skb_dirtytx = (skb_dirtytx + 1) &
1632                         TX_RING_MOD_MASK(tx_ring_size);
1633
1634                 howmany++;
1635                 priv->num_txbdfree += frags + 1;
1636         }
1637
1638         /* If we freed a buffer, we can restart transmission, if necessary */
1639         if (netif_queue_stopped(dev) && priv->num_txbdfree)
1640                 netif_wake_queue(dev);
1641
1642         /* Update dirty indicators */
1643         priv->skb_dirtytx = skb_dirtytx;
1644         priv->dirty_tx = bdp;
1645
1646         dev->stats.tx_packets += howmany;
1647
1648         return howmany;
1649 }
1650
1651 static void gfar_schedule_cleanup(struct net_device *dev)
1652 {
1653         struct gfar_private *priv = netdev_priv(dev);
1654         unsigned long flags;
1655
1656         spin_lock_irqsave(&priv->txlock, flags);
1657         spin_lock(&priv->rxlock);
1658
1659         if (napi_schedule_prep(&priv->napi)) {
1660                 gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
1661                 __napi_schedule(&priv->napi);
1662         } else {
1663                 /*
1664                  * Clear IEVENT, so interrupts aren't called again
1665                  * because of the packets that have already arrived.
1666                  */
1667                 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1668         }
1669
1670         spin_unlock(&priv->rxlock);
1671         spin_unlock_irqrestore(&priv->txlock, flags);
1672 }
1673
1674 /* Interrupt Handler for Transmit complete */
1675 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1676 {
1677         gfar_schedule_cleanup((struct net_device *)dev_id);
1678         return IRQ_HANDLED;
1679 }
1680
1681 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1682                 struct sk_buff *skb)
1683 {
1684         struct gfar_private *priv = netdev_priv(dev);
1685         u32 lstatus;
1686
1687         bdp->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1688                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1689
1690         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
1691
1692         if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1693                 lstatus |= BD_LFLAG(RXBD_WRAP);
1694
1695         eieio();
1696
1697         bdp->lstatus = lstatus;
1698 }
1699
1700
1701 struct sk_buff * gfar_new_skb(struct net_device *dev)
1702 {
1703         unsigned int alignamount;
1704         struct gfar_private *priv = netdev_priv(dev);
1705         struct sk_buff *skb = NULL;
1706
1707         skb = __skb_dequeue(&priv->rx_recycle);
1708         if (!skb)
1709                 skb = netdev_alloc_skb(dev,
1710                                 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1711
1712         if (!skb)
1713                 return NULL;
1714
1715         alignamount = RXBUF_ALIGNMENT -
1716                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1717
1718         /* We need the data buffer to be aligned properly.  We will reserve
1719          * as many bytes as needed to align the data properly
1720          */
1721         skb_reserve(skb, alignamount);
1722
1723         return skb;
1724 }
1725
1726 static inline void count_errors(unsigned short status, struct net_device *dev)
1727 {
1728         struct gfar_private *priv = netdev_priv(dev);
1729         struct net_device_stats *stats = &dev->stats;
1730         struct gfar_extra_stats *estats = &priv->extra_stats;
1731
1732         /* If the packet was truncated, none of the other errors
1733          * matter */
1734         if (status & RXBD_TRUNCATED) {
1735                 stats->rx_length_errors++;
1736
1737                 estats->rx_trunc++;
1738
1739                 return;
1740         }
1741         /* Count the errors, if there were any */
1742         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1743                 stats->rx_length_errors++;
1744
1745                 if (status & RXBD_LARGE)
1746                         estats->rx_large++;
1747                 else
1748                         estats->rx_short++;
1749         }
1750         if (status & RXBD_NONOCTET) {
1751                 stats->rx_frame_errors++;
1752                 estats->rx_nonoctet++;
1753         }
1754         if (status & RXBD_CRCERR) {
1755                 estats->rx_crcerr++;
1756                 stats->rx_crc_errors++;
1757         }
1758         if (status & RXBD_OVERRUN) {
1759                 estats->rx_overrun++;
1760                 stats->rx_crc_errors++;
1761         }
1762 }
1763
1764 irqreturn_t gfar_receive(int irq, void *dev_id)
1765 {
1766         gfar_schedule_cleanup((struct net_device *)dev_id);
1767         return IRQ_HANDLED;
1768 }
1769
1770 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1771 {
1772         /* If valid headers were found, and valid sums
1773          * were verified, then we tell the kernel that no
1774          * checksumming is necessary.  Otherwise, it is */
1775         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1776                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1777         else
1778                 skb->ip_summed = CHECKSUM_NONE;
1779 }
1780
1781
1782 /* gfar_process_frame() -- handle one incoming packet if skb
1783  * isn't NULL.  */
1784 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1785                               int amount_pull)
1786 {
1787         struct gfar_private *priv = netdev_priv(dev);
1788         struct rxfcb *fcb = NULL;
1789
1790         int ret;
1791
1792         /* fcb is at the beginning if exists */
1793         fcb = (struct rxfcb *)skb->data;
1794
1795         /* Remove the FCB from the skb */
1796         /* Remove the padded bytes, if there are any */
1797         if (amount_pull)
1798                 skb_pull(skb, amount_pull);
1799
1800         if (priv->rx_csum_enable)
1801                 gfar_rx_checksum(skb, fcb);
1802
1803         /* Tell the skb what kind of packet this is */
1804         skb->protocol = eth_type_trans(skb, dev);
1805
1806         /* Send the packet up the stack */
1807         if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1808                 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1809         else
1810                 ret = netif_receive_skb(skb);
1811
1812         if (NET_RX_DROP == ret)
1813                 priv->extra_stats.kernel_dropped++;
1814
1815         return 0;
1816 }
1817
1818 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1819  *   until the budget/quota has been reached. Returns the number
1820  *   of frames handled
1821  */
1822 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1823 {
1824         struct rxbd8 *bdp, *base;
1825         struct sk_buff *skb;
1826         int pkt_len;
1827         int amount_pull;
1828         int howmany = 0;
1829         struct gfar_private *priv = netdev_priv(dev);
1830
1831         /* Get the first full descriptor */
1832         bdp = priv->cur_rx;
1833         base = priv->rx_bd_base;
1834
1835         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1836                 priv->padding;
1837
1838         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1839                 struct sk_buff *newskb;
1840                 rmb();
1841
1842                 /* Add another skb for the future */
1843                 newskb = gfar_new_skb(dev);
1844
1845                 skb = priv->rx_skbuff[priv->skb_currx];
1846
1847                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
1848                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
1849
1850                 /* We drop the frame if we failed to allocate a new buffer */
1851                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1852                                  bdp->status & RXBD_ERR)) {
1853                         count_errors(bdp->status, dev);
1854
1855                         if (unlikely(!newskb))
1856                                 newskb = skb;
1857                         else if (skb) {
1858                                 /*
1859                                  * We need to reset ->data to what it
1860                                  * was before gfar_new_skb() re-aligned
1861                                  * it to an RXBUF_ALIGNMENT boundary
1862                                  * before we put the skb back on the
1863                                  * recycle list.
1864                                  */
1865                                 skb->data = skb->head + NET_SKB_PAD;
1866                                 __skb_queue_head(&priv->rx_recycle, skb);
1867                         }
1868                 } else {
1869                         /* Increment the number of packets */
1870                         dev->stats.rx_packets++;
1871                         howmany++;
1872
1873                         if (likely(skb)) {
1874                                 pkt_len = bdp->length - ETH_FCS_LEN;
1875                                 /* Remove the FCS from the packet length */
1876                                 skb_put(skb, pkt_len);
1877                                 dev->stats.rx_bytes += pkt_len;
1878
1879                                 if (in_irq() || irqs_disabled())
1880                                         printk("Interrupt problem!\n");
1881                                 gfar_process_frame(dev, skb, amount_pull);
1882
1883                         } else {
1884                                 if (netif_msg_rx_err(priv))
1885                                         printk(KERN_WARNING
1886                                                "%s: Missing skb!\n", dev->name);
1887                                 dev->stats.rx_dropped++;
1888                                 priv->extra_stats.rx_skbmissing++;
1889                         }
1890
1891                 }
1892
1893                 priv->rx_skbuff[priv->skb_currx] = newskb;
1894
1895                 /* Setup the new bdp */
1896                 gfar_new_rxbdp(dev, bdp, newskb);
1897
1898                 /* Update to the next pointer */
1899                 bdp = next_bd(bdp, base, priv->rx_ring_size);
1900
1901                 /* update to point at the next skb */
1902                 priv->skb_currx =
1903                     (priv->skb_currx + 1) &
1904                     RX_RING_MOD_MASK(priv->rx_ring_size);
1905         }
1906
1907         /* Update the current rxbd pointer to be the next one */
1908         priv->cur_rx = bdp;
1909
1910         return howmany;
1911 }
1912
1913 static int gfar_poll(struct napi_struct *napi, int budget)
1914 {
1915         struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1916         struct net_device *dev = priv->ndev;
1917         int tx_cleaned = 0;
1918         int rx_cleaned = 0;
1919         unsigned long flags;
1920
1921         /* Clear IEVENT, so interrupts aren't called again
1922          * because of the packets that have already arrived */
1923         gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1924
1925         /* If we fail to get the lock, don't bother with the TX BDs */
1926         if (spin_trylock_irqsave(&priv->txlock, flags)) {
1927                 tx_cleaned = gfar_clean_tx_ring(dev);
1928                 spin_unlock_irqrestore(&priv->txlock, flags);
1929         }
1930
1931         rx_cleaned = gfar_clean_rx_ring(dev, budget);
1932
1933         if (tx_cleaned)
1934                 return budget;
1935
1936         if (rx_cleaned < budget) {
1937                 napi_complete(napi);
1938
1939                 /* Clear the halt bit in RSTAT */
1940                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1941
1942                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1943
1944                 /* If we are coalescing interrupts, update the timer */
1945                 /* Otherwise, clear it */
1946                 if (likely(priv->rxcoalescing)) {
1947                         gfar_write(&priv->regs->rxic, 0);
1948                         gfar_write(&priv->regs->rxic, priv->rxic);
1949                 }
1950                 if (likely(priv->txcoalescing)) {
1951                         gfar_write(&priv->regs->txic, 0);
1952                         gfar_write(&priv->regs->txic, priv->txic);
1953                 }
1954         }
1955
1956         return rx_cleaned;
1957 }
1958
1959 #ifdef CONFIG_NET_POLL_CONTROLLER
1960 /*
1961  * Polling 'interrupt' - used by things like netconsole to send skbs
1962  * without having to re-enable interrupts. It's not called while
1963  * the interrupt routine is executing.
1964  */
1965 static void gfar_netpoll(struct net_device *dev)
1966 {
1967         struct gfar_private *priv = netdev_priv(dev);
1968
1969         /* If the device has multiple interrupts, run tx/rx */
1970         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1971                 disable_irq(priv->interruptTransmit);
1972                 disable_irq(priv->interruptReceive);
1973                 disable_irq(priv->interruptError);
1974                 gfar_interrupt(priv->interruptTransmit, dev);
1975                 enable_irq(priv->interruptError);
1976                 enable_irq(priv->interruptReceive);
1977                 enable_irq(priv->interruptTransmit);
1978         } else {
1979                 disable_irq(priv->interruptTransmit);
1980                 gfar_interrupt(priv->interruptTransmit, dev);
1981                 enable_irq(priv->interruptTransmit);
1982         }
1983 }
1984 #endif
1985
1986 /* The interrupt handler for devices with one interrupt */
1987 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1988 {
1989         struct net_device *dev = dev_id;
1990         struct gfar_private *priv = netdev_priv(dev);
1991
1992         /* Save ievent for future reference */
1993         u32 events = gfar_read(&priv->regs->ievent);
1994
1995         /* Check for reception */
1996         if (events & IEVENT_RX_MASK)
1997                 gfar_receive(irq, dev_id);
1998
1999         /* Check for transmit completion */
2000         if (events & IEVENT_TX_MASK)
2001                 gfar_transmit(irq, dev_id);
2002
2003         /* Check for errors */
2004         if (events & IEVENT_ERR_MASK)
2005                 gfar_error(irq, dev_id);
2006
2007         return IRQ_HANDLED;
2008 }
2009
2010 /* Called every time the controller might need to be made
2011  * aware of new link state.  The PHY code conveys this
2012  * information through variables in the phydev structure, and this
2013  * function converts those variables into the appropriate
2014  * register values, and can bring down the device if needed.
2015  */
2016 static void adjust_link(struct net_device *dev)
2017 {
2018         struct gfar_private *priv = netdev_priv(dev);
2019         struct gfar __iomem *regs = priv->regs;
2020         unsigned long flags;
2021         struct phy_device *phydev = priv->phydev;
2022         int new_state = 0;
2023
2024         spin_lock_irqsave(&priv->txlock, flags);
2025         if (phydev->link) {
2026                 u32 tempval = gfar_read(&regs->maccfg2);
2027                 u32 ecntrl = gfar_read(&regs->ecntrl);
2028
2029                 /* Now we make sure that we can be in full duplex mode.
2030                  * If not, we operate in half-duplex mode. */
2031                 if (phydev->duplex != priv->oldduplex) {
2032                         new_state = 1;
2033                         if (!(phydev->duplex))
2034                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2035                         else
2036                                 tempval |= MACCFG2_FULL_DUPLEX;
2037
2038                         priv->oldduplex = phydev->duplex;
2039                 }
2040
2041                 if (phydev->speed != priv->oldspeed) {
2042                         new_state = 1;
2043                         switch (phydev->speed) {
2044                         case 1000:
2045                                 tempval =
2046                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2047
2048                                 ecntrl &= ~(ECNTRL_R100);
2049                                 break;
2050                         case 100:
2051                         case 10:
2052                                 tempval =
2053                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2054
2055                                 /* Reduced mode distinguishes
2056                                  * between 10 and 100 */
2057                                 if (phydev->speed == SPEED_100)
2058                                         ecntrl |= ECNTRL_R100;
2059                                 else
2060                                         ecntrl &= ~(ECNTRL_R100);
2061                                 break;
2062                         default:
2063                                 if (netif_msg_link(priv))
2064                                         printk(KERN_WARNING
2065                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
2066                                                 dev->name, phydev->speed);
2067                                 break;
2068                         }
2069
2070                         priv->oldspeed = phydev->speed;
2071                 }
2072
2073                 gfar_write(&regs->maccfg2, tempval);
2074                 gfar_write(&regs->ecntrl, ecntrl);
2075
2076                 if (!priv->oldlink) {
2077                         new_state = 1;
2078                         priv->oldlink = 1;
2079                 }
2080         } else if (priv->oldlink) {
2081                 new_state = 1;
2082                 priv->oldlink = 0;
2083                 priv->oldspeed = 0;
2084                 priv->oldduplex = -1;
2085         }
2086
2087         if (new_state && netif_msg_link(priv))
2088                 phy_print_status(phydev);
2089
2090         spin_unlock_irqrestore(&priv->txlock, flags);
2091 }
2092
2093 /* Update the hash table based on the current list of multicast
2094  * addresses we subscribe to.  Also, change the promiscuity of
2095  * the device based on the flags (this function is called
2096  * whenever dev->flags is changed */
2097 static void gfar_set_multi(struct net_device *dev)
2098 {
2099         struct dev_mc_list *mc_ptr;
2100         struct gfar_private *priv = netdev_priv(dev);
2101         struct gfar __iomem *regs = priv->regs;
2102         u32 tempval;
2103
2104         if(dev->flags & IFF_PROMISC) {
2105                 /* Set RCTRL to PROM */
2106                 tempval = gfar_read(&regs->rctrl);
2107                 tempval |= RCTRL_PROM;
2108                 gfar_write(&regs->rctrl, tempval);
2109         } else {
2110                 /* Set RCTRL to not PROM */
2111                 tempval = gfar_read(&regs->rctrl);
2112                 tempval &= ~(RCTRL_PROM);
2113                 gfar_write(&regs->rctrl, tempval);
2114         }
2115
2116         if(dev->flags & IFF_ALLMULTI) {
2117                 /* Set the hash to rx all multicast frames */
2118                 gfar_write(&regs->igaddr0, 0xffffffff);
2119                 gfar_write(&regs->igaddr1, 0xffffffff);
2120                 gfar_write(&regs->igaddr2, 0xffffffff);
2121                 gfar_write(&regs->igaddr3, 0xffffffff);
2122                 gfar_write(&regs->igaddr4, 0xffffffff);
2123                 gfar_write(&regs->igaddr5, 0xffffffff);
2124                 gfar_write(&regs->igaddr6, 0xffffffff);
2125                 gfar_write(&regs->igaddr7, 0xffffffff);
2126                 gfar_write(&regs->gaddr0, 0xffffffff);
2127                 gfar_write(&regs->gaddr1, 0xffffffff);
2128                 gfar_write(&regs->gaddr2, 0xffffffff);
2129                 gfar_write(&regs->gaddr3, 0xffffffff);
2130                 gfar_write(&regs->gaddr4, 0xffffffff);
2131                 gfar_write(&regs->gaddr5, 0xffffffff);
2132                 gfar_write(&regs->gaddr6, 0xffffffff);
2133                 gfar_write(&regs->gaddr7, 0xffffffff);
2134         } else {
2135                 int em_num;
2136                 int idx;
2137
2138                 /* zero out the hash */
2139                 gfar_write(&regs->igaddr0, 0x0);
2140                 gfar_write(&regs->igaddr1, 0x0);
2141                 gfar_write(&regs->igaddr2, 0x0);
2142                 gfar_write(&regs->igaddr3, 0x0);
2143                 gfar_write(&regs->igaddr4, 0x0);
2144                 gfar_write(&regs->igaddr5, 0x0);
2145                 gfar_write(&regs->igaddr6, 0x0);
2146                 gfar_write(&regs->igaddr7, 0x0);
2147                 gfar_write(&regs->gaddr0, 0x0);
2148                 gfar_write(&regs->gaddr1, 0x0);
2149                 gfar_write(&regs->gaddr2, 0x0);
2150                 gfar_write(&regs->gaddr3, 0x0);
2151                 gfar_write(&regs->gaddr4, 0x0);
2152                 gfar_write(&regs->gaddr5, 0x0);
2153                 gfar_write(&regs->gaddr6, 0x0);
2154                 gfar_write(&regs->gaddr7, 0x0);
2155
2156                 /* If we have extended hash tables, we need to
2157                  * clear the exact match registers to prepare for
2158                  * setting them */
2159                 if (priv->extended_hash) {
2160                         em_num = GFAR_EM_NUM + 1;
2161                         gfar_clear_exact_match(dev);
2162                         idx = 1;
2163                 } else {
2164                         idx = 0;
2165                         em_num = 0;
2166                 }
2167
2168                 if(dev->mc_count == 0)
2169                         return;
2170
2171                 /* Parse the list, and set the appropriate bits */
2172                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2173                         if (idx < em_num) {
2174                                 gfar_set_mac_for_addr(dev, idx,
2175                                                 mc_ptr->dmi_addr);
2176                                 idx++;
2177                         } else
2178                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2179                 }
2180         }
2181
2182         return;
2183 }
2184
2185
2186 /* Clears each of the exact match registers to zero, so they
2187  * don't interfere with normal reception */
2188 static void gfar_clear_exact_match(struct net_device *dev)
2189 {
2190         int idx;
2191         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2192
2193         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2194                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2195 }
2196
2197 /* Set the appropriate hash bit for the given addr */
2198 /* The algorithm works like so:
2199  * 1) Take the Destination Address (ie the multicast address), and
2200  * do a CRC on it (little endian), and reverse the bits of the
2201  * result.
2202  * 2) Use the 8 most significant bits as a hash into a 256-entry
2203  * table.  The table is controlled through 8 32-bit registers:
2204  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
2205  * gaddr7.  This means that the 3 most significant bits in the
2206  * hash index which gaddr register to use, and the 5 other bits
2207  * indicate which bit (assuming an IBM numbering scheme, which
2208  * for PowerPC (tm) is usually the case) in the register holds
2209  * the entry. */
2210 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2211 {
2212         u32 tempval;
2213         struct gfar_private *priv = netdev_priv(dev);
2214         u32 result = ether_crc(MAC_ADDR_LEN, addr);
2215         int width = priv->hash_width;
2216         u8 whichbit = (result >> (32 - width)) & 0x1f;
2217         u8 whichreg = result >> (32 - width + 5);
2218         u32 value = (1 << (31-whichbit));
2219
2220         tempval = gfar_read(priv->hash_regs[whichreg]);
2221         tempval |= value;
2222         gfar_write(priv->hash_regs[whichreg], tempval);
2223
2224         return;
2225 }
2226
2227
2228 /* There are multiple MAC Address register pairs on some controllers
2229  * This function sets the numth pair to a given address
2230  */
2231 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2232 {
2233         struct gfar_private *priv = netdev_priv(dev);
2234         int idx;
2235         char tmpbuf[MAC_ADDR_LEN];
2236         u32 tempval;
2237         u32 __iomem *macptr = &priv->regs->macstnaddr1;
2238
2239         macptr += num*2;
2240
2241         /* Now copy it into the mac registers backwards, cuz */
2242         /* little endian is silly */
2243         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2244                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2245
2246         gfar_write(macptr, *((u32 *) (tmpbuf)));
2247
2248         tempval = *((u32 *) (tmpbuf + 4));
2249
2250         gfar_write(macptr+1, tempval);
2251 }
2252
2253 /* GFAR error interrupt handler */
2254 static irqreturn_t gfar_error(int irq, void *dev_id)
2255 {
2256         struct net_device *dev = dev_id;
2257         struct gfar_private *priv = netdev_priv(dev);
2258
2259         /* Save ievent for future reference */
2260         u32 events = gfar_read(&priv->regs->ievent);
2261
2262         /* Clear IEVENT */
2263         gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2264
2265         /* Magic Packet is not an error. */
2266         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2267             (events & IEVENT_MAG))
2268                 events &= ~IEVENT_MAG;
2269
2270         /* Hmm... */
2271         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2272                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2273                        dev->name, events, gfar_read(&priv->regs->imask));
2274
2275         /* Update the error counters */
2276         if (events & IEVENT_TXE) {
2277                 dev->stats.tx_errors++;
2278
2279                 if (events & IEVENT_LC)
2280                         dev->stats.tx_window_errors++;
2281                 if (events & IEVENT_CRL)
2282                         dev->stats.tx_aborted_errors++;
2283                 if (events & IEVENT_XFUN) {
2284                         if (netif_msg_tx_err(priv))
2285                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2286                                        "packet dropped.\n", dev->name);
2287                         dev->stats.tx_dropped++;
2288                         priv->extra_stats.tx_underrun++;
2289
2290                         /* Reactivate the Tx Queues */
2291                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2292                 }
2293                 if (netif_msg_tx_err(priv))
2294                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2295         }
2296         if (events & IEVENT_BSY) {
2297                 dev->stats.rx_errors++;
2298                 priv->extra_stats.rx_bsy++;
2299
2300                 gfar_receive(irq, dev_id);
2301
2302                 if (netif_msg_rx_err(priv))
2303                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2304                                dev->name, gfar_read(&priv->regs->rstat));
2305         }
2306         if (events & IEVENT_BABR) {
2307                 dev->stats.rx_errors++;
2308                 priv->extra_stats.rx_babr++;
2309
2310                 if (netif_msg_rx_err(priv))
2311                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2312         }
2313         if (events & IEVENT_EBERR) {
2314                 priv->extra_stats.eberr++;
2315                 if (netif_msg_rx_err(priv))
2316                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
2317         }
2318         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2319                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2320
2321         if (events & IEVENT_BABT) {
2322                 priv->extra_stats.tx_babt++;
2323                 if (netif_msg_tx_err(priv))
2324                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2325         }
2326         return IRQ_HANDLED;
2327 }
2328
2329 /* work with hotplug and coldplug */
2330 MODULE_ALIAS("platform:fsl-gianfar");
2331
2332 static struct of_device_id gfar_match[] =
2333 {
2334         {
2335                 .type = "network",
2336                 .compatible = "gianfar",
2337         },
2338         {},
2339 };
2340
2341 /* Structure for a device driver */
2342 static struct of_platform_driver gfar_driver = {
2343         .name = "fsl-gianfar",
2344         .match_table = gfar_match,
2345
2346         .probe = gfar_probe,
2347         .remove = gfar_remove,
2348         .suspend = gfar_suspend,
2349         .resume = gfar_resume,
2350 };
2351
2352 static int __init gfar_init(void)
2353 {
2354         return of_register_platform_driver(&gfar_driver);
2355 }
2356
2357 static void __exit gfar_exit(void)
2358 {
2359         of_unregister_platform_driver(&gfar_driver);
2360 }
2361
2362 module_init(gfar_init);
2363 module_exit(gfar_exit);
2364