drm/i915: pipelined fencing, part 2: fence setup
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 12 Feb 2010 08:26:33 +0000 (09:26 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 2 Mar 2010 22:53:02 +0000 (23:53 +0100)
commitd339c55788aaac4e2f6b6795bb68c48b7a04a2b1
treef9595493200b885fe537aaa2d9801ee5bc3cca44
parent89c3a5642569cb1800411d964a7352c440efa1f8
drm/i915: pipelined fencing, part 2: fence setup

This wires the fence setup part up. I've also implemented pipelined
fence setup for 4th gen chips - this may be useful when the pageflip
code switches to pipelined fencing.

With this change, every batchbuffer can use all available fences (save
pinned and scanout, of course) without ever stalling the gpu!

v2: Code in intel_display.c tried to be clever and not uncondionally
call i915_gem_object_get_fence_reg, which screws up fence state.

v3: Work around hw oddities. I've found out that the official
intel docs don't tell the whole story about MI_LOAD_REGISTER_IMM.
I've documented my findings in i915_reg.h

v4: Adapt to Sandybridge support.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_display.c