drm/i915: Don't reserve compatibility fence regs in KMS mode.
[daniel-s-linux-stuff:linux-kernel.git] / drivers / gpu / drm / i915 / i915_gem.c
1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <eric@anholt.net>
25  *
26  */
27
28 #include "drmP.h"
29 #include "drm.h"
30 #include "i915_drm.h"
31 #include "i915_drv.h"
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/swap.h>
35 #include <linux/pci.h>
36
37 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
38
39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
43                                              int write);
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
45                                                      uint64_t offset,
46                                                      uint64_t size);
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
50                                            unsigned alignment);
51 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
52 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
53 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
54 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55                                 struct drm_i915_gem_pwrite *args,
56                                 struct drm_file *file_priv);
57
58 static LIST_HEAD(shrink_list);
59 static DEFINE_SPINLOCK(shrink_list_lock);
60
61 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
62                      unsigned long end)
63 {
64         drm_i915_private_t *dev_priv = dev->dev_private;
65
66         if (start >= end ||
67             (start & (PAGE_SIZE - 1)) != 0 ||
68             (end & (PAGE_SIZE - 1)) != 0) {
69                 return -EINVAL;
70         }
71
72         drm_mm_init(&dev_priv->mm.gtt_space, start,
73                     end - start);
74
75         dev->gtt_total = (uint32_t) (end - start);
76
77         return 0;
78 }
79
80 int
81 i915_gem_init_ioctl(struct drm_device *dev, void *data,
82                     struct drm_file *file_priv)
83 {
84         struct drm_i915_gem_init *args = data;
85         int ret;
86
87         mutex_lock(&dev->struct_mutex);
88         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
89         mutex_unlock(&dev->struct_mutex);
90
91         return ret;
92 }
93
94 int
95 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96                             struct drm_file *file_priv)
97 {
98         struct drm_i915_gem_get_aperture *args = data;
99
100         if (!(dev->driver->driver_features & DRIVER_GEM))
101                 return -ENODEV;
102
103         args->aper_size = dev->gtt_total;
104         args->aper_available_size = (args->aper_size -
105                                      atomic_read(&dev->pin_memory));
106
107         return 0;
108 }
109
110
111 /**
112  * Creates a new mm object and returns a handle to it.
113  */
114 int
115 i915_gem_create_ioctl(struct drm_device *dev, void *data,
116                       struct drm_file *file_priv)
117 {
118         struct drm_i915_gem_create *args = data;
119         struct drm_gem_object *obj;
120         int ret;
121         u32 handle;
122
123         args->size = roundup(args->size, PAGE_SIZE);
124
125         /* Allocate the new object */
126         obj = drm_gem_object_alloc(dev, args->size);
127         if (obj == NULL)
128                 return -ENOMEM;
129
130         ret = drm_gem_handle_create(file_priv, obj, &handle);
131         mutex_lock(&dev->struct_mutex);
132         drm_gem_object_handle_unreference(obj);
133         mutex_unlock(&dev->struct_mutex);
134
135         if (ret)
136                 return ret;
137
138         args->handle = handle;
139
140         return 0;
141 }
142
143 static inline int
144 fast_shmem_read(struct page **pages,
145                 loff_t page_base, int page_offset,
146                 char __user *data,
147                 int length)
148 {
149         char __iomem *vaddr;
150         int unwritten;
151
152         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
153         if (vaddr == NULL)
154                 return -ENOMEM;
155         unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
156         kunmap_atomic(vaddr, KM_USER0);
157
158         if (unwritten)
159                 return -EFAULT;
160
161         return 0;
162 }
163
164 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
165 {
166         drm_i915_private_t *dev_priv = obj->dev->dev_private;
167         struct drm_i915_gem_object *obj_priv = obj->driver_private;
168
169         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
170                 obj_priv->tiling_mode != I915_TILING_NONE;
171 }
172
173 static inline int
174 slow_shmem_copy(struct page *dst_page,
175                 int dst_offset,
176                 struct page *src_page,
177                 int src_offset,
178                 int length)
179 {
180         char *dst_vaddr, *src_vaddr;
181
182         dst_vaddr = kmap_atomic(dst_page, KM_USER0);
183         if (dst_vaddr == NULL)
184                 return -ENOMEM;
185
186         src_vaddr = kmap_atomic(src_page, KM_USER1);
187         if (src_vaddr == NULL) {
188                 kunmap_atomic(dst_vaddr, KM_USER0);
189                 return -ENOMEM;
190         }
191
192         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
193
194         kunmap_atomic(src_vaddr, KM_USER1);
195         kunmap_atomic(dst_vaddr, KM_USER0);
196
197         return 0;
198 }
199
200 static inline int
201 slow_shmem_bit17_copy(struct page *gpu_page,
202                       int gpu_offset,
203                       struct page *cpu_page,
204                       int cpu_offset,
205                       int length,
206                       int is_read)
207 {
208         char *gpu_vaddr, *cpu_vaddr;
209
210         /* Use the unswizzled path if this page isn't affected. */
211         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
212                 if (is_read)
213                         return slow_shmem_copy(cpu_page, cpu_offset,
214                                                gpu_page, gpu_offset, length);
215                 else
216                         return slow_shmem_copy(gpu_page, gpu_offset,
217                                                cpu_page, cpu_offset, length);
218         }
219
220         gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
221         if (gpu_vaddr == NULL)
222                 return -ENOMEM;
223
224         cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
225         if (cpu_vaddr == NULL) {
226                 kunmap_atomic(gpu_vaddr, KM_USER0);
227                 return -ENOMEM;
228         }
229
230         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231          * XORing with the other bits (A9 for Y, A9 and A10 for X)
232          */
233         while (length > 0) {
234                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
235                 int this_length = min(cacheline_end - gpu_offset, length);
236                 int swizzled_gpu_offset = gpu_offset ^ 64;
237
238                 if (is_read) {
239                         memcpy(cpu_vaddr + cpu_offset,
240                                gpu_vaddr + swizzled_gpu_offset,
241                                this_length);
242                 } else {
243                         memcpy(gpu_vaddr + swizzled_gpu_offset,
244                                cpu_vaddr + cpu_offset,
245                                this_length);
246                 }
247                 cpu_offset += this_length;
248                 gpu_offset += this_length;
249                 length -= this_length;
250         }
251
252         kunmap_atomic(cpu_vaddr, KM_USER1);
253         kunmap_atomic(gpu_vaddr, KM_USER0);
254
255         return 0;
256 }
257
258 /**
259  * This is the fast shmem pread path, which attempts to copy_from_user directly
260  * from the backing pages of the object to the user's address space.  On a
261  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
262  */
263 static int
264 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
265                           struct drm_i915_gem_pread *args,
266                           struct drm_file *file_priv)
267 {
268         struct drm_i915_gem_object *obj_priv = obj->driver_private;
269         ssize_t remain;
270         loff_t offset, page_base;
271         char __user *user_data;
272         int page_offset, page_length;
273         int ret;
274
275         user_data = (char __user *) (uintptr_t) args->data_ptr;
276         remain = args->size;
277
278         mutex_lock(&dev->struct_mutex);
279
280         ret = i915_gem_object_get_pages(obj, 0);
281         if (ret != 0)
282                 goto fail_unlock;
283
284         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
285                                                         args->size);
286         if (ret != 0)
287                 goto fail_put_pages;
288
289         obj_priv = obj->driver_private;
290         offset = args->offset;
291
292         while (remain > 0) {
293                 /* Operation in this page
294                  *
295                  * page_base = page offset within aperture
296                  * page_offset = offset within page
297                  * page_length = bytes to copy for this page
298                  */
299                 page_base = (offset & ~(PAGE_SIZE-1));
300                 page_offset = offset & (PAGE_SIZE-1);
301                 page_length = remain;
302                 if ((page_offset + remain) > PAGE_SIZE)
303                         page_length = PAGE_SIZE - page_offset;
304
305                 ret = fast_shmem_read(obj_priv->pages,
306                                       page_base, page_offset,
307                                       user_data, page_length);
308                 if (ret)
309                         goto fail_put_pages;
310
311                 remain -= page_length;
312                 user_data += page_length;
313                 offset += page_length;
314         }
315
316 fail_put_pages:
317         i915_gem_object_put_pages(obj);
318 fail_unlock:
319         mutex_unlock(&dev->struct_mutex);
320
321         return ret;
322 }
323
324 static int
325 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
326 {
327         int ret;
328
329         ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
330
331         /* If we've insufficient memory to map in the pages, attempt
332          * to make some space by throwing out some old buffers.
333          */
334         if (ret == -ENOMEM) {
335                 struct drm_device *dev = obj->dev;
336
337                 ret = i915_gem_evict_something(dev, obj->size);
338                 if (ret)
339                         return ret;
340
341                 ret = i915_gem_object_get_pages(obj, 0);
342         }
343
344         return ret;
345 }
346
347 /**
348  * This is the fallback shmem pread path, which allocates temporary storage
349  * in kernel space to copy_to_user into outside of the struct_mutex, so we
350  * can copy out of the object's backing pages while holding the struct mutex
351  * and not take page faults.
352  */
353 static int
354 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
355                           struct drm_i915_gem_pread *args,
356                           struct drm_file *file_priv)
357 {
358         struct drm_i915_gem_object *obj_priv = obj->driver_private;
359         struct mm_struct *mm = current->mm;
360         struct page **user_pages;
361         ssize_t remain;
362         loff_t offset, pinned_pages, i;
363         loff_t first_data_page, last_data_page, num_pages;
364         int shmem_page_index, shmem_page_offset;
365         int data_page_index,  data_page_offset;
366         int page_length;
367         int ret;
368         uint64_t data_ptr = args->data_ptr;
369         int do_bit17_swizzling;
370
371         remain = args->size;
372
373         /* Pin the user pages containing the data.  We can't fault while
374          * holding the struct mutex, yet we want to hold it while
375          * dereferencing the user data.
376          */
377         first_data_page = data_ptr / PAGE_SIZE;
378         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
379         num_pages = last_data_page - first_data_page + 1;
380
381         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
382         if (user_pages == NULL)
383                 return -ENOMEM;
384
385         down_read(&mm->mmap_sem);
386         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
387                                       num_pages, 1, 0, user_pages, NULL);
388         up_read(&mm->mmap_sem);
389         if (pinned_pages < num_pages) {
390                 ret = -EFAULT;
391                 goto fail_put_user_pages;
392         }
393
394         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
395
396         mutex_lock(&dev->struct_mutex);
397
398         ret = i915_gem_object_get_pages_or_evict(obj);
399         if (ret)
400                 goto fail_unlock;
401
402         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
403                                                         args->size);
404         if (ret != 0)
405                 goto fail_put_pages;
406
407         obj_priv = obj->driver_private;
408         offset = args->offset;
409
410         while (remain > 0) {
411                 /* Operation in this page
412                  *
413                  * shmem_page_index = page number within shmem file
414                  * shmem_page_offset = offset within page in shmem file
415                  * data_page_index = page number in get_user_pages return
416                  * data_page_offset = offset with data_page_index page.
417                  * page_length = bytes to copy for this page
418                  */
419                 shmem_page_index = offset / PAGE_SIZE;
420                 shmem_page_offset = offset & ~PAGE_MASK;
421                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
422                 data_page_offset = data_ptr & ~PAGE_MASK;
423
424                 page_length = remain;
425                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
426                         page_length = PAGE_SIZE - shmem_page_offset;
427                 if ((data_page_offset + page_length) > PAGE_SIZE)
428                         page_length = PAGE_SIZE - data_page_offset;
429
430                 if (do_bit17_swizzling) {
431                         ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
432                                                     shmem_page_offset,
433                                                     user_pages[data_page_index],
434                                                     data_page_offset,
435                                                     page_length,
436                                                     1);
437                 } else {
438                         ret = slow_shmem_copy(user_pages[data_page_index],
439                                               data_page_offset,
440                                               obj_priv->pages[shmem_page_index],
441                                               shmem_page_offset,
442                                               page_length);
443                 }
444                 if (ret)
445                         goto fail_put_pages;
446
447                 remain -= page_length;
448                 data_ptr += page_length;
449                 offset += page_length;
450         }
451
452 fail_put_pages:
453         i915_gem_object_put_pages(obj);
454 fail_unlock:
455         mutex_unlock(&dev->struct_mutex);
456 fail_put_user_pages:
457         for (i = 0; i < pinned_pages; i++) {
458                 SetPageDirty(user_pages[i]);
459                 page_cache_release(user_pages[i]);
460         }
461         drm_free_large(user_pages);
462
463         return ret;
464 }
465
466 /**
467  * Reads data from the object referenced by handle.
468  *
469  * On error, the contents of *data are undefined.
470  */
471 int
472 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
473                      struct drm_file *file_priv)
474 {
475         struct drm_i915_gem_pread *args = data;
476         struct drm_gem_object *obj;
477         struct drm_i915_gem_object *obj_priv;
478         int ret;
479
480         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
481         if (obj == NULL)
482                 return -EBADF;
483         obj_priv = obj->driver_private;
484
485         /* Bounds check source.
486          *
487          * XXX: This could use review for overflow issues...
488          */
489         if (args->offset > obj->size || args->size > obj->size ||
490             args->offset + args->size > obj->size) {
491                 drm_gem_object_unreference(obj);
492                 return -EINVAL;
493         }
494
495         if (i915_gem_object_needs_bit17_swizzle(obj)) {
496                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
497         } else {
498                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
499                 if (ret != 0)
500                         ret = i915_gem_shmem_pread_slow(dev, obj, args,
501                                                         file_priv);
502         }
503
504         drm_gem_object_unreference(obj);
505
506         return ret;
507 }
508
509 /* This is the fast write path which cannot handle
510  * page faults in the source data
511  */
512
513 static inline int
514 fast_user_write(struct io_mapping *mapping,
515                 loff_t page_base, int page_offset,
516                 char __user *user_data,
517                 int length)
518 {
519         char *vaddr_atomic;
520         unsigned long unwritten;
521
522         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
523         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
524                                                       user_data, length);
525         io_mapping_unmap_atomic(vaddr_atomic);
526         if (unwritten)
527                 return -EFAULT;
528         return 0;
529 }
530
531 /* Here's the write path which can sleep for
532  * page faults
533  */
534
535 static inline int
536 slow_kernel_write(struct io_mapping *mapping,
537                   loff_t gtt_base, int gtt_offset,
538                   struct page *user_page, int user_offset,
539                   int length)
540 {
541         char *src_vaddr, *dst_vaddr;
542         unsigned long unwritten;
543
544         dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
545         src_vaddr = kmap_atomic(user_page, KM_USER1);
546         unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
547                                                       src_vaddr + user_offset,
548                                                       length);
549         kunmap_atomic(src_vaddr, KM_USER1);
550         io_mapping_unmap_atomic(dst_vaddr);
551         if (unwritten)
552                 return -EFAULT;
553         return 0;
554 }
555
556 static inline int
557 fast_shmem_write(struct page **pages,
558                  loff_t page_base, int page_offset,
559                  char __user *data,
560                  int length)
561 {
562         char __iomem *vaddr;
563         unsigned long unwritten;
564
565         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
566         if (vaddr == NULL)
567                 return -ENOMEM;
568         unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
569         kunmap_atomic(vaddr, KM_USER0);
570
571         if (unwritten)
572                 return -EFAULT;
573         return 0;
574 }
575
576 /**
577  * This is the fast pwrite path, where we copy the data directly from the
578  * user into the GTT, uncached.
579  */
580 static int
581 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
582                          struct drm_i915_gem_pwrite *args,
583                          struct drm_file *file_priv)
584 {
585         struct drm_i915_gem_object *obj_priv = obj->driver_private;
586         drm_i915_private_t *dev_priv = dev->dev_private;
587         ssize_t remain;
588         loff_t offset, page_base;
589         char __user *user_data;
590         int page_offset, page_length;
591         int ret;
592
593         user_data = (char __user *) (uintptr_t) args->data_ptr;
594         remain = args->size;
595         if (!access_ok(VERIFY_READ, user_data, remain))
596                 return -EFAULT;
597
598
599         mutex_lock(&dev->struct_mutex);
600         ret = i915_gem_object_pin(obj, 0);
601         if (ret) {
602                 mutex_unlock(&dev->struct_mutex);
603                 return ret;
604         }
605         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
606         if (ret)
607                 goto fail;
608
609         obj_priv = obj->driver_private;
610         offset = obj_priv->gtt_offset + args->offset;
611
612         while (remain > 0) {
613                 /* Operation in this page
614                  *
615                  * page_base = page offset within aperture
616                  * page_offset = offset within page
617                  * page_length = bytes to copy for this page
618                  */
619                 page_base = (offset & ~(PAGE_SIZE-1));
620                 page_offset = offset & (PAGE_SIZE-1);
621                 page_length = remain;
622                 if ((page_offset + remain) > PAGE_SIZE)
623                         page_length = PAGE_SIZE - page_offset;
624
625                 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
626                                        page_offset, user_data, page_length);
627
628                 /* If we get a fault while copying data, then (presumably) our
629                  * source page isn't available.  Return the error and we'll
630                  * retry in the slow path.
631                  */
632                 if (ret)
633                         goto fail;
634
635                 remain -= page_length;
636                 user_data += page_length;
637                 offset += page_length;
638         }
639
640 fail:
641         i915_gem_object_unpin(obj);
642         mutex_unlock(&dev->struct_mutex);
643
644         return ret;
645 }
646
647 /**
648  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
649  * the memory and maps it using kmap_atomic for copying.
650  *
651  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
652  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
653  */
654 static int
655 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
656                          struct drm_i915_gem_pwrite *args,
657                          struct drm_file *file_priv)
658 {
659         struct drm_i915_gem_object *obj_priv = obj->driver_private;
660         drm_i915_private_t *dev_priv = dev->dev_private;
661         ssize_t remain;
662         loff_t gtt_page_base, offset;
663         loff_t first_data_page, last_data_page, num_pages;
664         loff_t pinned_pages, i;
665         struct page **user_pages;
666         struct mm_struct *mm = current->mm;
667         int gtt_page_offset, data_page_offset, data_page_index, page_length;
668         int ret;
669         uint64_t data_ptr = args->data_ptr;
670
671         remain = args->size;
672
673         /* Pin the user pages containing the data.  We can't fault while
674          * holding the struct mutex, and all of the pwrite implementations
675          * want to hold it while dereferencing the user data.
676          */
677         first_data_page = data_ptr / PAGE_SIZE;
678         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
679         num_pages = last_data_page - first_data_page + 1;
680
681         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
682         if (user_pages == NULL)
683                 return -ENOMEM;
684
685         down_read(&mm->mmap_sem);
686         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
687                                       num_pages, 0, 0, user_pages, NULL);
688         up_read(&mm->mmap_sem);
689         if (pinned_pages < num_pages) {
690                 ret = -EFAULT;
691                 goto out_unpin_pages;
692         }
693
694         mutex_lock(&dev->struct_mutex);
695         ret = i915_gem_object_pin(obj, 0);
696         if (ret)
697                 goto out_unlock;
698
699         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
700         if (ret)
701                 goto out_unpin_object;
702
703         obj_priv = obj->driver_private;
704         offset = obj_priv->gtt_offset + args->offset;
705
706         while (remain > 0) {
707                 /* Operation in this page
708                  *
709                  * gtt_page_base = page offset within aperture
710                  * gtt_page_offset = offset within page in aperture
711                  * data_page_index = page number in get_user_pages return
712                  * data_page_offset = offset with data_page_index page.
713                  * page_length = bytes to copy for this page
714                  */
715                 gtt_page_base = offset & PAGE_MASK;
716                 gtt_page_offset = offset & ~PAGE_MASK;
717                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
718                 data_page_offset = data_ptr & ~PAGE_MASK;
719
720                 page_length = remain;
721                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
722                         page_length = PAGE_SIZE - gtt_page_offset;
723                 if ((data_page_offset + page_length) > PAGE_SIZE)
724                         page_length = PAGE_SIZE - data_page_offset;
725
726                 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
727                                         gtt_page_base, gtt_page_offset,
728                                         user_pages[data_page_index],
729                                         data_page_offset,
730                                         page_length);
731
732                 /* If we get a fault while copying data, then (presumably) our
733                  * source page isn't available.  Return the error and we'll
734                  * retry in the slow path.
735                  */
736                 if (ret)
737                         goto out_unpin_object;
738
739                 remain -= page_length;
740                 offset += page_length;
741                 data_ptr += page_length;
742         }
743
744 out_unpin_object:
745         i915_gem_object_unpin(obj);
746 out_unlock:
747         mutex_unlock(&dev->struct_mutex);
748 out_unpin_pages:
749         for (i = 0; i < pinned_pages; i++)
750                 page_cache_release(user_pages[i]);
751         drm_free_large(user_pages);
752
753         return ret;
754 }
755
756 /**
757  * This is the fast shmem pwrite path, which attempts to directly
758  * copy_from_user into the kmapped pages backing the object.
759  */
760 static int
761 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
762                            struct drm_i915_gem_pwrite *args,
763                            struct drm_file *file_priv)
764 {
765         struct drm_i915_gem_object *obj_priv = obj->driver_private;
766         ssize_t remain;
767         loff_t offset, page_base;
768         char __user *user_data;
769         int page_offset, page_length;
770         int ret;
771
772         user_data = (char __user *) (uintptr_t) args->data_ptr;
773         remain = args->size;
774
775         mutex_lock(&dev->struct_mutex);
776
777         ret = i915_gem_object_get_pages(obj, 0);
778         if (ret != 0)
779                 goto fail_unlock;
780
781         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
782         if (ret != 0)
783                 goto fail_put_pages;
784
785         obj_priv = obj->driver_private;
786         offset = args->offset;
787         obj_priv->dirty = 1;
788
789         while (remain > 0) {
790                 /* Operation in this page
791                  *
792                  * page_base = page offset within aperture
793                  * page_offset = offset within page
794                  * page_length = bytes to copy for this page
795                  */
796                 page_base = (offset & ~(PAGE_SIZE-1));
797                 page_offset = offset & (PAGE_SIZE-1);
798                 page_length = remain;
799                 if ((page_offset + remain) > PAGE_SIZE)
800                         page_length = PAGE_SIZE - page_offset;
801
802                 ret = fast_shmem_write(obj_priv->pages,
803                                        page_base, page_offset,
804                                        user_data, page_length);
805                 if (ret)
806                         goto fail_put_pages;
807
808                 remain -= page_length;
809                 user_data += page_length;
810                 offset += page_length;
811         }
812
813 fail_put_pages:
814         i915_gem_object_put_pages(obj);
815 fail_unlock:
816         mutex_unlock(&dev->struct_mutex);
817
818         return ret;
819 }
820
821 /**
822  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
823  * the memory and maps it using kmap_atomic for copying.
824  *
825  * This avoids taking mmap_sem for faulting on the user's address while the
826  * struct_mutex is held.
827  */
828 static int
829 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
830                            struct drm_i915_gem_pwrite *args,
831                            struct drm_file *file_priv)
832 {
833         struct drm_i915_gem_object *obj_priv = obj->driver_private;
834         struct mm_struct *mm = current->mm;
835         struct page **user_pages;
836         ssize_t remain;
837         loff_t offset, pinned_pages, i;
838         loff_t first_data_page, last_data_page, num_pages;
839         int shmem_page_index, shmem_page_offset;
840         int data_page_index,  data_page_offset;
841         int page_length;
842         int ret;
843         uint64_t data_ptr = args->data_ptr;
844         int do_bit17_swizzling;
845
846         remain = args->size;
847
848         /* Pin the user pages containing the data.  We can't fault while
849          * holding the struct mutex, and all of the pwrite implementations
850          * want to hold it while dereferencing the user data.
851          */
852         first_data_page = data_ptr / PAGE_SIZE;
853         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
854         num_pages = last_data_page - first_data_page + 1;
855
856         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
857         if (user_pages == NULL)
858                 return -ENOMEM;
859
860         down_read(&mm->mmap_sem);
861         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
862                                       num_pages, 0, 0, user_pages, NULL);
863         up_read(&mm->mmap_sem);
864         if (pinned_pages < num_pages) {
865                 ret = -EFAULT;
866                 goto fail_put_user_pages;
867         }
868
869         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
870
871         mutex_lock(&dev->struct_mutex);
872
873         ret = i915_gem_object_get_pages_or_evict(obj);
874         if (ret)
875                 goto fail_unlock;
876
877         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
878         if (ret != 0)
879                 goto fail_put_pages;
880
881         obj_priv = obj->driver_private;
882         offset = args->offset;
883         obj_priv->dirty = 1;
884
885         while (remain > 0) {
886                 /* Operation in this page
887                  *
888                  * shmem_page_index = page number within shmem file
889                  * shmem_page_offset = offset within page in shmem file
890                  * data_page_index = page number in get_user_pages return
891                  * data_page_offset = offset with data_page_index page.
892                  * page_length = bytes to copy for this page
893                  */
894                 shmem_page_index = offset / PAGE_SIZE;
895                 shmem_page_offset = offset & ~PAGE_MASK;
896                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
897                 data_page_offset = data_ptr & ~PAGE_MASK;
898
899                 page_length = remain;
900                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
901                         page_length = PAGE_SIZE - shmem_page_offset;
902                 if ((data_page_offset + page_length) > PAGE_SIZE)
903                         page_length = PAGE_SIZE - data_page_offset;
904
905                 if (do_bit17_swizzling) {
906                         ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
907                                                     shmem_page_offset,
908                                                     user_pages[data_page_index],
909                                                     data_page_offset,
910                                                     page_length,
911                                                     0);
912                 } else {
913                         ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
914                                               shmem_page_offset,
915                                               user_pages[data_page_index],
916                                               data_page_offset,
917                                               page_length);
918                 }
919                 if (ret)
920                         goto fail_put_pages;
921
922                 remain -= page_length;
923                 data_ptr += page_length;
924                 offset += page_length;
925         }
926
927 fail_put_pages:
928         i915_gem_object_put_pages(obj);
929 fail_unlock:
930         mutex_unlock(&dev->struct_mutex);
931 fail_put_user_pages:
932         for (i = 0; i < pinned_pages; i++)
933                 page_cache_release(user_pages[i]);
934         drm_free_large(user_pages);
935
936         return ret;
937 }
938
939 /**
940  * Writes data to the object referenced by handle.
941  *
942  * On error, the contents of the buffer that were to be modified are undefined.
943  */
944 int
945 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
946                       struct drm_file *file_priv)
947 {
948         struct drm_i915_gem_pwrite *args = data;
949         struct drm_gem_object *obj;
950         struct drm_i915_gem_object *obj_priv;
951         int ret = 0;
952
953         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
954         if (obj == NULL)
955                 return -EBADF;
956         obj_priv = obj->driver_private;
957
958         /* Bounds check destination.
959          *
960          * XXX: This could use review for overflow issues...
961          */
962         if (args->offset > obj->size || args->size > obj->size ||
963             args->offset + args->size > obj->size) {
964                 drm_gem_object_unreference(obj);
965                 return -EINVAL;
966         }
967
968         /* We can only do the GTT pwrite on untiled buffers, as otherwise
969          * it would end up going through the fenced access, and we'll get
970          * different detiling behavior between reading and writing.
971          * pread/pwrite currently are reading and writing from the CPU
972          * perspective, requiring manual detiling by the client.
973          */
974         if (obj_priv->phys_obj)
975                 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
976         else if (obj_priv->tiling_mode == I915_TILING_NONE &&
977                  dev->gtt_total != 0) {
978                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
979                 if (ret == -EFAULT) {
980                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
981                                                        file_priv);
982                 }
983         } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
984                 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
985         } else {
986                 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
987                 if (ret == -EFAULT) {
988                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
989                                                          file_priv);
990                 }
991         }
992
993 #if WATCH_PWRITE
994         if (ret)
995                 DRM_INFO("pwrite failed %d\n", ret);
996 #endif
997
998         drm_gem_object_unreference(obj);
999
1000         return ret;
1001 }
1002
1003 /**
1004  * Called when user space prepares to use an object with the CPU, either
1005  * through the mmap ioctl's mapping or a GTT mapping.
1006  */
1007 int
1008 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1009                           struct drm_file *file_priv)
1010 {
1011         struct drm_i915_private *dev_priv = dev->dev_private;
1012         struct drm_i915_gem_set_domain *args = data;
1013         struct drm_gem_object *obj;
1014         struct drm_i915_gem_object *obj_priv;
1015         uint32_t read_domains = args->read_domains;
1016         uint32_t write_domain = args->write_domain;
1017         int ret;
1018
1019         if (!(dev->driver->driver_features & DRIVER_GEM))
1020                 return -ENODEV;
1021
1022         /* Only handle setting domains to types used by the CPU. */
1023         if (write_domain & I915_GEM_GPU_DOMAINS)
1024                 return -EINVAL;
1025
1026         if (read_domains & I915_GEM_GPU_DOMAINS)
1027                 return -EINVAL;
1028
1029         /* Having something in the write domain implies it's in the read
1030          * domain, and only that read domain.  Enforce that in the request.
1031          */
1032         if (write_domain != 0 && read_domains != write_domain)
1033                 return -EINVAL;
1034
1035         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1036         if (obj == NULL)
1037                 return -EBADF;
1038         obj_priv = obj->driver_private;
1039
1040         mutex_lock(&dev->struct_mutex);
1041
1042         intel_mark_busy(dev, obj);
1043
1044 #if WATCH_BUF
1045         DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1046                  obj, obj->size, read_domains, write_domain);
1047 #endif
1048         if (read_domains & I915_GEM_DOMAIN_GTT) {
1049                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1050
1051                 /* Update the LRU on the fence for the CPU access that's
1052                  * about to occur.
1053                  */
1054                 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1055                         list_move_tail(&obj_priv->fence_list,
1056                                        &dev_priv->mm.fence_list);
1057                 }
1058
1059                 /* Silently promote "you're not bound, there was nothing to do"
1060                  * to success, since the client was just asking us to
1061                  * make sure everything was done.
1062                  */
1063                 if (ret == -EINVAL)
1064                         ret = 0;
1065         } else {
1066                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1067         }
1068
1069         drm_gem_object_unreference(obj);
1070         mutex_unlock(&dev->struct_mutex);
1071         return ret;
1072 }
1073
1074 /**
1075  * Called when user space has done writes to this buffer
1076  */
1077 int
1078 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1079                       struct drm_file *file_priv)
1080 {
1081         struct drm_i915_gem_sw_finish *args = data;
1082         struct drm_gem_object *obj;
1083         struct drm_i915_gem_object *obj_priv;
1084         int ret = 0;
1085
1086         if (!(dev->driver->driver_features & DRIVER_GEM))
1087                 return -ENODEV;
1088
1089         mutex_lock(&dev->struct_mutex);
1090         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1091         if (obj == NULL) {
1092                 mutex_unlock(&dev->struct_mutex);
1093                 return -EBADF;
1094         }
1095
1096 #if WATCH_BUF
1097         DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1098                  __func__, args->handle, obj, obj->size);
1099 #endif
1100         obj_priv = obj->driver_private;
1101
1102         /* Pinned buffers may be scanout, so flush the cache */
1103         if (obj_priv->pin_count)
1104                 i915_gem_object_flush_cpu_write_domain(obj);
1105
1106         drm_gem_object_unreference(obj);
1107         mutex_unlock(&dev->struct_mutex);
1108         return ret;
1109 }
1110
1111 /**
1112  * Maps the contents of an object, returning the address it is mapped
1113  * into.
1114  *
1115  * While the mapping holds a reference on the contents of the object, it doesn't
1116  * imply a ref on the object itself.
1117  */
1118 int
1119 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1120                    struct drm_file *file_priv)
1121 {
1122         struct drm_i915_gem_mmap *args = data;
1123         struct drm_gem_object *obj;
1124         loff_t offset;
1125         unsigned long addr;
1126
1127         if (!(dev->driver->driver_features & DRIVER_GEM))
1128                 return -ENODEV;
1129
1130         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1131         if (obj == NULL)
1132                 return -EBADF;
1133
1134         offset = args->offset;
1135
1136         down_write(&current->mm->mmap_sem);
1137         addr = do_mmap(obj->filp, 0, args->size,
1138                        PROT_READ | PROT_WRITE, MAP_SHARED,
1139                        args->offset);
1140         up_write(&current->mm->mmap_sem);
1141         mutex_lock(&dev->struct_mutex);
1142         drm_gem_object_unreference(obj);
1143         mutex_unlock(&dev->struct_mutex);
1144         if (IS_ERR((void *)addr))
1145                 return addr;
1146
1147         args->addr_ptr = (uint64_t) addr;
1148
1149         return 0;
1150 }
1151
1152 /**
1153  * i915_gem_fault - fault a page into the GTT
1154  * vma: VMA in question
1155  * vmf: fault info
1156  *
1157  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1158  * from userspace.  The fault handler takes care of binding the object to
1159  * the GTT (if needed), allocating and programming a fence register (again,
1160  * only if needed based on whether the old reg is still valid or the object
1161  * is tiled) and inserting a new PTE into the faulting process.
1162  *
1163  * Note that the faulting process may involve evicting existing objects
1164  * from the GTT and/or fence registers to make room.  So performance may
1165  * suffer if the GTT working set is large or there are few fence registers
1166  * left.
1167  */
1168 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1169 {
1170         struct drm_gem_object *obj = vma->vm_private_data;
1171         struct drm_device *dev = obj->dev;
1172         struct drm_i915_private *dev_priv = dev->dev_private;
1173         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1174         pgoff_t page_offset;
1175         unsigned long pfn;
1176         int ret = 0;
1177         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1178
1179         /* We don't use vmf->pgoff since that has the fake offset */
1180         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1181                 PAGE_SHIFT;
1182
1183         /* Now bind it into the GTT if needed */
1184         mutex_lock(&dev->struct_mutex);
1185         if (!obj_priv->gtt_space) {
1186                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1187                 if (ret)
1188                         goto unlock;
1189
1190                 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1191
1192                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1193                 if (ret)
1194                         goto unlock;
1195         }
1196
1197         /* Need a new fence register? */
1198         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1199                 ret = i915_gem_object_get_fence_reg(obj);
1200                 if (ret)
1201                         goto unlock;
1202         }
1203
1204         pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1205                 page_offset;
1206
1207         /* Finally, remap it using the new GTT offset */
1208         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1209 unlock:
1210         mutex_unlock(&dev->struct_mutex);
1211
1212         switch (ret) {
1213         case 0:
1214         case -ERESTARTSYS:
1215                 return VM_FAULT_NOPAGE;
1216         case -ENOMEM:
1217         case -EAGAIN:
1218                 return VM_FAULT_OOM;
1219         default:
1220                 return VM_FAULT_SIGBUS;
1221         }
1222 }
1223
1224 /**
1225  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1226  * @obj: obj in question
1227  *
1228  * GEM memory mapping works by handing back to userspace a fake mmap offset
1229  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1230  * up the object based on the offset and sets up the various memory mapping
1231  * structures.
1232  *
1233  * This routine allocates and attaches a fake offset for @obj.
1234  */
1235 static int
1236 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1237 {
1238         struct drm_device *dev = obj->dev;
1239         struct drm_gem_mm *mm = dev->mm_private;
1240         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1241         struct drm_map_list *list;
1242         struct drm_local_map *map;
1243         int ret = 0;
1244
1245         /* Set the object up for mmap'ing */
1246         list = &obj->map_list;
1247         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1248         if (!list->map)
1249                 return -ENOMEM;
1250
1251         map = list->map;
1252         map->type = _DRM_GEM;
1253         map->size = obj->size;
1254         map->handle = obj;
1255
1256         /* Get a DRM GEM mmap offset allocated... */
1257         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1258                                                     obj->size / PAGE_SIZE, 0, 0);
1259         if (!list->file_offset_node) {
1260                 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1261                 ret = -ENOMEM;
1262                 goto out_free_list;
1263         }
1264
1265         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1266                                                   obj->size / PAGE_SIZE, 0);
1267         if (!list->file_offset_node) {
1268                 ret = -ENOMEM;
1269                 goto out_free_list;
1270         }
1271
1272         list->hash.key = list->file_offset_node->start;
1273         if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1274                 DRM_ERROR("failed to add to map hash\n");
1275                 ret = -ENOMEM;
1276                 goto out_free_mm;
1277         }
1278
1279         /* By now we should be all set, any drm_mmap request on the offset
1280          * below will get to our mmap & fault handler */
1281         obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1282
1283         return 0;
1284
1285 out_free_mm:
1286         drm_mm_put_block(list->file_offset_node);
1287 out_free_list:
1288         kfree(list->map);
1289
1290         return ret;
1291 }
1292
1293 /**
1294  * i915_gem_release_mmap - remove physical page mappings
1295  * @obj: obj in question
1296  *
1297  * Preserve the reservation of the mmapping with the DRM core code, but
1298  * relinquish ownership of the pages back to the system.
1299  *
1300  * It is vital that we remove the page mapping if we have mapped a tiled
1301  * object through the GTT and then lose the fence register due to
1302  * resource pressure. Similarly if the object has been moved out of the
1303  * aperture, than pages mapped into userspace must be revoked. Removing the
1304  * mapping will then trigger a page fault on the next user access, allowing
1305  * fixup by i915_gem_fault().
1306  */
1307 void
1308 i915_gem_release_mmap(struct drm_gem_object *obj)
1309 {
1310         struct drm_device *dev = obj->dev;
1311         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1312
1313         if (dev->dev_mapping)
1314                 unmap_mapping_range(dev->dev_mapping,
1315                                     obj_priv->mmap_offset, obj->size, 1);
1316 }
1317
1318 static void
1319 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1320 {
1321         struct drm_device *dev = obj->dev;
1322         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1323         struct drm_gem_mm *mm = dev->mm_private;
1324         struct drm_map_list *list;
1325
1326         list = &obj->map_list;
1327         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1328
1329         if (list->file_offset_node) {
1330                 drm_mm_put_block(list->file_offset_node);
1331                 list->file_offset_node = NULL;
1332         }
1333
1334         if (list->map) {
1335                 kfree(list->map);
1336                 list->map = NULL;
1337         }
1338
1339         obj_priv->mmap_offset = 0;
1340 }
1341
1342 /**
1343  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1344  * @obj: object to check
1345  *
1346  * Return the required GTT alignment for an object, taking into account
1347  * potential fence register mapping if needed.
1348  */
1349 static uint32_t
1350 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1351 {
1352         struct drm_device *dev = obj->dev;
1353         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1354         int start, i;
1355
1356         /*
1357          * Minimum alignment is 4k (GTT page size), but might be greater
1358          * if a fence register is needed for the object.
1359          */
1360         if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1361                 return 4096;
1362
1363         /*
1364          * Previous chips need to be aligned to the size of the smallest
1365          * fence register that can contain the object.
1366          */
1367         if (IS_I9XX(dev))
1368                 start = 1024*1024;
1369         else
1370                 start = 512*1024;
1371
1372         for (i = start; i < obj->size; i <<= 1)
1373                 ;
1374
1375         return i;
1376 }
1377
1378 /**
1379  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1380  * @dev: DRM device
1381  * @data: GTT mapping ioctl data
1382  * @file_priv: GEM object info
1383  *
1384  * Simply returns the fake offset to userspace so it can mmap it.
1385  * The mmap call will end up in drm_gem_mmap(), which will set things
1386  * up so we can get faults in the handler above.
1387  *
1388  * The fault handler will take care of binding the object into the GTT
1389  * (since it may have been evicted to make room for something), allocating
1390  * a fence register, and mapping the appropriate aperture address into
1391  * userspace.
1392  */
1393 int
1394 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1395                         struct drm_file *file_priv)
1396 {
1397         struct drm_i915_gem_mmap_gtt *args = data;
1398         struct drm_i915_private *dev_priv = dev->dev_private;
1399         struct drm_gem_object *obj;
1400         struct drm_i915_gem_object *obj_priv;
1401         int ret;
1402
1403         if (!(dev->driver->driver_features & DRIVER_GEM))
1404                 return -ENODEV;
1405
1406         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1407         if (obj == NULL)
1408                 return -EBADF;
1409
1410         mutex_lock(&dev->struct_mutex);
1411
1412         obj_priv = obj->driver_private;
1413
1414         if (obj_priv->madv != I915_MADV_WILLNEED) {
1415                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1416                 drm_gem_object_unreference(obj);
1417                 mutex_unlock(&dev->struct_mutex);
1418                 return -EINVAL;
1419         }
1420
1421
1422         if (!obj_priv->mmap_offset) {
1423                 ret = i915_gem_create_mmap_offset(obj);
1424                 if (ret) {
1425                         drm_gem_object_unreference(obj);
1426                         mutex_unlock(&dev->struct_mutex);
1427                         return ret;
1428                 }
1429         }
1430
1431         args->offset = obj_priv->mmap_offset;
1432
1433         /*
1434          * Pull it into the GTT so that we have a page list (makes the
1435          * initial fault faster and any subsequent flushing possible).
1436          */
1437         if (!obj_priv->agp_mem) {
1438                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1439                 if (ret) {
1440                         drm_gem_object_unreference(obj);
1441                         mutex_unlock(&dev->struct_mutex);
1442                         return ret;
1443                 }
1444                 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1445         }
1446
1447         drm_gem_object_unreference(obj);
1448         mutex_unlock(&dev->struct_mutex);
1449
1450         return 0;
1451 }
1452
1453 void
1454 i915_gem_object_put_pages(struct drm_gem_object *obj)
1455 {
1456         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1457         int page_count = obj->size / PAGE_SIZE;
1458         int i;
1459
1460         BUG_ON(obj_priv->pages_refcount == 0);
1461         BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1462
1463         if (--obj_priv->pages_refcount != 0)
1464                 return;
1465
1466         if (obj_priv->tiling_mode != I915_TILING_NONE)
1467                 i915_gem_object_save_bit_17_swizzle(obj);
1468
1469         if (obj_priv->madv == I915_MADV_DONTNEED)
1470                 obj_priv->dirty = 0;
1471
1472         for (i = 0; i < page_count; i++) {
1473                 if (obj_priv->pages[i] == NULL)
1474                         break;
1475
1476                 if (obj_priv->dirty)
1477                         set_page_dirty(obj_priv->pages[i]);
1478
1479                 if (obj_priv->madv == I915_MADV_WILLNEED)
1480                         mark_page_accessed(obj_priv->pages[i]);
1481
1482                 page_cache_release(obj_priv->pages[i]);
1483         }
1484         obj_priv->dirty = 0;
1485
1486         drm_free_large(obj_priv->pages);
1487         obj_priv->pages = NULL;
1488 }
1489
1490 static void
1491 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1492 {
1493         struct drm_device *dev = obj->dev;
1494         drm_i915_private_t *dev_priv = dev->dev_private;
1495         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1496
1497         /* Add a reference if we're newly entering the active list. */
1498         if (!obj_priv->active) {
1499                 drm_gem_object_reference(obj);
1500                 obj_priv->active = 1;
1501         }
1502         /* Move from whatever list we were on to the tail of execution. */
1503         spin_lock(&dev_priv->mm.active_list_lock);
1504         list_move_tail(&obj_priv->list,
1505                        &dev_priv->mm.active_list);
1506         spin_unlock(&dev_priv->mm.active_list_lock);
1507         obj_priv->last_rendering_seqno = seqno;
1508 }
1509
1510 static void
1511 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1512 {
1513         struct drm_device *dev = obj->dev;
1514         drm_i915_private_t *dev_priv = dev->dev_private;
1515         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1516
1517         BUG_ON(!obj_priv->active);
1518         list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1519         obj_priv->last_rendering_seqno = 0;
1520 }
1521
1522 /* Immediately discard the backing storage */
1523 static void
1524 i915_gem_object_truncate(struct drm_gem_object *obj)
1525 {
1526         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1527         struct inode *inode;
1528
1529         inode = obj->filp->f_path.dentry->d_inode;
1530         if (inode->i_op->truncate)
1531                 inode->i_op->truncate (inode);
1532
1533         obj_priv->madv = __I915_MADV_PURGED;
1534 }
1535
1536 static inline int
1537 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1538 {
1539         return obj_priv->madv == I915_MADV_DONTNEED;
1540 }
1541
1542 static void
1543 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1544 {
1545         struct drm_device *dev = obj->dev;
1546         drm_i915_private_t *dev_priv = dev->dev_private;
1547         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1548
1549         i915_verify_inactive(dev, __FILE__, __LINE__);
1550         if (obj_priv->pin_count != 0)
1551                 list_del_init(&obj_priv->list);
1552         else
1553                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1554
1555         BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1556
1557         obj_priv->last_rendering_seqno = 0;
1558         if (obj_priv->active) {
1559                 obj_priv->active = 0;
1560                 drm_gem_object_unreference(obj);
1561         }
1562         i915_verify_inactive(dev, __FILE__, __LINE__);
1563 }
1564
1565 /**
1566  * Creates a new sequence number, emitting a write of it to the status page
1567  * plus an interrupt, which will trigger i915_user_interrupt_handler.
1568  *
1569  * Must be called with struct_lock held.
1570  *
1571  * Returned sequence numbers are nonzero on success.
1572  */
1573 uint32_t
1574 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1575                  uint32_t flush_domains)
1576 {
1577         drm_i915_private_t *dev_priv = dev->dev_private;
1578         struct drm_i915_file_private *i915_file_priv = NULL;
1579         struct drm_i915_gem_request *request;
1580         uint32_t seqno;
1581         int was_empty;
1582         RING_LOCALS;
1583
1584         if (file_priv != NULL)
1585                 i915_file_priv = file_priv->driver_priv;
1586
1587         request = kzalloc(sizeof(*request), GFP_KERNEL);
1588         if (request == NULL)
1589                 return 0;
1590
1591         /* Grab the seqno we're going to make this request be, and bump the
1592          * next (skipping 0 so it can be the reserved no-seqno value).
1593          */
1594         seqno = dev_priv->mm.next_gem_seqno;
1595         dev_priv->mm.next_gem_seqno++;
1596         if (dev_priv->mm.next_gem_seqno == 0)
1597                 dev_priv->mm.next_gem_seqno++;
1598
1599         BEGIN_LP_RING(4);
1600         OUT_RING(MI_STORE_DWORD_INDEX);
1601         OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1602         OUT_RING(seqno);
1603
1604         OUT_RING(MI_USER_INTERRUPT);
1605         ADVANCE_LP_RING();
1606
1607         DRM_DEBUG_DRIVER("%d\n", seqno);
1608
1609         request->seqno = seqno;
1610         request->emitted_jiffies = jiffies;
1611         was_empty = list_empty(&dev_priv->mm.request_list);
1612         list_add_tail(&request->list, &dev_priv->mm.request_list);
1613         if (i915_file_priv) {
1614                 list_add_tail(&request->client_list,
1615                               &i915_file_priv->mm.request_list);
1616         } else {
1617                 INIT_LIST_HEAD(&request->client_list);
1618         }
1619
1620         /* Associate any objects on the flushing list matching the write
1621          * domain we're flushing with our flush.
1622          */
1623         if (flush_domains != 0) {
1624                 struct drm_i915_gem_object *obj_priv, *next;
1625
1626                 list_for_each_entry_safe(obj_priv, next,
1627                                          &dev_priv->mm.gpu_write_list,
1628                                          gpu_write_list) {
1629                         struct drm_gem_object *obj = obj_priv->obj;
1630
1631                         if ((obj->write_domain & flush_domains) ==
1632                             obj->write_domain) {
1633                                 uint32_t old_write_domain = obj->write_domain;
1634
1635                                 obj->write_domain = 0;
1636                                 list_del_init(&obj_priv->gpu_write_list);
1637                                 i915_gem_object_move_to_active(obj, seqno);
1638
1639                                 trace_i915_gem_object_change_domain(obj,
1640                                                                     obj->read_domains,
1641                                                                     old_write_domain);
1642                         }
1643                 }
1644
1645         }
1646
1647         if (!dev_priv->mm.suspended) {
1648                 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1649                 if (was_empty)
1650                         queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1651         }
1652         return seqno;
1653 }
1654
1655 /**
1656  * Command execution barrier
1657  *
1658  * Ensures that all commands in the ring are finished
1659  * before signalling the CPU
1660  */
1661 static uint32_t
1662 i915_retire_commands(struct drm_device *dev)
1663 {
1664         drm_i915_private_t *dev_priv = dev->dev_private;
1665         uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1666         uint32_t flush_domains = 0;
1667         RING_LOCALS;
1668
1669         /* The sampler always gets flushed on i965 (sigh) */
1670         if (IS_I965G(dev))
1671                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1672         BEGIN_LP_RING(2);
1673         OUT_RING(cmd);
1674         OUT_RING(0); /* noop */
1675         ADVANCE_LP_RING();
1676         return flush_domains;
1677 }
1678
1679 /**
1680  * Moves buffers associated only with the given active seqno from the active
1681  * to inactive list, potentially freeing them.
1682  */
1683 static void
1684 i915_gem_retire_request(struct drm_device *dev,
1685                         struct drm_i915_gem_request *request)
1686 {
1687         drm_i915_private_t *dev_priv = dev->dev_private;
1688
1689         trace_i915_gem_request_retire(dev, request->seqno);
1690
1691         /* Move any buffers on the active list that are no longer referenced
1692          * by the ringbuffer to the flushing/inactive lists as appropriate.
1693          */
1694         spin_lock(&dev_priv->mm.active_list_lock);
1695         while (!list_empty(&dev_priv->mm.active_list)) {
1696                 struct drm_gem_object *obj;
1697                 struct drm_i915_gem_object *obj_priv;
1698
1699                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1700                                             struct drm_i915_gem_object,
1701                                             list);
1702                 obj = obj_priv->obj;
1703
1704                 /* If the seqno being retired doesn't match the oldest in the
1705                  * list, then the oldest in the list must still be newer than
1706                  * this seqno.
1707                  */
1708                 if (obj_priv->last_rendering_seqno != request->seqno)
1709                         goto out;
1710
1711 #if WATCH_LRU
1712                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1713                          __func__, request->seqno, obj);
1714 #endif
1715
1716                 if (obj->write_domain != 0)
1717                         i915_gem_object_move_to_flushing(obj);
1718                 else {
1719                         /* Take a reference on the object so it won't be
1720                          * freed while the spinlock is held.  The list
1721                          * protection for this spinlock is safe when breaking
1722                          * the lock like this since the next thing we do
1723                          * is just get the head of the list again.
1724                          */
1725                         drm_gem_object_reference(obj);
1726                         i915_gem_object_move_to_inactive(obj);
1727                         spin_unlock(&dev_priv->mm.active_list_lock);
1728                         drm_gem_object_unreference(obj);
1729                         spin_lock(&dev_priv->mm.active_list_lock);
1730                 }
1731         }
1732 out:
1733         spin_unlock(&dev_priv->mm.active_list_lock);
1734 }
1735
1736 /**
1737  * Returns true if seq1 is later than seq2.
1738  */
1739 bool
1740 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1741 {
1742         return (int32_t)(seq1 - seq2) >= 0;
1743 }
1744
1745 uint32_t
1746 i915_get_gem_seqno(struct drm_device *dev)
1747 {
1748         drm_i915_private_t *dev_priv = dev->dev_private;
1749
1750         return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1751 }
1752
1753 /**
1754  * This function clears the request list as sequence numbers are passed.
1755  */
1756 void
1757 i915_gem_retire_requests(struct drm_device *dev)
1758 {
1759         drm_i915_private_t *dev_priv = dev->dev_private;
1760         uint32_t seqno;
1761
1762         if (!dev_priv->hw_status_page || list_empty(&dev_priv->mm.request_list))
1763                 return;
1764
1765         seqno = i915_get_gem_seqno(dev);
1766
1767         while (!list_empty(&dev_priv->mm.request_list)) {
1768                 struct drm_i915_gem_request *request;
1769                 uint32_t retiring_seqno;
1770
1771                 request = list_first_entry(&dev_priv->mm.request_list,
1772                                            struct drm_i915_gem_request,
1773                                            list);
1774                 retiring_seqno = request->seqno;
1775
1776                 if (i915_seqno_passed(seqno, retiring_seqno) ||
1777                     atomic_read(&dev_priv->mm.wedged)) {
1778                         i915_gem_retire_request(dev, request);
1779
1780                         list_del(&request->list);
1781                         list_del(&request->client_list);
1782                         kfree(request);
1783                 } else
1784                         break;
1785         }
1786
1787         if (unlikely (dev_priv->trace_irq_seqno &&
1788                       i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1789                 i915_user_irq_put(dev);
1790                 dev_priv->trace_irq_seqno = 0;
1791         }
1792 }
1793
1794 void
1795 i915_gem_retire_work_handler(struct work_struct *work)
1796 {
1797         drm_i915_private_t *dev_priv;
1798         struct drm_device *dev;
1799
1800         dev_priv = container_of(work, drm_i915_private_t,
1801                                 mm.retire_work.work);
1802         dev = dev_priv->dev;
1803
1804         mutex_lock(&dev->struct_mutex);
1805         i915_gem_retire_requests(dev);
1806         if (!dev_priv->mm.suspended &&
1807             !list_empty(&dev_priv->mm.request_list))
1808                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1809         mutex_unlock(&dev->struct_mutex);
1810 }
1811
1812 int
1813 i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
1814 {
1815         drm_i915_private_t *dev_priv = dev->dev_private;
1816         u32 ier;
1817         int ret = 0;
1818
1819         BUG_ON(seqno == 0);
1820
1821         if (atomic_read(&dev_priv->mm.wedged))
1822                 return -EIO;
1823
1824         if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1825                 if (IS_IRONLAKE(dev))
1826                         ier = I915_READ(DEIER) | I915_READ(GTIER);
1827                 else
1828                         ier = I915_READ(IER);
1829                 if (!ier) {
1830                         DRM_ERROR("something (likely vbetool) disabled "
1831                                   "interrupts, re-enabling\n");
1832                         i915_driver_irq_preinstall(dev);
1833                         i915_driver_irq_postinstall(dev);
1834                 }
1835
1836                 trace_i915_gem_request_wait_begin(dev, seqno);
1837
1838                 dev_priv->mm.waiting_gem_seqno = seqno;
1839                 i915_user_irq_get(dev);
1840                 if (interruptible)
1841                         ret = wait_event_interruptible(dev_priv->irq_queue,
1842                                 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1843                                 atomic_read(&dev_priv->mm.wedged));
1844                 else
1845                         wait_event(dev_priv->irq_queue,
1846                                 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1847                                 atomic_read(&dev_priv->mm.wedged));
1848
1849                 i915_user_irq_put(dev);
1850                 dev_priv->mm.waiting_gem_seqno = 0;
1851
1852                 trace_i915_gem_request_wait_end(dev, seqno);
1853         }
1854         if (atomic_read(&dev_priv->mm.wedged))
1855                 ret = -EIO;
1856
1857         if (ret && ret != -ERESTARTSYS)
1858                 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1859                           __func__, ret, seqno, i915_get_gem_seqno(dev));
1860
1861         /* Directly dispatch request retiring.  While we have the work queue
1862          * to handle this, the waiter on a request often wants an associated
1863          * buffer to have made it to the inactive list, and we would need
1864          * a separate wait queue to handle that.
1865          */
1866         if (ret == 0)
1867                 i915_gem_retire_requests(dev);
1868
1869         return ret;
1870 }
1871
1872 /**
1873  * Waits for a sequence number to be signaled, and cleans up the
1874  * request and object lists appropriately for that event.
1875  */
1876 static int
1877 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1878 {
1879         return i915_do_wait_request(dev, seqno, 1);
1880 }
1881
1882 static void
1883 i915_gem_flush(struct drm_device *dev,
1884                uint32_t invalidate_domains,
1885                uint32_t flush_domains)
1886 {
1887         drm_i915_private_t *dev_priv = dev->dev_private;
1888         uint32_t cmd;
1889         RING_LOCALS;
1890
1891 #if WATCH_EXEC
1892         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1893                   invalidate_domains, flush_domains);
1894 #endif
1895         trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1896                                      invalidate_domains, flush_domains);
1897
1898         if (flush_domains & I915_GEM_DOMAIN_CPU)
1899                 drm_agp_chipset_flush(dev);
1900
1901         if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1902                 /*
1903                  * read/write caches:
1904                  *
1905                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1906                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
1907                  * also flushed at 2d versus 3d pipeline switches.
1908                  *
1909                  * read-only caches:
1910                  *
1911                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1912                  * MI_READ_FLUSH is set, and is always flushed on 965.
1913                  *
1914                  * I915_GEM_DOMAIN_COMMAND may not exist?
1915                  *
1916                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1917                  * invalidated when MI_EXE_FLUSH is set.
1918                  *
1919                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1920                  * invalidated with every MI_FLUSH.
1921                  *
1922                  * TLBs:
1923                  *
1924                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1925                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1926                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1927                  * are flushed at any MI_FLUSH.
1928                  */
1929
1930                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1931                 if ((invalidate_domains|flush_domains) &
1932                     I915_GEM_DOMAIN_RENDER)
1933                         cmd &= ~MI_NO_WRITE_FLUSH;
1934                 if (!IS_I965G(dev)) {
1935                         /*
1936                          * On the 965, the sampler cache always gets flushed
1937                          * and this bit is reserved.
1938                          */
1939                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1940                                 cmd |= MI_READ_FLUSH;
1941                 }
1942                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1943                         cmd |= MI_EXE_FLUSH;
1944
1945 #if WATCH_EXEC
1946                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1947 #endif
1948                 BEGIN_LP_RING(2);
1949                 OUT_RING(cmd);
1950                 OUT_RING(MI_NOOP);
1951                 ADVANCE_LP_RING();
1952         }
1953 }
1954
1955 /**
1956  * Ensures that all rendering to the object has completed and the object is
1957  * safe to unbind from the GTT or access from the CPU.
1958  */
1959 static int
1960 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1961 {
1962         struct drm_device *dev = obj->dev;
1963         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1964         int ret;
1965
1966         /* This function only exists to support waiting for existing rendering,
1967          * not for emitting required flushes.
1968          */
1969         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1970
1971         /* If there is rendering queued on the buffer being evicted, wait for
1972          * it.
1973          */
1974         if (obj_priv->active) {
1975 #if WATCH_BUF
1976                 DRM_INFO("%s: object %p wait for seqno %08x\n",
1977                           __func__, obj, obj_priv->last_rendering_seqno);
1978 #endif
1979                 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1980                 if (ret != 0)
1981                         return ret;
1982         }
1983
1984         return 0;
1985 }
1986
1987 /**
1988  * Unbinds an object from the GTT aperture.
1989  */
1990 int
1991 i915_gem_object_unbind(struct drm_gem_object *obj)
1992 {
1993         struct drm_device *dev = obj->dev;
1994         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1995         int ret = 0;
1996
1997 #if WATCH_BUF
1998         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1999         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
2000 #endif
2001         if (obj_priv->gtt_space == NULL)
2002                 return 0;
2003
2004         if (obj_priv->pin_count != 0) {
2005                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2006                 return -EINVAL;
2007         }
2008
2009         /* blow away mappings if mapped through GTT */
2010         i915_gem_release_mmap(obj);
2011
2012         /* Move the object to the CPU domain to ensure that
2013          * any possible CPU writes while it's not in the GTT
2014          * are flushed when we go to remap it. This will
2015          * also ensure that all pending GPU writes are finished
2016          * before we unbind.
2017          */
2018         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2019         if (ret) {
2020                 if (ret != -ERESTARTSYS)
2021                         DRM_ERROR("set_domain failed: %d\n", ret);
2022                 return ret;
2023         }
2024
2025         BUG_ON(obj_priv->active);
2026
2027         /* release the fence reg _after_ flushing */
2028         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2029                 i915_gem_clear_fence_reg(obj);
2030
2031         if (obj_priv->agp_mem != NULL) {
2032                 drm_unbind_agp(obj_priv->agp_mem);
2033                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2034                 obj_priv->agp_mem = NULL;
2035         }
2036
2037         i915_gem_object_put_pages(obj);
2038         BUG_ON(obj_priv->pages_refcount);
2039
2040         if (obj_priv->gtt_space) {
2041                 atomic_dec(&dev->gtt_count);
2042                 atomic_sub(obj->size, &dev->gtt_memory);
2043
2044                 drm_mm_put_block(obj_priv->gtt_space);
2045                 obj_priv->gtt_space = NULL;
2046         }
2047
2048         /* Remove ourselves from the LRU list if present. */
2049         if (!list_empty(&obj_priv->list))
2050                 list_del_init(&obj_priv->list);
2051
2052         if (i915_gem_object_is_purgeable(obj_priv))
2053                 i915_gem_object_truncate(obj);
2054
2055         trace_i915_gem_object_unbind(obj);
2056
2057         return 0;
2058 }
2059
2060 static struct drm_gem_object *
2061 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2062 {
2063         drm_i915_private_t *dev_priv = dev->dev_private;
2064         struct drm_i915_gem_object *obj_priv;
2065         struct drm_gem_object *best = NULL;
2066         struct drm_gem_object *first = NULL;
2067
2068         /* Try to find the smallest clean object */
2069         list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2070                 struct drm_gem_object *obj = obj_priv->obj;
2071                 if (obj->size >= min_size) {
2072                         if ((!obj_priv->dirty ||
2073                              i915_gem_object_is_purgeable(obj_priv)) &&
2074                             (!best || obj->size < best->size)) {
2075                                 best = obj;
2076                                 if (best->size == min_size)
2077                                         return best;
2078                         }
2079                         if (!first)
2080                             first = obj;
2081                 }
2082         }
2083
2084         return best ? best : first;
2085 }
2086
2087 static int
2088 i915_gem_evict_everything(struct drm_device *dev)
2089 {
2090         drm_i915_private_t *dev_priv = dev->dev_private;
2091         int ret;
2092         uint32_t seqno;
2093         bool lists_empty;
2094
2095         spin_lock(&dev_priv->mm.active_list_lock);
2096         lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2097                        list_empty(&dev_priv->mm.flushing_list) &&
2098                        list_empty(&dev_priv->mm.active_list));
2099         spin_unlock(&dev_priv->mm.active_list_lock);
2100
2101         if (lists_empty)
2102                 return -ENOSPC;
2103
2104         /* Flush everything (on to the inactive lists) and evict */
2105         i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2106         seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2107         if (seqno == 0)
2108                 return -ENOMEM;
2109
2110         ret = i915_wait_request(dev, seqno);
2111         if (ret)
2112                 return ret;
2113
2114         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2115
2116         ret = i915_gem_evict_from_inactive_list(dev);
2117         if (ret)
2118                 return ret;
2119
2120         spin_lock(&dev_priv->mm.active_list_lock);
2121         lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2122                        list_empty(&dev_priv->mm.flushing_list) &&
2123                        list_empty(&dev_priv->mm.active_list));
2124         spin_unlock(&dev_priv->mm.active_list_lock);
2125         BUG_ON(!lists_empty);
2126
2127         return 0;
2128 }
2129
2130 static int
2131 i915_gem_evict_something(struct drm_device *dev, int min_size)
2132 {
2133         drm_i915_private_t *dev_priv = dev->dev_private;
2134         struct drm_gem_object *obj;
2135         int ret;
2136
2137         for (;;) {
2138                 i915_gem_retire_requests(dev);
2139
2140                 /* If there's an inactive buffer available now, grab it
2141                  * and be done.
2142                  */
2143                 obj = i915_gem_find_inactive_object(dev, min_size);
2144                 if (obj) {
2145                         struct drm_i915_gem_object *obj_priv;
2146
2147 #if WATCH_LRU
2148                         DRM_INFO("%s: evicting %p\n", __func__, obj);
2149 #endif
2150                         obj_priv = obj->driver_private;
2151                         BUG_ON(obj_priv->pin_count != 0);
2152                         BUG_ON(obj_priv->active);
2153
2154                         /* Wait on the rendering and unbind the buffer. */
2155                         return i915_gem_object_unbind(obj);
2156                 }
2157
2158                 /* If we didn't get anything, but the ring is still processing
2159                  * things, wait for the next to finish and hopefully leave us
2160                  * a buffer to evict.
2161                  */
2162                 if (!list_empty(&dev_priv->mm.request_list)) {
2163                         struct drm_i915_gem_request *request;
2164
2165                         request = list_first_entry(&dev_priv->mm.request_list,
2166                                                    struct drm_i915_gem_request,
2167                                                    list);
2168
2169                         ret = i915_wait_request(dev, request->seqno);
2170                         if (ret)
2171                                 return ret;
2172
2173                         continue;
2174                 }
2175
2176                 /* If we didn't have anything on the request list but there
2177                  * are buffers awaiting a flush, emit one and try again.
2178                  * When we wait on it, those buffers waiting for that flush
2179                  * will get moved to inactive.
2180                  */
2181                 if (!list_empty(&dev_priv->mm.flushing_list)) {
2182                         struct drm_i915_gem_object *obj_priv;
2183
2184                         /* Find an object that we can immediately reuse */
2185                         list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2186                                 obj = obj_priv->obj;
2187                                 if (obj->size >= min_size)
2188                                         break;
2189
2190                                 obj = NULL;
2191                         }
2192
2193                         if (obj != NULL) {
2194                                 uint32_t seqno;
2195
2196                                 i915_gem_flush(dev,
2197                                                obj->write_domain,
2198                                                obj->write_domain);
2199                                 seqno = i915_add_request(dev, NULL, obj->write_domain);
2200                                 if (seqno == 0)
2201                                         return -ENOMEM;
2202
2203                                 ret = i915_wait_request(dev, seqno);
2204                                 if (ret)
2205                                         return ret;
2206
2207                                 continue;
2208                         }
2209                 }
2210
2211                 /* If we didn't do any of the above, there's no single buffer
2212                  * large enough to swap out for the new one, so just evict
2213                  * everything and start again. (This should be rare.)
2214                  */
2215                 if (!list_empty (&dev_priv->mm.inactive_list))
2216                         return i915_gem_evict_from_inactive_list(dev);
2217                 else
2218                         return i915_gem_evict_everything(dev);
2219         }
2220 }
2221
2222 int
2223 i915_gem_object_get_pages(struct drm_gem_object *obj,
2224                           gfp_t gfpmask)
2225 {
2226         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2227         int page_count, i;
2228         struct address_space *mapping;
2229         struct inode *inode;
2230         struct page *page;
2231         int ret;
2232
2233         if (obj_priv->pages_refcount++ != 0)
2234                 return 0;
2235
2236         /* Get the list of pages out of our struct file.  They'll be pinned
2237          * at this point until we release them.
2238          */
2239         page_count = obj->size / PAGE_SIZE;
2240         BUG_ON(obj_priv->pages != NULL);
2241         obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2242         if (obj_priv->pages == NULL) {
2243                 obj_priv->pages_refcount--;
2244                 return -ENOMEM;
2245         }
2246
2247         inode = obj->filp->f_path.dentry->d_inode;
2248         mapping = inode->i_mapping;
2249         for (i = 0; i < page_count; i++) {
2250                 page = read_cache_page_gfp(mapping, i,
2251                                            mapping_gfp_mask (mapping) |
2252                                            __GFP_COLD |
2253                                            gfpmask);
2254                 if (IS_ERR(page)) {
2255                         ret = PTR_ERR(page);
2256                         i915_gem_object_put_pages(obj);
2257                         return ret;
2258                 }
2259                 obj_priv->pages[i] = page;
2260         }
2261
2262         if (obj_priv->tiling_mode != I915_TILING_NONE)
2263                 i915_gem_object_do_bit_17_swizzle(obj);
2264
2265         return 0;
2266 }
2267
2268 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2269 {
2270         struct drm_gem_object *obj = reg->obj;
2271         struct drm_device *dev = obj->dev;
2272         drm_i915_private_t *dev_priv = dev->dev_private;
2273         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2274         int regnum = obj_priv->fence_reg;
2275         uint64_t val;
2276
2277         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2278                     0xfffff000) << 32;
2279         val |= obj_priv->gtt_offset & 0xfffff000;
2280         val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2281         if (obj_priv->tiling_mode == I915_TILING_Y)
2282                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2283         val |= I965_FENCE_REG_VALID;
2284
2285         I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2286 }
2287
2288 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2289 {
2290         struct drm_gem_object *obj = reg->obj;
2291         struct drm_device *dev = obj->dev;
2292         drm_i915_private_t *dev_priv = dev->dev_private;
2293         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2294         int regnum = obj_priv->fence_reg;
2295         int tile_width;
2296         uint32_t fence_reg, val;
2297         uint32_t pitch_val;
2298
2299         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2300             (obj_priv->gtt_offset & (obj->size - 1))) {
2301                 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2302                      __func__, obj_priv->gtt_offset, obj->size);
2303                 return;
2304         }
2305
2306         if (obj_priv->tiling_mode == I915_TILING_Y &&
2307             HAS_128_BYTE_Y_TILING(dev))
2308                 tile_width = 128;
2309         else
2310                 tile_width = 512;
2311
2312         /* Note: pitch better be a power of two tile widths */
2313         pitch_val = obj_priv->stride / tile_width;
2314         pitch_val = ffs(pitch_val) - 1;
2315
2316         val = obj_priv->gtt_offset;
2317         if (obj_priv->tiling_mode == I915_TILING_Y)
2318                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2319         val |= I915_FENCE_SIZE_BITS(obj->size);
2320         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2321         val |= I830_FENCE_REG_VALID;
2322
2323         if (regnum < 8)
2324                 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2325         else
2326                 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2327         I915_WRITE(fence_reg, val);
2328 }
2329
2330 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2331 {
2332         struct drm_gem_object *obj = reg->obj;
2333         struct drm_device *dev = obj->dev;
2334         drm_i915_private_t *dev_priv = dev->dev_private;
2335         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2336         int regnum = obj_priv->fence_reg;
2337         uint32_t val;
2338         uint32_t pitch_val;
2339         uint32_t fence_size_bits;
2340
2341         if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2342             (obj_priv->gtt_offset & (obj->size - 1))) {
2343                 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2344                      __func__, obj_priv->gtt_offset);
2345                 return;
2346         }
2347
2348         pitch_val = obj_priv->stride / 128;
2349         pitch_val = ffs(pitch_val) - 1;
2350         WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2351
2352         val = obj_priv->gtt_offset;
2353         if (obj_priv->tiling_mode == I915_TILING_Y)
2354                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2355         fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2356         WARN_ON(fence_size_bits & ~0x00000f00);
2357         val |= fence_size_bits;
2358         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2359         val |= I830_FENCE_REG_VALID;
2360
2361         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2362 }
2363
2364 /**
2365  * i915_gem_object_get_fence_reg - set up a fence reg for an object
2366  * @obj: object to map through a fence reg
2367  *
2368  * When mapping objects through the GTT, userspace wants to be able to write
2369  * to them without having to worry about swizzling if the object is tiled.
2370  *
2371  * This function walks the fence regs looking for a free one for @obj,
2372  * stealing one if it can't find any.
2373  *
2374  * It then sets up the reg based on the object's properties: address, pitch
2375  * and tiling format.
2376  */
2377 int
2378 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2379 {
2380         struct drm_device *dev = obj->dev;
2381         struct drm_i915_private *dev_priv = dev->dev_private;
2382         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2383         struct drm_i915_fence_reg *reg = NULL;
2384         struct drm_i915_gem_object *old_obj_priv = NULL;
2385         int i, ret, avail;
2386
2387         /* Just update our place in the LRU if our fence is getting used. */
2388         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2389                 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2390                 return 0;
2391         }
2392
2393         switch (obj_priv->tiling_mode) {
2394         case I915_TILING_NONE:
2395                 WARN(1, "allocating a fence for non-tiled object?\n");
2396                 break;
2397         case I915_TILING_X:
2398                 if (!obj_priv->stride)
2399                         return -EINVAL;
2400                 WARN((obj_priv->stride & (512 - 1)),
2401                      "object 0x%08x is X tiled but has non-512B pitch\n",
2402                      obj_priv->gtt_offset);
2403                 break;
2404         case I915_TILING_Y:
2405                 if (!obj_priv->stride)
2406                         return -EINVAL;
2407                 WARN((obj_priv->stride & (128 - 1)),
2408                      "object 0x%08x is Y tiled but has non-128B pitch\n",
2409                      obj_priv->gtt_offset);
2410                 break;
2411         }
2412
2413         /* First try to find a free reg */
2414         avail = 0;
2415         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2416                 reg = &dev_priv->fence_regs[i];
2417                 if (!reg->obj)
2418                         break;
2419
2420                 old_obj_priv = reg->obj->driver_private;
2421                 if (!old_obj_priv->pin_count)
2422                     avail++;
2423         }
2424
2425         /* None available, try to steal one or wait for a user to finish */
2426         if (i == dev_priv->num_fence_regs) {
2427                 struct drm_gem_object *old_obj = NULL;
2428
2429                 if (avail == 0)
2430                         return -ENOSPC;
2431
2432                 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2433                                     fence_list) {
2434                         old_obj = old_obj_priv->obj;
2435
2436                         if (old_obj_priv->pin_count)
2437                                 continue;
2438
2439                         /* Take a reference, as otherwise the wait_rendering
2440                          * below may cause the object to get freed out from
2441                          * under us.
2442                          */
2443                         drm_gem_object_reference(old_obj);
2444
2445                         /* i915 uses fences for GPU access to tiled buffers */
2446                         if (IS_I965G(dev) || !old_obj_priv->active)
2447                                 break;
2448
2449                         /* This brings the object to the head of the LRU if it
2450                          * had been written to.  The only way this should
2451                          * result in us waiting longer than the expected
2452                          * optimal amount of time is if there was a
2453                          * fence-using buffer later that was read-only.
2454                          */
2455                         i915_gem_object_flush_gpu_write_domain(old_obj);
2456                         ret = i915_gem_object_wait_rendering(old_obj);
2457                         if (ret != 0) {
2458                                 drm_gem_object_unreference(old_obj);
2459                                 return ret;
2460                         }
2461
2462                         break;
2463                 }
2464
2465                 /*
2466                  * Zap this virtual mapping so we can set up a fence again
2467                  * for this object next time we need it.
2468                  */
2469                 i915_gem_release_mmap(old_obj);
2470
2471                 i = old_obj_priv->fence_reg;
2472                 reg = &dev_priv->fence_regs[i];