OMAP3: SDRC: add 100MHz timing data for Hynix H8KDS0UN0MER-4EM
authorRanjith Lohithakshan <ranjithl@ti.com>
Fri, 28 May 2010 09:43:18 +0000 (15:13 +0530)
committerRanjith Lohithakshan <ranjithl@ti.com>
Fri, 28 May 2010 09:43:18 +0000 (15:13 +0530)
commit908b7949544571e9acc1fe0cce918f6e338926c9
tree0e20b4e7a746376ceb3d30a7f7ddf2e9a6836fa9
parenta6bad4464f985fdd3bed72e1b82dcbfc004d7869
OMAP3: SDRC: add 100MHz timing data for Hynix H8KDS0UN0MER-4EM

Also, the refresh control value used at 200MHz was incorrect. Fixed
that as well.

Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com>
arch/arm/mach-omap2/sdram-hynix-h8kds0un0mer-4em.h