wl1271: Add wl1271_load_firmware() and export some functions
[beagleboard-validation:linux.git] / drivers / net / wireless / wl12xx / boot.c
1 /*
2  * This file is part of wl1271
3  *
4  * Copyright (C) 2008-2010 Nokia Corporation
5  *
6  * Contact: Luciano Coelho <luciano.coelho@nokia.com>
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but
13  * WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20  * 02110-1301 USA
21  *
22  */
23
24 #include <linux/gpio.h>
25 #include <linux/slab.h>
26
27 #include "acx.h"
28 #include "reg.h"
29 #include "boot.h"
30 #include "io.h"
31 #include "event.h"
32
33 static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
34         [PART_DOWN] = {
35                 .mem = {
36                         .start = 0x00000000,
37                         .size  = 0x000177c0
38                 },
39                 .reg = {
40                         .start = REGISTERS_BASE,
41                         .size  = 0x00008800
42                 },
43                 .mem2 = {
44                         .start = 0x00000000,
45                         .size  = 0x00000000
46                 },
47                 .mem3 = {
48                         .start = 0x00000000,
49                         .size  = 0x00000000
50                 },
51         },
52
53         [PART_WORK] = {
54                 .mem = {
55                         .start = 0x00040000,
56                         .size  = 0x00014fc0
57                 },
58                 .reg = {
59                         .start = REGISTERS_BASE,
60                         .size  = 0x0000a000
61                 },
62                 .mem2 = {
63                         .start = 0x003004f8,
64                         .size  = 0x00000004
65                 },
66                 .mem3 = {
67                         .start = 0x00040404,
68                         .size  = 0x00000000
69                 },
70         },
71
72         [PART_DRPW] = {
73                 .mem = {
74                         .start = 0x00040000,
75                         .size  = 0x00014fc0
76                 },
77                 .reg = {
78                         .start = DRPW_BASE,
79                         .size  = 0x00006000
80                 },
81                 .mem2 = {
82                         .start = 0x00000000,
83                         .size  = 0x00000000
84                 },
85                 .mem3 = {
86                         .start = 0x00000000,
87                         .size  = 0x00000000
88                 }
89         }
90 };
91
92 static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
93 {
94         u32 cpu_ctrl;
95
96         /* 10.5.0 run the firmware (I) */
97         cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL);
98
99         /* 10.5.1 run the firmware (II) */
100         cpu_ctrl |= flag;
101         wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
102 }
103
104 static void wl1271_boot_fw_version(struct wl1271 *wl)
105 {
106         struct wl1271_static_data static_data;
107
108         wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data),
109                     false);
110
111         strncpy(wl->chip.fw_ver, static_data.fw_version,
112                 sizeof(wl->chip.fw_ver));
113
114         /* make sure the string is NULL-terminated */
115         wl->chip.fw_ver[sizeof(wl->chip.fw_ver) - 1] = '\0';
116 }
117
118 static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
119                                              size_t fw_data_len, u32 dest)
120 {
121         struct wl1271_partition_set partition;
122         int addr, chunk_num, partition_limit;
123         u8 *p, *chunk;
124
125         /* whal_FwCtrl_LoadFwImageSm() */
126
127         wl1271_debug(DEBUG_BOOT, "starting firmware upload");
128
129         wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
130                      fw_data_len, CHUNK_SIZE);
131
132         if ((fw_data_len % 4) != 0) {
133                 wl1271_error("firmware length not multiple of four");
134                 return -EIO;
135         }
136
137         chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
138         if (!chunk) {
139                 wl1271_error("allocation for firmware upload chunk failed");
140                 return -ENOMEM;
141         }
142
143         memcpy(&partition, &part_table[PART_DOWN], sizeof(partition));
144         partition.mem.start = dest;
145         wl1271_set_partition(wl, &partition);
146
147         /* 10.1 set partition limit and chunk num */
148         chunk_num = 0;
149         partition_limit = part_table[PART_DOWN].mem.size;
150
151         while (chunk_num < fw_data_len / CHUNK_SIZE) {
152                 /* 10.2 update partition, if needed */
153                 addr = dest + (chunk_num + 2) * CHUNK_SIZE;
154                 if (addr > partition_limit) {
155                         addr = dest + chunk_num * CHUNK_SIZE;
156                         partition_limit = chunk_num * CHUNK_SIZE +
157                                 part_table[PART_DOWN].mem.size;
158                         partition.mem.start = addr;
159                         wl1271_set_partition(wl, &partition);
160                 }
161
162                 /* 10.3 upload the chunk */
163                 addr = dest + chunk_num * CHUNK_SIZE;
164                 p = buf + chunk_num * CHUNK_SIZE;
165                 memcpy(chunk, p, CHUNK_SIZE);
166                 wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
167                              p, addr);
168                 wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);
169
170                 chunk_num++;
171         }
172
173         /* 10.4 upload the last chunk */
174         addr = dest + chunk_num * CHUNK_SIZE;
175         p = buf + chunk_num * CHUNK_SIZE;
176         memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
177         wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
178                      fw_data_len % CHUNK_SIZE, p, addr);
179         wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
180
181         kfree(chunk);
182         return 0;
183 }
184
185 static int wl1271_boot_upload_firmware(struct wl1271 *wl)
186 {
187         u32 chunks, addr, len;
188         int ret = 0;
189         u8 *fw;
190
191         fw = wl->fw;
192         chunks = be32_to_cpup((__be32 *) fw);
193         fw += sizeof(u32);
194
195         wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
196
197         while (chunks--) {
198                 addr = be32_to_cpup((__be32 *) fw);
199                 fw += sizeof(u32);
200                 len = be32_to_cpup((__be32 *) fw);
201                 fw += sizeof(u32);
202
203                 if (len > 300000) {
204                         wl1271_info("firmware chunk too long: %u", len);
205                         return -EINVAL;
206                 }
207                 wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
208                              chunks, addr, len);
209                 ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
210                 if (ret != 0)
211                         break;
212                 fw += len;
213         }
214
215         return ret;
216 }
217
218 static int wl1271_boot_upload_nvs(struct wl1271 *wl)
219 {
220         size_t nvs_len, burst_len;
221         int i;
222         u32 dest_addr, val;
223         u8 *nvs_ptr, *nvs_aligned;
224
225         if (wl->nvs == NULL)
226                 return -ENODEV;
227
228         /*
229          * FIXME: the LEGACY NVS image support (NVS's missing the 5GHz band
230          * configurations) can be removed when those NVS files stop floating
231          * around.
232          */
233         if (wl->nvs_len == sizeof(struct wl1271_nvs_file) ||
234             wl->nvs_len == WL1271_INI_LEGACY_NVS_FILE_SIZE) {
235                 if (wl->nvs->general_params.dual_mode_select)
236                         wl->enable_11a = true;
237         }
238
239         if (wl->nvs_len != sizeof(struct wl1271_nvs_file) &&
240             (wl->nvs_len != WL1271_INI_LEGACY_NVS_FILE_SIZE ||
241              wl->enable_11a)) {
242                 wl1271_error("nvs size is not as expected: %zu != %zu",
243                              wl->nvs_len, sizeof(struct wl1271_nvs_file));
244                 kfree(wl->nvs);
245                 wl->nvs = NULL;
246                 wl->nvs_len = 0;
247                 return -EILSEQ;
248         }
249
250         /* only the first part of the NVS needs to be uploaded */
251         nvs_len = sizeof(wl->nvs->nvs);
252         nvs_ptr = (u8 *)wl->nvs->nvs;
253
254         /* update current MAC address to NVS */
255         nvs_ptr[11] = wl->mac_addr[0];
256         nvs_ptr[10] = wl->mac_addr[1];
257         nvs_ptr[6] = wl->mac_addr[2];
258         nvs_ptr[5] = wl->mac_addr[3];
259         nvs_ptr[4] = wl->mac_addr[4];
260         nvs_ptr[3] = wl->mac_addr[5];
261
262         /*
263          * Layout before the actual NVS tables:
264          * 1 byte : burst length.
265          * 2 bytes: destination address.
266          * n bytes: data to burst copy.
267          *
268          * This is ended by a 0 length, then the NVS tables.
269          */
270
271         /* FIXME: Do we need to check here whether the LSB is 1? */
272         while (nvs_ptr[0]) {
273                 burst_len = nvs_ptr[0];
274                 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
275
276                 /*
277                  * Due to our new wl1271_translate_reg_addr function,
278                  * we need to add the REGISTER_BASE to the destination
279                  */
280                 dest_addr += REGISTERS_BASE;
281
282                 /* We move our pointer to the data */
283                 nvs_ptr += 3;
284
285                 for (i = 0; i < burst_len; i++) {
286                         val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
287                                | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
288
289                         wl1271_debug(DEBUG_BOOT,
290                                      "nvs burst write 0x%x: 0x%x",
291                                      dest_addr, val);
292                         wl1271_write32(wl, dest_addr, val);
293
294                         nvs_ptr += 4;
295                         dest_addr += 4;
296                 }
297         }
298
299         /*
300          * We've reached the first zero length, the first NVS table
301          * is located at an aligned offset which is at least 7 bytes further.
302          */
303         nvs_ptr = (u8 *)wl->nvs->nvs +
304                         ALIGN(nvs_ptr - (u8 *)wl->nvs->nvs + 7, 4);
305         nvs_len -= nvs_ptr - (u8 *)wl->nvs->nvs;
306
307         /* Now we must set the partition correctly */
308         wl1271_set_partition(wl, &part_table[PART_WORK]);
309
310         /* Copy the NVS tables to a new block to ensure alignment */
311         nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
312         if (!nvs_aligned)
313                 return -ENOMEM;
314
315         /* And finally we upload the NVS tables */
316         wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
317
318         kfree(nvs_aligned);
319         return 0;
320 }
321
322 static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
323 {
324         wl1271_enable_interrupts(wl);
325         wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
326                        WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
327         wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
328 }
329
330 static int wl1271_boot_soft_reset(struct wl1271 *wl)
331 {
332         unsigned long timeout;
333         u32 boot_data;
334
335         /* perform soft reset */
336         wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
337
338         /* SOFT_RESET is self clearing */
339         timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
340         while (1) {
341                 boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET);
342                 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
343                 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
344                         break;
345
346                 if (time_after(jiffies, timeout)) {
347                         /* 1.2 check pWhalBus->uSelfClearTime if the
348                          * timeout was reached */
349                         wl1271_error("soft reset timeout");
350                         return -1;
351                 }
352
353                 udelay(SOFT_RESET_STALL_TIME);
354         }
355
356         /* disable Rx/Tx */
357         wl1271_write32(wl, ENABLE, 0x0);
358
359         /* disable auto calibration on start*/
360         wl1271_write32(wl, SPARE_A2, 0xffff);
361
362         return 0;
363 }
364
365 static int wl1271_boot_run_firmware(struct wl1271 *wl)
366 {
367         int loop, ret;
368         u32 chip_id, intr;
369
370         wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
371
372         chip_id = wl1271_read32(wl, CHIP_ID_B);
373
374         wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
375
376         if (chip_id != wl->chip.id) {
377                 wl1271_error("chip id doesn't match after firmware boot");
378                 return -EIO;
379         }
380
381         /* wait for init to complete */
382         loop = 0;
383         while (loop++ < INIT_LOOP) {
384                 udelay(INIT_LOOP_DELAY);
385                 intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
386
387                 if (intr == 0xffffffff) {
388                         wl1271_error("error reading hardware complete "
389                                      "init indication");
390                         return -EIO;
391                 }
392                 /* check that ACX_INTR_INIT_COMPLETE is enabled */
393                 else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) {
394                         wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
395                                        WL1271_ACX_INTR_INIT_COMPLETE);
396                         break;
397                 }
398         }
399
400         if (loop > INIT_LOOP) {
401                 wl1271_error("timeout waiting for the hardware to "
402                              "complete initialization");
403                 return -EIO;
404         }
405
406         /* get hardware config command mail box */
407         wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR);
408
409         /* get hardware config event mail box */
410         wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
411
412         /* set the working partition to its "running" mode offset */
413         wl1271_set_partition(wl, &part_table[PART_WORK]);
414
415         wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
416                      wl->cmd_box_addr, wl->event_box_addr);
417
418         wl1271_boot_fw_version(wl);
419
420         /*
421          * in case of full asynchronous mode the firmware event must be
422          * ready to receive event from the command mailbox
423          */
424
425         /* unmask required mbox events  */
426         wl->event_mask = BSS_LOSE_EVENT_ID |
427                 SCAN_COMPLETE_EVENT_ID |
428                 PS_REPORT_EVENT_ID |
429                 JOIN_EVENT_COMPLETE_ID |
430                 DISCONNECT_EVENT_COMPLETE_ID |
431                 RSSI_SNR_TRIGGER_0_EVENT_ID |
432                 PSPOLL_DELIVERY_FAILURE_EVENT_ID |
433                 SOFT_GEMINI_SENSE_EVENT_ID;
434
435         ret = wl1271_event_unmask(wl);
436         if (ret < 0) {
437                 wl1271_error("EVENT mask setting failed");
438                 return ret;
439         }
440
441         wl1271_event_mbox_config(wl);
442
443         /* firmware startup completed */
444         return 0;
445 }
446
447 static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
448 {
449         u32 polarity;
450
451         polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);
452
453         /* We use HIGH polarity, so unset the LOW bit */
454         polarity &= ~POLARITY_LOW;
455         wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);
456
457         return 0;
458 }
459
460 static void wl1271_boot_hw_version(struct wl1271 *wl)
461 {
462         u32 fuse;
463
464         fuse = wl1271_top_reg_read(wl, REG_FUSE_DATA_2_1);
465         fuse = (fuse & PG_VER_MASK) >> PG_VER_OFFSET;
466
467         wl->hw_pg_ver = (s8)fuse;
468 }
469
470 /* uploads NVS and firmware */
471 int wl1271_load_firmware(struct wl1271 *wl)
472 {
473         int ret = 0;
474         u32 tmp, clk, pause;
475
476         wl1271_boot_hw_version(wl);
477
478         if (wl->ref_clock == 0 || wl->ref_clock == 2 || wl->ref_clock == 4)
479                 /* ref clk: 19.2/38.4/38.4-XTAL */
480                 clk = 0x3;
481         else if (wl->ref_clock == 1 || wl->ref_clock == 3)
482                 /* ref clk: 26/52 */
483                 clk = 0x5;
484         else
485                 return -EINVAL;
486
487         if (wl->ref_clock != 0) {
488                 u16 val;
489                 /* Set clock type (open drain) */
490                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
491                 val &= FREF_CLK_TYPE_BITS;
492                 wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
493
494                 /* Set clock pull mode (no pull) */
495                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_PULL);
496                 val |= NO_PULL;
497                 wl1271_top_reg_write(wl, OCP_REG_CLK_PULL, val);
498         } else {
499                 u16 val;
500                 /* Set clock polarity */
501                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
502                 val &= FREF_CLK_POLARITY_BITS;
503                 val |= CLK_REQ_OUTN_SEL;
504                 wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
505         }
506
507         wl1271_write32(wl, PLL_PARAMETERS, clk);
508
509         pause = wl1271_read32(wl, PLL_PARAMETERS);
510
511         wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
512
513         pause &= ~(WU_COUNTER_PAUSE_VAL);
514         pause |= WU_COUNTER_PAUSE_VAL;
515         wl1271_write32(wl, WU_COUNTER_PAUSE, pause);
516
517         /* Continue the ELP wake up sequence */
518         wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
519         udelay(500);
520
521         wl1271_set_partition(wl, &part_table[PART_DRPW]);
522
523         /* Read-modify-write DRPW_SCRATCH_START register (see next state)
524            to be used by DRPw FW. The RTRIM value will be added by the FW
525            before taking DRPw out of reset */
526
527         wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
528         clk = wl1271_read32(wl, DRPW_SCRATCH_START);
529
530         wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
531
532         clk |= (wl->ref_clock << 1) << 4;
533         wl1271_write32(wl, DRPW_SCRATCH_START, clk);
534
535         wl1271_set_partition(wl, &part_table[PART_WORK]);
536
537         /* Disable interrupts */
538         wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
539
540         ret = wl1271_boot_soft_reset(wl);
541         if (ret < 0)
542                 goto out;
543
544         /* 2. start processing NVS file */
545         ret = wl1271_boot_upload_nvs(wl);
546         if (ret < 0)
547                 goto out;
548
549         /* write firmware's last address (ie. it's length) to
550          * ACX_EEPROMLESS_IND_REG */
551         wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
552
553         wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
554
555         tmp = wl1271_read32(wl, CHIP_ID_B);
556
557         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
558
559         /* 6. read the EEPROM parameters */
560         tmp = wl1271_read32(wl, SCR_PAD2);
561
562         ret = wl1271_boot_write_irq_polarity(wl);
563         if (ret < 0)
564                 goto out;
565
566         wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
567                        WL1271_ACX_ALL_EVENTS_VECTOR);
568
569         /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
570          * to upload_fw) */
571
572         ret = wl1271_boot_upload_firmware(wl);
573         if (ret < 0)
574                 goto out;
575
576 out:
577         return ret;
578 }
579 EXPORT_SYMBOL_GPL(wl1271_load_firmware);
580
581 int wl1271_boot(struct wl1271 *wl)
582 {
583         int ret;
584
585         /* upload NVS and firmware */
586         ret = wl1271_load_firmware(wl);
587         if (ret)
588                 return ret;
589
590         /* 10.5 start firmware */
591         ret = wl1271_boot_run_firmware(wl);
592         if (ret < 0)
593                 goto out;
594
595         /* Enable firmware interrupts now */
596         wl1271_boot_enable_interrupts(wl);
597
598         /* set the wl1271 default filters */
599         wl->rx_config = WL1271_DEFAULT_RX_CONFIG;
600         wl->rx_filter = WL1271_DEFAULT_RX_FILTER;
601
602         wl1271_event_mbox_config(wl);
603
604 out:
605         return ret;
606 }