ARM: 7015/1: ARM errata: Possible cache data corruption with hit-under-miss enabled
authorCatalin Marinas <catalin.marinas@arm.com>
Mon, 15 Aug 2011 10:04:41 +0000 (11:04 +0100)
committerJason Kridner <jdk@ti.com>
Sat, 17 Sep 2011 13:14:33 +0000 (09:14 -0400)
commit58bd06d3e9f69abd7ccaa2e480f35532ac7c476f
treea48e304763dfe8ba3007808b9bbbf684acd6b950
parent58deb1c9cd37154a75fba418af84f5d4dc234375
ARM: 7015/1: ARM errata: Possible cache data corruption with hit-under-miss enabled

This patch is a workaround for the 364296 ARM1136 r0p2 erratum (possible
cache data corruption with hit-under-miss enabled). It sets the
undocumented bit 31 in the auxiliary control register and the FI bit in
the control register, thus disabling hit-under-miss without putting the
processor into full low interrupt latency mode.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit 6e4365cf13702d2249b4bcd424d30db3b13bd6da)
arch/arm/Kconfig
arch/arm/mm/proc-v6.S