ARM: 7015/1: ARM errata: Possible cache data corruption with hit-under-miss enabled
authorCatalin Marinas <catalin.marinas@arm.com>
Mon, 15 Aug 2011 10:04:41 +0000 (11:04 +0100)
committerJason Kridner <jdk@ti.com>
Thu, 15 Sep 2011 18:59:14 +0000 (14:59 -0400)
commit24e0eebbeb902847f6585a2bc9a60ff78da346f7
treeb2f1c3e325d83019cf1e5f5d873996dad91c233f
parent22d37e4cffe599aa4a9fb3bd7b9dcadd6440d669
ARM: 7015/1: ARM errata: Possible cache data corruption with hit-under-miss enabled

This patch is a workaround for the 364296 ARM1136 r0p2 erratum (possible
cache data corruption with hit-under-miss enabled). It sets the
undocumented bit 31 in the auxiliary control register and the FI bit in
the control register, thus disabling hit-under-miss without putting the
processor into full low interrupt latency mode.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit 6e4365cf13702d2249b4bcd424d30db3b13bd6da)
arch/arm/Kconfig
arch/arm/mm/proc-v6.S