ARM: 7014/1: cache-l2x0: Fix L2 Cache size calculation.
authorSrinivas Kandagatla <srinivas.kandagatla@st.com>
Mon, 15 Aug 2011 09:43:44 +0000 (10:43 +0100)
committerJason Kridner <jdk@ti.com>
Thu, 15 Sep 2011 18:59:13 +0000 (14:59 -0400)
commit22d37e4cffe599aa4a9fb3bd7b9dcadd6440d669
tree2d0d2dd9a80d98f7108148251d21463a6a0d57f5
parent8433df4db7d44201189b579e6933e893bb52d8f5
ARM: 7014/1: cache-l2x0: Fix L2 Cache size calculation.

This patch fixes L2 Cache size calculations for L2C-210, L2C-310 and
PL310, by changing the L2X0_AUX_CTRL_WAY_SIZE_MASK from 2 bits to 3
bits.

The Auxiliary Control Register for L2C-210, L2C-310 and PL310 has 3bits
[19:17] for Way size, however the existing code only uses 2 bits to
get this value. This results in incorrect cachesize calculations.

It also results in performing operations on the whole cache when we
erroneously decide that the range is big enough (due to l2x0_size being
too small) and also prints incorrect cachesize.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: stable@kernel.org
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit 061b6358605d4d7597744d7be3bd5b9f74bfabfc)
arch/arm/include/asm/hardware/cache-l2x0.h