am335x: setup ddr pll's when configuring ddr emif registers
authorHebbar, Gururaja <gururaja.hebbar@ti.com>
Tue, 8 May 2012 13:17:37 +0000 (18:47 +0530)
committerTom Rini <trini@ti.com>
Tue, 8 May 2012 16:18:24 +0000 (09:18 -0700)
commitee66f0c08d83f644ccf02d46fe96b74c7e1e2a93
tree75605919b8ac52b5de6f9ea2f5b28128e529d364
parent71c1c65fc496067d9e56af3c425cd47ea2edfd3c
am335x: setup ddr pll's when configuring ddr emif registers

Different DDR's are run at different frequency (and may be on differents
boards as-well). DDR2 on EVM, BB = 266MHz, DDR3 on EVM-SK = 303 MHz.

So this patch moves the ddr pll init to ddr emif register configuration
stage.

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
board/ti/am335x/common_def.h
board/ti/am335x/evm.c
board/ti/am335x/pll.c