ARM: AM33XX: clock: Fix wrong parent clock for cpsw_cpts_rft_clk
[am335x:linux-am33x.git] / arch / arm / mach-omap2 / clock33xx_data.c
1 /*
2  * AM33XX Clock data
3  *
4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation version 2.
9  *
10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11  * kind, whether express or implied; without even the implied warranty
12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13  * GNU General Public License for more details.
14  */
15
16 #include <linux/kernel.h>
17 #include <linux/list.h>
18 #include <linux/clk.h>
19 #include <plat/clkdev_omap.h>
20
21 #include "control.h"
22 #include "clock.h"
23 #include "clock33xx.h"
24 #include "cm.h"
25 #include "cm33xx.h"
26 #include "cm-regbits-33xx.h"
27 #include "prm.h"
28
29 /* Modulemode control */
30 #define AM33XX_MODULEMODE_HWCTRL        0
31 #define AM33XX_MODULEMODE_SWCTRL        1
32
33 /* Root clocks */
34 static struct clk clk_32768_ck = {
35         .name           = "clk_32768_ck",
36         .rate           = 32768,
37         .ops            = &clkops_null,
38 };
39
40 /* On-Chip 32KHz RC OSC */
41 static struct clk clk_rc32k_ck = {
42         .name           = "clk_rc32k_ck",
43         .rate           = 32000,
44         .ops            = &clkops_null,
45 };
46
47 /* Crystal input clks */
48 static struct clk virt_19_2m_ck = {
49         .name           = "virt_19_2m_ck",
50         .rate           = 19200000,
51         .ops            = &clkops_null,
52 };
53
54 static struct clk virt_24m_ck = {
55         .name           = "virt_24m_ck",
56         .rate           = 24000000,
57         .ops            = &clkops_null,
58 };
59
60 static struct clk virt_25m_ck = {
61         .name           = "virt_25m_ck",
62         .rate           = 25000000,
63         .ops            = &clkops_null,
64 };
65
66 static struct clk virt_26m_ck = {
67         .name           = "virt_26m_ck",
68         .rate           = 26000000,
69         .ops            = &clkops_null,
70 };
71
72 static struct clk tclkin_ck = {
73         .name           = "tclkin_ck",
74         .rate           = 12000000,
75         .ops            = &clkops_null,
76 };
77
78 static const struct clksel_rate div_1_0_rates[] = {
79         { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
80         { .div = 0 },
81 };
82
83 static const struct clksel_rate div_1_1_rates[] = {
84         { .div = 1, .val = 1, .flags = RATE_IN_AM33XX },
85         { .div = 0 },
86 };
87
88 static const struct clksel_rate div_1_2_rates[] = {
89         { .div = 1, .val = 2, .flags = RATE_IN_AM33XX },
90         { .div = 0 },
91 };
92
93 static const struct clksel_rate div_1_3_rates[] = {
94         { .div = 1, .val = 3, .flags = RATE_IN_AM33XX },
95         { .div = 0 },
96 };
97
98 static const struct clksel_rate div_1_4_rates[] = {
99         { .div = 1, .val = 4, .flags = RATE_IN_AM33XX },
100         { .div = 0 },
101 };
102
103 static const struct clksel_rate div31_1to31_rates[] = {
104         { .div = 1, .val = 1, .flags = RATE_IN_AM33XX },
105         { .div = 2, .val = 2, .flags = RATE_IN_AM33XX },
106         { .div = 3, .val = 3, .flags = RATE_IN_AM33XX },
107         { .div = 4, .val = 4, .flags = RATE_IN_AM33XX },
108         { .div = 5, .val = 5, .flags = RATE_IN_AM33XX },
109         { .div = 6, .val = 6, .flags = RATE_IN_AM33XX },
110         { .div = 7, .val = 7, .flags = RATE_IN_AM33XX },
111         { .div = 8, .val = 8, .flags = RATE_IN_AM33XX },
112         { .div = 9, .val = 9, .flags = RATE_IN_AM33XX },
113         { .div = 10, .val = 10, .flags = RATE_IN_AM33XX },
114         { .div = 11, .val = 11, .flags = RATE_IN_AM33XX },
115         { .div = 12, .val = 12, .flags = RATE_IN_AM33XX },
116         { .div = 13, .val = 13, .flags = RATE_IN_AM33XX },
117         { .div = 14, .val = 14, .flags = RATE_IN_AM33XX },
118         { .div = 15, .val = 15, .flags = RATE_IN_AM33XX },
119         { .div = 16, .val = 16, .flags = RATE_IN_AM33XX },
120         { .div = 17, .val = 17, .flags = RATE_IN_AM33XX },
121         { .div = 18, .val = 18, .flags = RATE_IN_AM33XX },
122         { .div = 19, .val = 19, .flags = RATE_IN_AM33XX },
123         { .div = 20, .val = 20, .flags = RATE_IN_AM33XX },
124         { .div = 21, .val = 21, .flags = RATE_IN_AM33XX },
125         { .div = 22, .val = 22, .flags = RATE_IN_AM33XX },
126         { .div = 23, .val = 23, .flags = RATE_IN_AM33XX },
127         { .div = 24, .val = 24, .flags = RATE_IN_AM33XX },
128         { .div = 25, .val = 25, .flags = RATE_IN_AM33XX },
129         { .div = 26, .val = 26, .flags = RATE_IN_AM33XX },
130         { .div = 27, .val = 27, .flags = RATE_IN_AM33XX },
131         { .div = 28, .val = 28, .flags = RATE_IN_AM33XX },
132         { .div = 29, .val = 29, .flags = RATE_IN_AM33XX },
133         { .div = 30, .val = 30, .flags = RATE_IN_AM33XX },
134         { .div = 31, .val = 31, .flags = RATE_IN_AM33XX },
135         { .div = 0 },
136 };
137
138 /* Oscillator clock */
139 /* 19.2, 24, 25 or 26 MHz */
140 static const struct clksel sys_clkin_sel[] = {
141         { .parent = &virt_19_2m_ck, .rates = div_1_0_rates },
142         { .parent = &virt_24m_ck, .rates = div_1_1_rates },
143         { .parent = &virt_25m_ck, .rates = div_1_2_rates },
144         { .parent = &virt_26m_ck, .rates = div_1_3_rates },
145         { .parent = NULL },
146 };
147
148 /* sys_clk_in */
149 static struct clk sys_clkin_ck = {
150         .name           = "sys_clkin_ck",
151         .parent         = &virt_24m_ck,
152         .init           = &omap2_init_clksel_parent,
153         .clksel_reg     = AM33XX_CTRL_REGADDR(0x40),    /* CONTROL_STATUS */
154         .clksel_mask    = (0x3 << 22),
155         .clksel         = sys_clkin_sel,
156         .ops            = &clkops_null,
157         .recalc         = &omap2_clksel_recalc,
158 };
159
160 /* DPLL_CORE */
161 static struct dpll_data dpll_core_dd = {
162         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_CORE,
163         .clk_bypass     = &sys_clkin_ck,
164         .clk_ref        = &sys_clkin_ck,
165         .control_reg    = AM33XX_CM_CLKMODE_DPLL_CORE,
166         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
167         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_CORE,
168         .mult_mask      = AM33XX_DPLL_MULT_MASK,
169         .div1_mask      = AM33XX_DPLL_DIV_MASK,
170         .enable_mask    = AM33XX_DPLL_EN_MASK,
171         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
172         .max_multiplier = AM33XX_MAX_DPLL_MULT,
173         .max_divider    = AM33XX_MAX_DPLL_DIV,
174         .min_divider    = 1,
175 };
176
177 /* CLKDCOLDO output */
178 static struct clk dpll_core_ck = {
179         .name           = "dpll_core_ck",
180         .parent         = &sys_clkin_ck,
181         .dpll_data      = &dpll_core_dd,
182         .init           = &omap2_init_dpll_parent,
183         .ops            = &clkops_omap3_core_dpll_ops,
184         .recalc         = &omap3_dpll_recalc,
185 };
186
187 static struct clk dpll_core_x2_ck = {
188         .name           = "dpll_core_x2_ck",
189         .parent         = &dpll_core_ck,
190         .flags          = CLOCK_CLKOUTX2,
191         .ops            = &clkops_null,
192         .recalc         = &omap3_clkoutx2_recalc,
193 };
194
195
196 static const struct clksel dpll_core_m4_div[] = {
197         { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
198         { .parent = NULL },
199 };
200
201 static struct clk dpll_core_m4_ck = {
202         .name           = "dpll_core_m4_ck",
203         .parent         = &dpll_core_x2_ck,
204         .clksel         = dpll_core_m4_div,
205         .clksel_reg     = AM33XX_CM_DIV_M4_DPLL_CORE,
206         .clksel_mask    = AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK,
207         .ops            = &clkops_null,
208         .recalc         = &omap2_clksel_recalc,
209         .round_rate     = &omap2_clksel_round_rate,
210         .set_rate       = &omap2_clksel_set_rate,
211 };
212
213 static const struct clksel dpll_core_m5_div[] = {
214         { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
215         { .parent = NULL },
216 };
217
218 static struct clk dpll_core_m5_ck = {
219         .name           = "dpll_core_m5_ck",
220         .parent         = &dpll_core_x2_ck,
221         .clksel         = dpll_core_m5_div,
222         .clksel_reg     = AM33XX_CM_DIV_M5_DPLL_CORE,
223         .clksel_mask    = AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK,
224         .ops            = &clkops_null,
225         .recalc         = &omap2_clksel_recalc,
226         .round_rate     = &omap2_clksel_round_rate,
227         .set_rate       = &omap2_clksel_set_rate,
228 };
229
230 static const struct clksel dpll_core_m6_div[] = {
231         { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
232         { .parent = NULL },
233 };
234
235 static struct clk dpll_core_m6_ck = {
236         .name           = "dpll_core_m6_ck",
237         .parent         = &dpll_core_x2_ck,
238         .clksel         = dpll_core_m6_div,
239         .clksel_reg     = AM33XX_CM_DIV_M6_DPLL_CORE,
240         .clksel_mask    = AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK,
241         .ops            = &clkops_null,
242         .recalc         = &omap2_clksel_recalc,
243         .round_rate     = &omap2_clksel_round_rate,
244         .set_rate       = &omap2_clksel_set_rate,
245 };
246
247 static struct clk sysclk1_ck = {
248         .name           = "sysclk1_ck",
249         .parent         = &dpll_core_m4_ck,
250         .ops            = &clkops_null,
251         .recalc         = &followparent_recalc,
252 };
253
254 static struct clk sysclk2_ck = {
255         .name           = "sysclk2_ck",
256         .parent         = &dpll_core_m5_ck,
257         .ops            = &clkops_null,
258         .recalc         = &followparent_recalc,
259 };
260
261 static struct clk core_clk_out = {
262         .name           = "core_clk_out",
263         .parent         = &dpll_core_m4_ck,
264         .ops            = &clkops_null,
265         .recalc         = &followparent_recalc,
266 };
267
268 /* DPLL_MPU */
269 static struct dpll_data dpll_mpu_dd = {
270         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_MPU,
271         .clk_bypass     = &sys_clkin_ck,
272         .clk_ref        = &sys_clkin_ck,
273         .control_reg    = AM33XX_CM_CLKMODE_DPLL_MPU,
274         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
275         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_MPU,
276         .mult_mask      = AM33XX_DPLL_MULT_MASK,
277         .div1_mask      = AM33XX_DPLL_DIV_MASK,
278         .enable_mask    = AM33XX_DPLL_EN_MASK,
279         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
280         .max_multiplier = AM33XX_MAX_DPLL_MULT,
281         .max_divider    = AM33XX_MAX_DPLL_DIV,
282         .min_divider    = 1,
283 };
284
285 /* CLKOUT: fdpll/M2 */
286 static struct clk dpll_mpu_ck = {
287         .name           = "dpll_mpu_ck",
288         .parent         = &sys_clkin_ck,
289         .dpll_data      = &dpll_mpu_dd,
290         .init           = &omap2_init_dpll_parent,
291         .ops            = &clkops_omap3_noncore_dpll_ops,
292         .recalc         = &omap3_dpll_recalc,
293         .round_rate     = &omap2_dpll_round_rate,
294         .set_rate       = &omap3_noncore_dpll_set_rate,
295 };
296
297 /*
298  * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
299  * and ALT_CLK1/2)
300  */
301 static const struct clksel dpll_mpu_m2_div[] = {
302         { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
303         { .parent = NULL },
304 };
305
306 static struct clk dpll_mpu_m2_ck = {
307         .name           = "dpll_mpu_m2_ck",
308         .parent         = &dpll_mpu_ck,
309         .clksel         = dpll_mpu_m2_div,
310         .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_MPU,
311         .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
312         .ops            = &clkops_null,
313         .recalc         = &omap2_clksel_recalc,
314         .round_rate     = &omap2_clksel_round_rate,
315         .set_rate       = &omap2_clksel_set_rate,
316 };
317
318 static struct clk mpu_fck = {
319         .name           = "mpu_fck",
320         .clkdm_name     = "mpu_clkdm",
321         .parent         = &dpll_mpu_m2_ck,
322         .ops            = &clkops_omap2_dflt,
323         .enable_reg     = AM33XX_CM_MPU_MPU_CLKCTRL,
324         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
325         .recalc         = &followparent_recalc,
326         .flags          = ENABLE_ON_INIT,
327 };
328
329 /* DPLL_DDR */
330 static struct dpll_data dpll_ddr_dd = {
331         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_DDR,
332         .clk_bypass     = &sys_clkin_ck,
333         .clk_ref        = &sys_clkin_ck,
334         .control_reg    = AM33XX_CM_CLKMODE_DPLL_DDR,
335         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
336         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DDR,
337         .mult_mask      = AM33XX_DPLL_MULT_MASK,
338         .div1_mask      = AM33XX_DPLL_DIV_MASK,
339         .enable_mask    = AM33XX_DPLL_EN_MASK,
340         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
341         .max_multiplier = AM33XX_MAX_DPLL_MULT,
342         .max_divider    = AM33XX_MAX_DPLL_DIV,
343         .min_divider    = 1,
344 };
345
346 /* CLKOUT: fdpll/M2 */
347 static struct clk dpll_ddr_ck = {
348         .name           = "dpll_ddr_ck",
349         .parent         = &sys_clkin_ck,
350         .dpll_data      = &dpll_ddr_dd,
351         .init           = &omap2_init_dpll_parent,
352         .ops            = &clkops_null,
353         .recalc         = &omap3_dpll_recalc,
354 };
355
356 /*
357  * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
358  * and ALT_CLK1/2)
359  */
360 static const struct clksel dpll_ddr_m2_div[] = {
361         { .parent = &dpll_ddr_ck, .rates = div31_1to31_rates },
362         { .parent = NULL },
363 };
364
365 static struct clk dpll_ddr_m2_ck = {
366         .name           = "dpll_ddr_m2_ck",
367         .parent         = &dpll_ddr_ck,
368         .clksel         = dpll_ddr_m2_div,
369         .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_DDR,
370         .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
371         .ops            = &clkops_null,
372         .recalc         = &omap2_clksel_recalc,
373         .round_rate     = &omap2_clksel_round_rate,
374         .set_rate       = &omap2_clksel_set_rate,
375 };
376
377 static struct clk ddr_pll_clk = {
378         .name           = "ddr_pll_clk",
379         .parent         = &dpll_ddr_m2_ck,
380         .ops            = &clkops_null,
381         .recalc         = &followparent_recalc,
382 };
383
384 static struct clk emif_fck = {
385         .name           = "emif_fck",
386         .clkdm_name     = "l3_clkdm",
387         .parent         = &ddr_pll_clk,
388         .ops            = &clkops_omap2_dflt,
389         .enable_reg     = AM33XX_CM_PER_EMIF_CLKCTRL,
390         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
391         .fixed_div      = 2,
392         .recalc         = &omap_fixed_divisor_recalc,
393         .flags          = ENABLE_ON_INIT,
394 };
395
396 /* DPLL_DISP */
397 static struct dpll_data dpll_disp_dd = {
398         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_DISP,
399         .clk_bypass     = &sys_clkin_ck,
400         .clk_ref        = &sys_clkin_ck,
401         .control_reg    = AM33XX_CM_CLKMODE_DPLL_DISP,
402         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
403         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DISP,
404         .mult_mask      = AM33XX_DPLL_MULT_MASK,
405         .div1_mask      = AM33XX_DPLL_DIV_MASK,
406         .enable_mask    = AM33XX_DPLL_EN_MASK,
407         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
408         .max_multiplier = AM33XX_MAX_DPLL_MULT,
409         .max_divider    = AM33XX_MAX_DPLL_DIV,
410         .min_divider    = 1,
411 };
412
413 /* CLKOUT: fdpll/M2 */
414 static struct clk dpll_disp_ck = {
415         .name           = "dpll_disp_ck",
416         .parent         = &sys_clkin_ck,
417         .dpll_data      = &dpll_disp_dd,
418         .init           = &omap2_init_dpll_parent,
419         .ops            = &clkops_null,
420         .recalc         = &omap3_dpll_recalc,
421         .round_rate     = &omap2_dpll_round_rate,
422         .set_rate       = &omap3_noncore_dpll_set_rate,
423 };
424
425 /*
426  * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
427  * and ALT_CLK1/2)
428  */
429 static const struct clksel dpll_disp_m2_div[] = {
430         { .parent = &dpll_disp_ck, .rates = div31_1to31_rates },
431         { .parent = NULL },
432 };
433
434 static struct clk dpll_disp_m2_ck = {
435         .name           = "dpll_disp_m2_ck",
436         .parent         = &dpll_disp_ck,
437         .clksel         = dpll_disp_m2_div,
438         .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_DISP,
439         .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
440         .ops            = &clkops_null,
441         .recalc         = &omap2_clksel_recalc,
442         .round_rate     = &omap2_clksel_round_rate,
443         .set_rate       = &omap2_clksel_set_rate,
444 };
445
446 static struct clk disp_pll_clk = {
447         .name           = "disp_pll_clk",
448         .parent         = &dpll_disp_m2_ck,
449         .ops            = &clkops_null,
450         .recalc         = &followparent_recalc,
451 };
452
453 /* DPLL_PER */
454 static struct dpll_data dpll_per_dd = {
455         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_PERIPH,
456         .clk_bypass     = &sys_clkin_ck,
457         .clk_ref        = &sys_clkin_ck,
458         .control_reg    = AM33XX_CM_CLKMODE_DPLL_PER,
459         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
460         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_PER,
461         .mult_mask      = AM33XX_DPLL_MULT_PERIPH_MASK,
462         .div1_mask      = AM33XX_DPLL_PER_DIV_MASK,
463         .enable_mask    = AM33XX_DPLL_EN_MASK,
464         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
465         .max_multiplier = AM33XX_MAX_DPLL_MULT,
466         .max_divider    = AM33XX_MAX_DPLL_DIV,
467         .min_divider    = 1,
468         .flags          = DPLL_J_TYPE,
469 };
470
471 /* CLKDCOLDO */
472 static struct clk dpll_per_ck = {
473         .name           = "dpll_per_ck",
474         .parent         = &sys_clkin_ck,
475         .dpll_data      = &dpll_per_dd,
476         .init           = &omap2_init_dpll_parent,
477         .ops            = &clkops_null,
478         .recalc         = &omap3_dpll_recalc,
479         .round_rate     = &omap2_dpll_round_rate,
480         .set_rate       = &omap3_noncore_dpll_set_rate,
481 };
482
483 /* CLKOUT: fdpll/M2 */
484 static const struct clksel dpll_per_m2_div[] = {
485         { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
486         { .parent = NULL },
487 };
488
489 static struct clk dpll_per_m2_ck = {
490         .name           = "dpll_per_m2_ck",
491         .parent         = &dpll_per_ck,
492         .clksel         = dpll_per_m2_div,
493         .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_PER,
494         .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
495         .ops            = &clkops_null,
496         .recalc         = &omap2_clksel_recalc,
497         .round_rate     = &omap2_clksel_round_rate,
498         .set_rate       = &omap2_clksel_set_rate,
499 };
500
501 static struct clk per_192mhz_clk = {
502         .name           = "per_192mhz_clk",
503         .parent         = &dpll_per_m2_ck,
504         .ops            = &clkops_null,
505         .recalc         = &followparent_recalc,
506 };
507
508 static struct clk usb_pll_clk = {
509         .name           = "usb_pll_clk",
510         .parent         = &dpll_per_ck,
511         .ops            = &clkops_null,
512         .recalc         = &followparent_recalc,
513 };
514
515 static struct clk core_100mhz_ck = {
516         .name           = "core_100mhz_ck",
517         .parent         = &sysclk1_ck,
518         .ops            = &clkops_null,
519         .fixed_div      = 2,
520         .recalc         = &omap_fixed_divisor_recalc,
521 };
522
523 static struct clk l3_aon_gclk = {
524         .name           = "l3_aon_gclk",
525         .parent         = &sysclk1_ck,
526         .ops            = &clkops_null,
527         .recalc         = &followparent_recalc,
528 };
529
530 static struct clk l4_wkup_aon_gclk = {
531         .name           = "l4_wkup_aon_gclk",
532         .clkdm_name     = "l4_wkup_aon_clkdm",
533         .parent         = &sysclk1_ck,
534         .enable_reg     = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL,
535         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
536         .ops            = &clkops_null,
537         .fixed_div      = 2,
538         .recalc         = &followparent_recalc,
539 };
540
541 static struct clk l3_gclk = {
542         .name           = "l3_gclk",
543         .parent         = &sysclk1_ck,
544         .ops            = &clkops_null,
545         .recalc         = &followparent_recalc,
546 };
547
548 static struct clk l3_ick = {
549         .name           = "l3_ick",
550         .clkdm_name     = "l3_clkdm",
551         .parent         = &l3_gclk,
552         .enable_reg     = AM33XX_CM_PER_L3_CLKCTRL,
553         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
554         .flags          = ENABLE_ON_INIT,
555         .ops            = &clkops_omap2_dflt,
556         .recalc         = &followparent_recalc,
557 };
558
559 static struct clk l3_instr_ick = {
560         .name           = "l3_instr_ick",
561         .clkdm_name     = "l3_clkdm",
562         .parent         = &l3_gclk,
563         .enable_reg     = AM33XX_CM_PER_L3_INSTR_CLKCTRL,
564         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
565         .flags          = ENABLE_ON_INIT,
566         .ops            = &clkops_omap2_dflt,
567         .recalc         = &followparent_recalc,
568 };
569
570 static struct clk l4_wkup_gclk = {
571         .name           = "l4_wkup_gclk",
572         .parent         = &sysclk1_ck,
573         .ops            = &clkops_null,
574         .fixed_div      = 2,
575         .recalc         = &omap_fixed_divisor_recalc,
576 };
577
578 static struct clk l4hs_gclk = {
579         .name           = "l4hs_gclk",
580         .parent         = &sysclk1_ck,
581         .ops            = &clkops_null,
582         .recalc         = &followparent_recalc,
583 };
584
585 static struct clk gfx_l3_gclk = {
586         .name           = "gfx_l3_gclk",
587         .clkdm_name     = "gfx_l3_clkdm",
588         .parent         = &sysclk1_ck,
589         .ops            = &clkops_null,
590         .recalc         = &followparent_recalc,
591 };
592
593 static struct clk debug_clka_gclk = {
594         .name           = "debug_clka_gclk",
595         .parent         = &sysclk1_ck,
596         .ops            = &clkops_null,
597         .recalc         = &followparent_recalc,
598 };
599
600 static struct clk l4_rtc_gclk = {
601         .name           = "l4_rtc_gclk",
602         .parent         = &sysclk1_ck,
603         .ops            = &clkops_null,
604         .fixed_div      = 2,
605         .recalc         = &omap_fixed_divisor_recalc,
606 };
607
608 static struct clk rtc_ick = {
609         .name           = "rtc_ick",
610         .parent         = &l4_rtc_gclk,
611         .ops            = &clkops_null,
612         .recalc         = &followparent_recalc,
613 };
614
615 static struct clk l3s_gclk = {
616         .name           = "l3s_gclk",
617         .parent         = &core_100mhz_ck,
618         .ops            = &clkops_null,
619         .recalc         = &followparent_recalc,
620 };
621
622 static struct clk l4fw_gclk = {
623         .name           = "l4fw_gclk",
624         .parent         = &core_100mhz_ck,
625         .ops            = &clkops_null,
626         .recalc         = &followparent_recalc,
627 };
628
629 static struct clk l4ls_gclk = {
630         .name           = "l4ls_gclk",
631         .clkdm_name     = "l4ls_clkdm",
632         .parent         = &core_100mhz_ck,
633         .enable_reg     = AM33XX_CM_PER_L4LS_CLKCTRL,
634         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
635         .ops            = &clkops_omap2_dflt,
636         .recalc         = &followparent_recalc,
637 };
638
639 static struct clk clk_24mhz = {
640         .name           = "clk_24mhz",
641         .parent         = &per_192mhz_clk,
642         .fixed_div      = 8,
643         .ops            = &clkops_null,
644         .recalc         = &omap_fixed_divisor_recalc,
645 };
646
647 static struct clk l4_cefuse_gclk = {
648         .name           = "l4_cefsue_gclk",
649         .parent         = &core_100mhz_ck,
650         .ops            = &clkops_null,
651         .recalc         = &followparent_recalc,
652 };
653
654 static struct clk cefuse_iclk = {
655         .name           = "cefuse_iclk",
656         .clkdm_name     = "l4_cefuse_clkdm",
657         .parent         = &l4_cefuse_gclk,
658         .ops            = &clkops_null,
659         .recalc         = &followparent_recalc,
660 };
661
662 static struct clk cefuse_fck = {
663         .name           = "cefuse_fck",
664         .clkdm_name     = "l4_cefuse_clkdm",
665         .parent         = &sys_clkin_ck,
666         .enable_reg     = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL,
667         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
668         .ops            = &clkops_omap2_dflt,
669         .recalc         = &followparent_recalc,
670 };
671
672 static struct clk sysclk_div_ck = {
673         .name           = "sysclk_div_ck",
674         .parent         = &dpll_core_m4_ck,
675         .ops            = &clkops_null,
676         .recalc         = &followparent_recalc,
677 };
678
679 static struct clk adc_tsc_fck = {
680         .name           = "adc_tsc_fck",
681         .clkdm_name     = "l4_wkup_clkdm",
682         .parent         = &sys_clkin_ck,
683         .ops            = &clkops_null,
684         .recalc         = &followparent_recalc,
685 };
686
687 static struct clk adc_tsc_ick = {
688         .name           = "adc_tsc_ick",
689         .clkdm_name     = "l4_wkup_clkdm",
690         .parent         = &l4_wkup_gclk,
691         .enable_reg     = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL,
692         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
693         .ops            = &clkops_omap2_dflt,
694         .recalc         = &followparent_recalc,
695 };
696
697 static struct clk aes0_fck = {
698         .name           = "aes0_fck",
699         .clkdm_name     = "l3_clkdm",
700         .parent         = &l3_gclk,
701         .enable_reg     = AM33XX_CM_PER_AES0_CLKCTRL,
702         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
703         .ops            = &clkops_omap2_dflt,
704         .recalc         = &followparent_recalc,
705 };
706
707 /*
708  * clkdiv32 is generated from fixed division of 732.4219
709  */
710 static struct clk clkdiv32k_ick = {
711         .name           = "clkdiv32k_ick",
712         .clkdm_name     = "clk_24mhz_clkdm",
713         .rate           = 32768,
714         .parent         = &clk_24mhz,
715         .enable_reg     = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
716         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
717         .ops            = &clkops_omap2_dflt,
718 };
719
720 static struct clk clk_32khz_ck = {
721         .name           = "clk_32khz_ck",
722         .clkdm_name     = "clk_24mhz_clkdm",
723         .parent         = &clkdiv32k_ick,
724         .ops            = &clkops_null,
725         .recalc         = &followparent_recalc,
726 };
727
728 static struct clk control_fck = {
729         .name           = "control_fck",
730         .clkdm_name     = "l4_wkup_clkdm",
731         .parent         = &l4_wkup_gclk,
732         .enable_reg     = AM33XX_CM_WKUP_CONTROL_CLKCTRL,
733         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
734         .ops            = &clkops_omap2_dflt,
735         .recalc         = &followparent_recalc,
736 };
737
738 static struct clk dcan0_ick = {
739         .name           = "dcan0_ick",
740         .clkdm_name     = "l4ls_clkdm",
741         .parent         = &l4ls_gclk,
742         .ops            = &clkops_null,
743         .recalc         = &followparent_recalc,
744 };
745
746 static struct clk dcan0_fck = {
747         .name           = "dcan0_fck",
748         .clkdm_name     = "l4ls_clkdm",
749         .parent         = &sys_clkin_ck,
750         .enable_reg     = AM33XX_CM_PER_DCAN0_CLKCTRL,
751         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
752         .ops            = &clkops_omap2_dflt,
753         .recalc         = &followparent_recalc,
754 };
755
756 static struct clk dcan1_ick = {
757         .name           = "dcan1_ick",
758         .clkdm_name     = "l4ls_clkdm",
759         .parent         = &l4ls_gclk,
760         .ops            = &clkops_null,
761         .recalc         = &followparent_recalc,
762 };
763
764 static struct clk dcan1_fck = {
765         .name           = "dcan1_fck",
766         .clkdm_name     = "l4ls_clkdm",
767         .parent         = &sys_clkin_ck,
768         .enable_reg     = AM33XX_CM_PER_DCAN1_CLKCTRL,
769         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
770         .ops            = &clkops_omap2_dflt,
771         .recalc         = &followparent_recalc,
772 };
773
774 static struct clk debugss_ick = {
775         .name           = "debugss_ick",
776         .clkdm_name     = "l3_aon_clkdm",
777         .parent         = &l3_aon_gclk,
778         .ops            = &clkops_omap2_dflt,
779         .enable_reg     = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
780         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
781         .recalc         = &followparent_recalc,
782 };
783
784 static struct clk elm_fck = {
785         .name           = "elm_fck",
786         .clkdm_name     = "l4ls_clkdm",
787         .parent         = &l4ls_gclk,
788         .enable_reg     = AM33XX_CM_PER_ELM_CLKCTRL,
789         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
790         .ops            = &clkops_omap2_dflt,
791         .recalc         = &followparent_recalc,
792 };
793
794 static struct clk emif_fw_fck = {
795         .name           = "emif_fw_fck",
796         .clkdm_name     = "l4fw_clkdm",
797         .parent         = &l4fw_gclk,
798         .enable_reg     = AM33XX_CM_PER_EMIF_FW_CLKCTRL,
799         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
800         .ops            = &clkops_omap2_dflt,
801         .recalc         = &followparent_recalc,
802 };
803
804 static struct clk epwmss0_fck = {
805         .name           = "epwmss0_fck",
806         .clkdm_name     = "l4ls_clkdm",
807         .parent         = &l4ls_gclk,
808         .enable_reg     = AM33XX_CM_PER_EPWMSS0_CLKCTRL,
809         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
810         .ops            = &clkops_omap2_dflt,
811         .recalc         = &followparent_recalc,
812 };
813
814 static struct clk epwmss1_fck = {
815         .name           = "epwmss1_fck",
816         .clkdm_name     = "l4ls_clkdm",
817         .parent         = &l4ls_gclk,
818         .enable_reg     = AM33XX_CM_PER_EPWMSS1_CLKCTRL,
819         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
820         .ops            = &clkops_omap2_dflt,
821         .recalc         = &followparent_recalc,
822 };
823
824 static struct clk epwmss2_fck = {
825         .name           = "epwmss2_fck",
826         .clkdm_name     = "l4ls_clkdm",
827         .parent         = &l4ls_gclk,
828         .enable_reg     = AM33XX_CM_PER_EPWMSS2_CLKCTRL,
829         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
830         .ops            = &clkops_omap2_dflt,
831         .recalc         = &followparent_recalc,
832 };
833
834 static struct clk gpmc_fck = {
835         .name           = "gpmc_fck",
836         .clkdm_name     = "l3s_clkdm",
837         .parent         = &l3s_gclk,
838         .enable_reg     = AM33XX_CM_PER_GPMC_CLKCTRL,
839         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
840         .ops            = &clkops_omap2_dflt,
841         .recalc         = &followparent_recalc,
842 };
843
844 static struct clk i2c1_ick = {
845         .name           = "i2c1_ick",
846         .clkdm_name     = "l4_wkup_clkdm",
847         .parent         = &l4_wkup_gclk,
848         .ops            = &clkops_null,
849         .recalc         = &followparent_recalc,
850 };
851
852 static struct clk i2c1_fck = {
853         .name           = "i2c1_fck",
854         .clkdm_name     = "l4_wkup_clkdm",
855         .parent         = &per_192mhz_clk,
856         .enable_reg     = AM33XX_CM_WKUP_I2C0_CLKCTRL,
857         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
858         .fixed_div      = 4,
859         .ops            = &clkops_omap2_dflt,
860         .recalc         = &omap_fixed_divisor_recalc,
861 };
862
863 static struct clk i2c2_ick = {
864         .name           = "i2c2_ick",
865         .clkdm_name     = "l4ls_clkdm",
866         .parent         = &l4ls_gclk,
867         .ops            = &clkops_null,
868         .recalc         = &followparent_recalc,
869 };
870
871 static struct clk i2c2_fck = {
872         .name           = "i2c2_fck",
873         .clkdm_name     = "l4ls_clkdm",
874         .parent         = &per_192mhz_clk,
875         .enable_reg     = AM33XX_CM_PER_I2C1_CLKCTRL,
876         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
877         .fixed_div      = 4,
878         .ops            = &clkops_omap2_dflt,
879         .recalc         = &omap_fixed_divisor_recalc,
880 };
881
882 static struct clk i2c3_ick = {
883         .name           = "i2c3_ick",
884         .clkdm_name     = "l4ls_clkdm",
885         .parent         = &l4ls_gclk,
886         .ops            = &clkops_null,
887         .recalc         = &followparent_recalc,
888 };
889
890 static struct clk i2c3_fck = {
891         .name           = "i2c3_fck",
892         .parent         = &per_192mhz_clk,
893         .enable_reg     = AM33XX_CM_PER_I2C2_CLKCTRL,
894         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
895         .clkdm_name     = "l4ls_clkdm",
896         .fixed_div      = 4,
897         .ops            = &clkops_omap2_dflt,
898         .recalc         = &omap_fixed_divisor_recalc,
899 };
900
901 static struct clk ieee5000_fck = {
902         .name           = "ieee5000_fck",
903         .clkdm_name     = "l3s_clkdm",
904         .parent         = &l3s_gclk,
905         .enable_reg     = AM33XX_CM_PER_IEEE5000_CLKCTRL,
906         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
907         .ops            = &clkops_omap2_dflt,
908         .recalc         = &followparent_recalc,
909 };
910
911 static struct clk l4hs_ick = {
912         .name           = "l4hs_ick",
913         .clkdm_name     = "l4hs_clkdm",
914         .parent         = &l4hs_gclk,
915         .enable_reg     = AM33XX_CM_PER_L4HS_CLKCTRL,
916         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
917         .flags          = ENABLE_ON_INIT,
918         .ops            = &clkops_omap2_dflt,
919         .recalc         = &followparent_recalc,
920 };
921
922 static struct clk l4wkup_ick = {
923         .name           = "l4wkup_ick",
924         .clkdm_name     = "l4_wkup_aon_clkdm",
925         .parent         = &l4_wkup_aon_gclk,
926         .enable_reg     = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL,
927         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
928         .flags          = ENABLE_ON_INIT,
929         .ops            = &clkops_omap2_dflt,
930         .recalc         = &followparent_recalc,
931 };
932
933 static struct clk l4fw_ick = {
934         .name           = "l4fw_ick",
935         .clkdm_name     = "l4fw_clkdm",
936         .parent         = &core_100mhz_ck,
937         .enable_reg     = AM33XX_CM_PER_L4FW_CLKCTRL,
938         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
939         .flags          = ENABLE_ON_INIT,
940         .ops            = &clkops_omap2_dflt,
941         .recalc         = &followparent_recalc,
942 };
943
944 static struct clk l4ls_ick = {
945         .name           = "l4ls_ick",
946         .clkdm_name     = "l4ls_clkdm",
947         .parent         = &l4ls_gclk,
948         .enable_reg     = AM33XX_CM_PER_L4LS_CLKCTRL,
949         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
950         .flags          = ENABLE_ON_INIT,
951         .ops            = &clkops_omap2_dflt,
952         .recalc         = &followparent_recalc,
953 };
954
955 static struct clk mailbox0_fck = {
956         .name           = "mailbox0_fck",
957         .clkdm_name     = "l4ls_clkdm",
958         .parent         = &l4ls_gclk,
959         .enable_reg     = AM33XX_CM_PER_MAILBOX0_CLKCTRL,
960         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
961         .ops            = &clkops_omap2_dflt,
962         .recalc         = &followparent_recalc,
963 };
964
965 static struct clk mcasp0_ick = {
966         .name           = "mcasp0_ick",
967         .parent         = &l3s_gclk,
968         .ops            = &clkops_null,
969         .recalc         = &followparent_recalc,
970 };
971
972 static struct clk mcasp0_fck = {
973         .name           = "mcasp0_fck",
974         .clkdm_name     = "l3s_clkdm",
975         .parent         = &sys_clkin_ck,
976         .enable_reg     = AM33XX_CM_PER_MCASP0_CLKCTRL,
977         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
978         .ops            = &clkops_omap2_dflt,
979         .recalc         = &followparent_recalc,
980 };
981
982 static struct clk mcasp1_ick = {
983         .name           = "mcasp1_ick",
984         .parent         = &l3s_gclk,
985         .ops            = &clkops_null,
986         .recalc         = &followparent_recalc,
987 };
988
989 static struct clk mcasp1_fck = {
990         .name           = "mcasp1_fck",
991         .clkdm_name     = "l3s_clkdm",
992         .parent         = &sys_clkin_ck,
993         .enable_reg     = AM33XX_CM_PER_MCASP1_CLKCTRL,
994         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
995         .ops            = &clkops_omap2_dflt,
996         .recalc         = &followparent_recalc,
997 };
998
999 static struct clk mlb_fck = {
1000         .name           = "mlb_fck",
1001         .ops            = &clkops_omap2_dflt,
1002         .enable_reg     = AM33XX_CM_PER_MLB_CLKCTRL,
1003         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1004         .clkdm_name     = "l3_clkdm",
1005         .parent         = &sysclk_div_ck,
1006         .recalc         = &followparent_recalc,
1007 };
1008
1009 static struct clk mmu_fck = {
1010         .name           = "mmu_fck",
1011         .clkdm_name     = "gfx_l3_clkdm",
1012         .parent         = &gfx_l3_gclk,
1013         .ops            = &clkops_omap2_dflt,
1014         .enable_reg     = AM33XX_CM_GFX_MMUDATA_CLKCTRL,
1015         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1016         .recalc         = &followparent_recalc,
1017 };
1018
1019 static struct clk ocmcram_ick = {
1020         .name           = "ocmcram_ick",
1021         .clkdm_name     = "l3_clkdm",
1022         .parent         = &l3_gclk,
1023         .enable_reg     = AM33XX_CM_PER_OCMCRAM_CLKCTRL,
1024         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1025         .ops            = &clkops_omap2_dflt,
1026         .recalc         = &followparent_recalc,
1027 };
1028
1029 static struct clk ocpwp_fck = {
1030         .name           = "ocpwp_fck",
1031         .clkdm_name     = "l4ls_clkdm",
1032         .parent         = &l4ls_gclk,
1033         .enable_reg     = AM33XX_CM_PER_OCPWP_CLKCTRL,
1034         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1035         .ops            = &clkops_omap2_dflt,
1036         .recalc         = &followparent_recalc,
1037 };
1038
1039 static struct clk pka_fck = {
1040         .name           = "pka_fck",
1041         .clkdm_name     = "l4ls_clkdm",
1042         .parent         = &l4ls_gclk,
1043         .enable_reg     = AM33XX_CM_PER_PKA_CLKCTRL,
1044         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1045         .ops            = &clkops_omap2_dflt,
1046         .recalc         = &followparent_recalc,
1047 };
1048
1049 static struct clk rng_fck = {
1050         .name           = "rng_fck",
1051         .clkdm_name     = "l4ls_clkdm",
1052         .parent         = &l4ls_gclk,
1053         .enable_reg     = AM33XX_CM_PER_RNG_CLKCTRL,
1054         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1055         .ops            = &clkops_omap2_dflt,
1056         .recalc         = &followparent_recalc,
1057 };
1058
1059 static struct clk rtc_fck = {
1060         .name           = "rtc_fck",
1061         .clkdm_name     = "l4_rtc_clkdm",
1062         .parent         = &clk_32768_ck,
1063         .enable_reg     = AM33XX_CM_RTC_RTC_CLKCTRL,
1064         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1065         .ops            = &clkops_omap2_dflt,
1066         .recalc         = &followparent_recalc,
1067 };
1068
1069 static struct clk sha0_fck = {
1070         .name           = "sha0_fck",
1071         .clkdm_name     = "l3_clkdm",
1072         .parent         = &l3_gclk,
1073         .enable_reg     = AM33XX_CM_PER_SHA0_CLKCTRL,
1074         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1075         .ops            = &clkops_omap2_dflt,
1076         .recalc         = &followparent_recalc,
1077 };
1078
1079 static struct clk smartreflex0_ick = {
1080         .name           = "smartreflex0_ick",
1081         .parent         = &l4_wkup_gclk,
1082         .ops            = &clkops_null,
1083         .recalc         = &followparent_recalc,
1084 };
1085
1086 static struct clk smartreflex0_fck = {
1087         .name           = "smartreflex0_fck",
1088         .clkdm_name     = "l4_wkup_clkdm",
1089         .parent         = &sys_clkin_ck,
1090         .enable_reg     = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL,
1091         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1092         .ops            = &clkops_omap2_dflt,
1093         .recalc         = &followparent_recalc,
1094 };
1095
1096 static struct clk smartreflex1_ick = {
1097         .name           = "smartreflex1_ick",
1098         .parent         = &l4_wkup_gclk,
1099         .ops            = &clkops_null,
1100         .recalc         = &followparent_recalc,
1101 };
1102
1103 static struct clk smartreflex1_fck = {
1104         .name           = "smartreflex1_fck",
1105         .clkdm_name     = "l4_wkup_clkdm",
1106         .parent         = &sys_clkin_ck,
1107         .enable_reg     = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL,
1108         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1109         .ops            = &clkops_omap2_dflt,
1110         .recalc         = &followparent_recalc,
1111 };
1112
1113 static struct clk spi0_ick = {
1114         .name           = "spi0_ick",
1115         .parent         = &l4ls_gclk,
1116         .ops            = &clkops_null,
1117         .recalc         = &followparent_recalc,
1118 };
1119
1120 static struct clk spi0_fck = {
1121         .name           = "spi0_fck",
1122         .clkdm_name     = "l4ls_clkdm",
1123         .parent         = &per_192mhz_clk,
1124         .enable_reg     = AM33XX_CM_PER_SPI0_CLKCTRL,
1125         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1126         .fixed_div      = 4,
1127         .ops            = &clkops_omap2_dflt,
1128         .recalc         = &omap_fixed_divisor_recalc,
1129 };
1130
1131 static struct clk spi1_ick = {
1132         .name           = "spi1_ick",
1133         .parent         = &l4ls_gclk,
1134         .ops            = &clkops_null,
1135         .recalc         = &followparent_recalc,
1136 };
1137
1138 static struct clk spi1_fck = {
1139         .name           = "spi1_fck",
1140         .clkdm_name     = "l4ls_clkdm",
1141         .parent         = &per_192mhz_clk,
1142         .enable_reg     = AM33XX_CM_PER_SPI1_CLKCTRL,
1143         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1144         .fixed_div      = 4,
1145         .ops            = &clkops_omap2_dflt,
1146         .recalc         = &omap_fixed_divisor_recalc,
1147 };
1148
1149 static struct clk spinlock_fck = {
1150         .name           = "spinlock_fck",
1151         .clkdm_name     = "l4ls_clkdm",
1152         .parent         = &l4ls_gclk,
1153         .enable_reg     = AM33XX_CM_PER_SPINLOCK_CLKCTRL,
1154         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1155         .ops            = &clkops_omap2_dflt,
1156         .recalc         = &followparent_recalc,
1157 };
1158
1159 static struct clk clk_32khz_timer = {
1160         .name           = "clk_32khz_timer",
1161         .parent         = &clk_32khz_ck,
1162         .ops            = &clkops_null,
1163         .recalc         = &followparent_recalc,
1164 };
1165
1166 /* Timers */
1167
1168 /* Secure Timer: Used only to disable the clocks and for completeness */
1169 static const struct clksel timer0_clkmux_sel[] = {
1170         { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
1171         { .parent = &clk_32khz_ck, .rates = div_1_1_rates },
1172         { .parent = &sys_clkin_ck, .rates = div_1_2_rates },
1173         { .parent = &tclkin_ck, .rates = div_1_3_rates },
1174         { .parent = NULL },
1175 };
1176
1177 static struct clk timer0_ick = {
1178         .name           = "timer0_ick",
1179         .parent         = &l4_wkup_gclk,
1180         .ops            = &clkops_null,
1181         .recalc         = &followparent_recalc,
1182 };
1183
1184 static struct clk timer0_fck = {
1185         .name           = "timer0_fck",
1186         .clkdm_name     = "l4_wkup_clkdm",
1187         .parent         = &clk_rc32k_ck,
1188         .clksel         = timer0_clkmux_sel,
1189         .enable_reg     = AM33XX_CM_WKUP_TIMER0_CLKCTRL,
1190         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1191         .clksel_reg     = AM33XX_CTRL_REGADDR(0x01BC),
1192         .clksel_mask    = (0x3 << 4),
1193         .ops            = &clkops_omap2_dflt,
1194         .recalc         = &followparent_recalc,
1195 };
1196
1197 static const struct clksel timer1_clkmux_sel[] = {
1198         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1199         { .parent = &clk_32khz_ck, .rates = div_1_1_rates },
1200         { .parent = &tclkin_ck, .rates = div_1_2_rates },
1201         { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
1202         { .parent = &clk_32768_ck, .rates = div_1_4_rates },
1203         { .parent = NULL },
1204 };
1205
1206 static struct clk timer1_ick = {
1207         .name           = "timer1_ick",
1208         .parent         = &l4_wkup_gclk,
1209         .ops            = &clkops_null,
1210         .recalc         = &followparent_recalc,
1211 };
1212
1213 static struct clk timer1_fck = {
1214         .name           = "timer1_fck",
1215         .clkdm_name     = "l4ls_clkdm",
1216         .parent         = &sys_clkin_ck,
1217         .init           = &omap2_init_clksel_parent,
1218         .clksel         = timer1_clkmux_sel,
1219         .enable_reg     = AM33XX_CM_WKUP_TIMER1_CLKCTRL,
1220         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1221         .clksel_reg     = AM33XX_CLKSEL_TIMER1MS_CLK,
1222         .clksel_mask    = AM33XX_CLKSEL_0_2_MASK,
1223         .ops            = &clkops_omap2_dflt,
1224         .recalc         = &omap2_clksel_recalc,
1225 };
1226
1227 static const struct clksel timer2_to_7_clk_sel[] = {
1228         { .parent = &tclkin_ck, .rates = div_1_0_rates },
1229         { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
1230         { .parent = &clk_32khz_timer, .rates = div_1_2_rates },
1231         { .parent = NULL },
1232 };
1233
1234 static struct clk timer2_ick = {
1235         .name           = "timer2_ick",
1236         .parent         = &l4ls_gclk,
1237         .ops            = &clkops_null,
1238         .recalc         = &followparent_recalc,
1239 };
1240
1241 static struct clk timer2_fck = {
1242         .name           = "timer2_fck",
1243         .clkdm_name     = "l4ls_clkdm",
1244         .parent         = &sys_clkin_ck,
1245         .init           = &omap2_init_clksel_parent,
1246         .clksel         = timer2_to_7_clk_sel,
1247         .enable_reg     = AM33XX_CM_PER_TIMER2_CLKCTRL,
1248         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1249         .clksel_reg     = AM33XX_CLKSEL_TIMER2_CLK,
1250         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
1251         .ops            = &clkops_omap2_dflt,
1252         .recalc         = &omap2_clksel_recalc,
1253 };
1254
1255 static struct clk timer3_ick = {
1256         .name           = "timer3_ick",
1257         .parent         = &l4ls_gclk,
1258         .ops            = &clkops_null,
1259         .recalc         = &followparent_recalc,
1260 };
1261
1262 static struct clk timer3_fck = {
1263         .name           = "timer3_fck",
1264         .clkdm_name     = "l4ls_clkdm",
1265         .parent         = &sys_clkin_ck,
1266         .init           = &am33xx_init_timer_parent,
1267         .clksel         = timer2_to_7_clk_sel,
1268         .enable_reg     = AM33XX_CM_PER_TIMER3_CLKCTRL,
1269         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1270         .clksel_reg     = AM33XX_CLKSEL_TIMER3_CLK,
1271         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
1272         .ops            = &clkops_omap2_dflt,
1273         .recalc         = &omap2_clksel_recalc,
1274 };
1275
1276 static struct clk timer4_ick = {
1277         .name           = "timer4_ick",
1278         .parent         = &l4ls_gclk,
1279         .ops            = &clkops_null,
1280         .recalc         = &followparent_recalc,
1281 };
1282
1283 static struct clk timer4_fck = {
1284         .name           = "timer4_fck",
1285         .clkdm_name     = "l4ls_clkdm",
1286         .parent         = &sys_clkin_ck,
1287         .init           = &omap2_init_clksel_parent,
1288         .clksel         = timer2_to_7_clk_sel,
1289         .enable_reg     = AM33XX_CM_PER_TIMER4_CLKCTRL,
1290         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1291         .clksel_reg     = AM33XX_CLKSEL_TIMER4_CLK,
1292         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
1293         .ops            = &clkops_omap2_dflt,
1294         .recalc         = &omap2_clksel_recalc,
1295 };
1296
1297 static struct clk timer5_ick = {
1298         .name           = "timer5_ick",
1299         .parent         = &l4ls_gclk,
1300         .ops            = &clkops_null,
1301         .recalc         = &followparent_recalc,
1302 };
1303
1304 static struct clk timer5_fck = {
1305         .name           = "timer5_fck",
1306         .clkdm_name     = "l4ls_clkdm",
1307         .parent         = &sys_clkin_ck,
1308         .init           = &omap2_init_clksel_parent,
1309         .clksel         = timer2_to_7_clk_sel,
1310         .enable_reg     = AM33XX_CM_PER_TIMER5_CLKCTRL,
1311         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1312         .clksel_reg     = AM33XX_CLKSEL_TIMER5_CLK,
1313         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
1314         .ops            = &clkops_omap2_dflt,
1315         .recalc         = &omap2_clksel_recalc,
1316 };
1317
1318 static struct clk timer6_ick = {
1319         .name           = "timer6_ick",
1320         .parent         = &l4ls_gclk,
1321         .ops            = &clkops_null,
1322         .recalc         = &followparent_recalc,
1323 };
1324
1325 static struct clk timer6_fck = {
1326         .name           = "timer6_fck",
1327         .clkdm_name     = "l4ls_clkdm",
1328         .parent         = &sys_clkin_ck,
1329         .init           = &am33xx_init_timer_parent,
1330         .clksel         = timer2_to_7_clk_sel,
1331         .enable_reg     = AM33XX_CM_PER_TIMER6_CLKCTRL,
1332         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1333         .clksel_reg     = AM33XX_CLKSEL_TIMER6_CLK,
1334         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
1335         .ops            = &clkops_omap2_dflt,
1336         .recalc         = &omap2_clksel_recalc,
1337 };
1338
1339 static struct clk timer7_ick = {
1340         .name           = "timer7_ick",
1341         .parent         = &l4ls_gclk,
1342         .ops            = &clkops_null,
1343         .recalc         = &followparent_recalc,
1344 };
1345
1346 static struct clk timer7_fck = {
1347         .name           = "timer7_fck",
1348         .clkdm_name     = "l4ls_clkdm",
1349         .parent         = &sys_clkin_ck,
1350         .init           = &omap2_init_clksel_parent,
1351         .clksel         = timer2_to_7_clk_sel,
1352         .enable_reg     = AM33XX_CM_PER_TIMER7_CLKCTRL,
1353         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1354         .clksel_reg     = AM33XX_CLKSEL_TIMER7_CLK,
1355         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
1356         .ops            = &clkops_omap2_dflt,
1357         .recalc         = &omap2_clksel_recalc,
1358 };
1359
1360 static struct clk tpcc_ick = {
1361         .name           = "tpcc_ick",
1362         .clkdm_name     = "l3_clkdm",
1363         .parent         = &l3_gclk,
1364         .enable_reg     = AM33XX_CM_PER_TPCC_CLKCTRL,
1365         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1366         .ops            = &clkops_omap2_dflt,
1367         .recalc         = &followparent_recalc,
1368 };
1369
1370 static struct clk tptc0_ick = {
1371         .name           = "tptc0_ick",
1372         .parent         = &l3_gclk,
1373         .clkdm_name     = "l3_clkdm",
1374         .enable_reg     = AM33XX_CM_PER_TPTC0_CLKCTRL,
1375         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1376         .ops            = &clkops_omap2_dflt,
1377         .recalc         = &followparent_recalc,
1378 };
1379
1380 static struct clk tptc1_ick = {
1381         .name           = "tptc1_ick",
1382         .clkdm_name     = "l3_clkdm",
1383         .parent         = &l3_gclk,
1384         .enable_reg     = AM33XX_CM_PER_TPTC1_CLKCTRL,
1385         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1386         .ops            = &clkops_omap2_dflt,
1387         .recalc         = &followparent_recalc,
1388 };
1389
1390 static struct clk tptc2_ick = {
1391         .name           = "tptc2_ick",
1392         .clkdm_name     = "l3_clkdm",
1393         .parent         = &l3_gclk,
1394         .enable_reg     = AM33XX_CM_PER_TPTC2_CLKCTRL,
1395         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1396         .ops            = &clkops_omap2_dflt,
1397         .recalc         = &followparent_recalc,
1398 };
1399
1400 static struct clk uart1_ick = {
1401         .name           = "uart1_ick",
1402         .parent         = &l4_wkup_gclk,
1403         .ops            = &clkops_null,
1404         .recalc         = &followparent_recalc,
1405 };
1406
1407 static struct clk uart1_fck = {
1408         .name           = "uart1_fck",
1409         .clkdm_name     = "l4_wkup_clkdm",
1410         .parent         = &per_192mhz_clk,
1411         .enable_reg     = AM33XX_CM_WKUP_UART0_CLKCTRL,
1412         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1413         .fixed_div      = 4,
1414         .ops            = &clkops_omap2_dflt,
1415         .recalc         = &omap_fixed_divisor_recalc,
1416 };
1417
1418 static struct clk uart2_ick = {
1419         .name           = "uart2_ick",
1420         .parent         = &l4ls_gclk,
1421         .ops            = &clkops_null,
1422         .recalc         = &followparent_recalc,
1423 };
1424
1425 static struct clk uart2_fck = {
1426         .name           = "uart2_fck",
1427         .clkdm_name     = "l4ls_clkdm",
1428         .parent         = &per_192mhz_clk,
1429         .enable_reg     = AM33XX_CM_PER_UART1_CLKCTRL,
1430         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1431         .fixed_div      = 4,
1432         .ops            = &clkops_omap2_dflt,
1433         .recalc         = &omap_fixed_divisor_recalc,
1434 };
1435
1436 static struct clk uart3_ick = {
1437         .name           = "uart3_ick",
1438         .parent         = &l4ls_gclk,
1439         .ops            = &clkops_null,
1440         .recalc         = &followparent_recalc,
1441 };
1442
1443 static struct clk uart3_fck = {
1444         .name           = "uart3_fck",
1445         .clkdm_name     = "l4ls_clkdm",
1446         .parent         = &per_192mhz_clk,
1447         .enable_reg     = AM33XX_CM_PER_UART2_CLKCTRL,
1448         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1449         .fixed_div      = 4,
1450         .ops            = &clkops_omap2_dflt,
1451         .recalc         = &omap_fixed_divisor_recalc,
1452 };
1453
1454 static struct clk uart4_ick = {
1455         .name           = "uart4_ick",
1456         .parent         = &l4ls_gclk,
1457         .ops            = &clkops_null,
1458         .recalc         = &followparent_recalc,
1459 };
1460
1461 static struct clk uart4_fck = {
1462         .name           = "uart4_fck",
1463         .clkdm_name     = "l4ls_clkdm",
1464         .parent         = &per_192mhz_clk,
1465         .enable_reg     = AM33XX_CM_PER_UART3_CLKCTRL,
1466         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1467         .fixed_div      = 4,
1468         .ops            = &clkops_omap2_dflt,
1469         .recalc         = &omap_fixed_divisor_recalc,
1470 };
1471
1472 static struct clk uart5_ick = {
1473         .name           = "uart5_ick",
1474         .parent         = &l4ls_gclk,
1475         .ops            = &clkops_null,
1476         .recalc         = &followparent_recalc,
1477 };
1478
1479 static struct clk uart5_fck = {
1480         .name           = "uart5_fck",
1481         .clkdm_name     = "l4ls_clkdm",
1482         .parent         = &per_192mhz_clk,
1483         .enable_reg     = AM33XX_CM_PER_UART4_CLKCTRL,
1484         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1485         .fixed_div      = 4,
1486         .ops            = &clkops_omap2_dflt,
1487         .recalc         = &omap_fixed_divisor_recalc,
1488 };
1489
1490 static struct clk uart6_ick = {
1491         .name           = "uart6_ick",
1492         .parent         = &l4ls_gclk,
1493         .ops            = &clkops_null,
1494         .recalc         = &followparent_recalc,
1495 };
1496
1497 static struct clk uart6_fck = {
1498         .name           = "uart6_fck",
1499         .clkdm_name     = "l4ls_clkdm",
1500         .parent         = &per_192mhz_clk,
1501         .enable_reg     = AM33XX_CM_PER_UART5_CLKCTRL,
1502         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1503         .fixed_div      = 4,
1504         .ops            = &clkops_omap2_dflt,
1505         .recalc         = &omap_fixed_divisor_recalc,
1506 };
1507
1508 static struct clk wkup_m3_fck = {
1509         .name           = "wkup_m3_fck",
1510         .clkdm_name     = "l4_wkup_aon_clkdm",
1511         .parent         = &l4_wkup_aon_gclk,
1512         .enable_reg     = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL,
1513         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1514         .ops            = &clkops_omap2_dflt,
1515         .recalc         = &followparent_recalc,
1516 };
1517
1518 static struct clk cpsw_250mhz_clk = {
1519         .name           = "cpsw_250mhz_clk",
1520         .clkdm_name     = "l4hs_clkdm",
1521         .parent         = &sysclk2_ck,
1522         .ops            = &clkops_null,
1523         .recalc         = &followparent_recalc,
1524 };
1525
1526 static struct clk cpsw_125mhz_gclk = {
1527         .name           = "cpsw_125mhz_gclk",
1528         .clkdm_name     = "cpsw_125mhz_clkdm",
1529         .parent         = &sysclk2_ck,
1530         .ops            = &clkops_null,
1531         .fixed_div      = 2,
1532         .recalc         = &omap_fixed_divisor_recalc,
1533 };
1534
1535 /*
1536  * TODO: As per clock tree @OPP50 /2 is used, but there is not register
1537  * to configure this. @ normal OPP, /5 is used - 250MHz/5 = 50MHz
1538  */
1539 static struct clk cpsw_50mhz_clk = {
1540         .name           = "cpsw_50mhz_clk",
1541         .clkdm_name     = "l4hs_clkdm",
1542         .parent         = &sysclk2_ck,
1543         .ops            = &clkops_null,
1544         .fixed_div      = 5,
1545         .recalc         = &omap_fixed_divisor_recalc,
1546 };
1547
1548 static struct clk cpsw_5mhz_clk = {
1549         .name           = "cpsw_5mhz_clk",
1550         .clkdm_name     = "l4hs_clkdm",
1551         .parent         = &cpsw_50mhz_clk,
1552         .ops            = &clkops_null,
1553         .fixed_div      = 10,
1554         .recalc         = &omap_fixed_divisor_recalc,
1555 };
1556
1557 static struct clk cpgmac0_ick = {
1558         .name           = "cpgmac0_ick",
1559         .clkdm_name     = "cpsw_125mhz_clkdm",
1560         .ops            = &clkops_omap2_dflt,
1561         .enable_reg     = AM33XX_CM_PER_CPGMAC0_CLKCTRL,
1562         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1563         .parent         = &cpsw_125mhz_gclk,
1564         .recalc         = &followparent_recalc,
1565 };
1566
1567 static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
1568         { .parent = &sysclk2_ck, .rates = div_1_0_rates },
1569         { .parent = &sysclk1_ck, .rates = div_1_1_rates },
1570         { .parent = NULL },
1571 };
1572
1573 static struct clk cpsw_cpts_rft_clk = {
1574         .name           = "cpsw_cpts_rft_clk",
1575         .clkdm_name     = "l3_clkdm",
1576         .parent         = &sysclk2_ck,
1577         .clksel         = cpsw_cpts_rft_clkmux_sel,
1578         .clksel_reg     = AM33XX_CM_CPTS_RFT_CLKSEL,
1579         .clksel_mask    = AM33XX_CLKSEL_0_0_MASK,
1580         .ops            = &clkops_null,
1581         .recalc         = &followparent_recalc,
1582 };
1583
1584 static struct clk usbotg_ick = {
1585         .name           = "usbotg_ick",
1586         .clkdm_name     = "l3s_clkdm",
1587         .parent         = &l3s_gclk,
1588         .ops            = &clkops_omap2_dflt,
1589         .enable_reg     = AM33XX_CM_PER_USB0_CLKCTRL,
1590         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1591         .recalc         = &followparent_recalc,
1592 };
1593
1594 static struct clk usbotg_fck = {
1595         .name           = "usbotg_fck",
1596         .clkdm_name     = "l3s_clkdm",
1597         .parent         = &usb_pll_clk,
1598         .enable_reg     = AM33XX_CM_CLKDCOLDO_DPLL_PER,
1599         .enable_bit     = AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
1600         .ops            = &clkops_omap2_dflt,
1601         .recalc         = &followparent_recalc,
1602 };
1603
1604 /* gpio */
1605 static const struct clksel gpio0_dbclk_mux_sel[] = {
1606         { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
1607         { .parent = &clk_32768_ck, .rates = div_1_1_rates },
1608         { .parent = &clk_32khz_timer, .rates = div_1_2_rates },
1609         { .parent = NULL },
1610 };
1611
1612 static struct clk gpio0_dbclk_mux_ck = {
1613         .name           = "gpio0_dbclk_mux_ck",
1614         .clkdm_name     = "l4_wkup_clkdm",
1615         .parent         = &clk_rc32k_ck,
1616         .init           = &omap2_init_clksel_parent,
1617         .clksel         = gpio0_dbclk_mux_sel,
1618         .clksel_reg     = AM33XX_CLKSEL_GPIO0_DBCLK,
1619         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
1620         .ops            = &clkops_null,
1621         .recalc         = &omap2_clksel_recalc,
1622 };
1623
1624 static struct clk gpio0_dbclk = {
1625         .name           = "gpio0_dbclk",
1626         .clkdm_name     = "l4_wkup_clkdm",
1627         .parent         = &gpio0_dbclk_mux_ck,
1628         .enable_reg     = AM33XX_CM_WKUP_GPIO0_CLKCTRL,
1629         .enable_bit     = AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT,
1630         .ops            = &clkops_omap2_dflt,
1631         .recalc         = &followparent_recalc,
1632 };
1633
1634 static struct clk gpio0_ick = {
1635         .name           = "gpio0_ick",
1636         .clkdm_name     = "l4_wkup_clkdm",
1637         .parent         = &l4_wkup_gclk,
1638         .enable_reg     = AM33XX_CM_WKUP_GPIO0_CLKCTRL,
1639         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1640         .ops            = &clkops_omap2_dflt,
1641         .recalc         = &followparent_recalc,
1642 };
1643
1644 static struct clk gpio1_dbclk = {
1645         .name           = "gpio1_dbclk",
1646         .clkdm_name     = "l4ls_clkdm",
1647         .parent         = &clkdiv32k_ick,
1648         .enable_reg     = AM33XX_CM_PER_GPIO1_CLKCTRL,
1649         .enable_bit     = AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT,
1650         .ops            = &clkops_omap2_dflt,
1651         .recalc         = &followparent_recalc,
1652 };
1653
1654 static struct clk gpio1_ick = {
1655         .name           = "gpio1_ick",
1656         .clkdm_name     = "l4ls_clkdm",
1657         .parent         = &l4ls_gclk,
1658         .enable_reg     = AM33XX_CM_PER_GPIO1_CLKCTRL,
1659         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1660         .ops            = &clkops_omap2_dflt,
1661         .recalc         = &followparent_recalc,
1662 };
1663
1664 static struct clk gpio2_dbclk = {
1665         .name           = "gpio2_dbclk",
1666         .clkdm_name     = "l4ls_clkdm",
1667         .parent         = &clkdiv32k_ick,
1668         .enable_reg     = AM33XX_CM_PER_GPIO2_CLKCTRL,
1669         .enable_bit     = AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT,
1670         .ops            = &clkops_omap2_dflt,
1671         .recalc         = &followparent_recalc,
1672 };
1673
1674 static struct clk gpio2_ick = {
1675         .name           = "gpio2_ick",
1676         .clkdm_name     = "l4ls_clkdm",
1677         .parent         = &l4ls_gclk,
1678         .enable_reg     = AM33XX_CM_PER_GPIO2_CLKCTRL,
1679         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1680         .ops            = &clkops_omap2_dflt,
1681         .recalc         = &followparent_recalc,
1682 };
1683
1684 static struct clk gpio3_dbclk = {
1685         .name           = "gpio3_dbclk",
1686         .clkdm_name     = "l4ls_clkdm",
1687         .parent         = &clkdiv32k_ick,
1688         .enable_reg     = AM33XX_CM_PER_GPIO3_CLKCTRL,
1689         .enable_bit     = AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT,
1690         .ops            = &clkops_omap2_dflt,
1691         .recalc         = &followparent_recalc,
1692 };
1693
1694 static struct clk gpio3_ick = {
1695         .name           = "gpio3_ick",
1696         .clkdm_name     = "l4ls_clkdm",
1697         .parent         = &l4ls_gclk,
1698         .enable_reg     = AM33XX_CM_PER_GPIO3_CLKCTRL,
1699         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1700         .ops            = &clkops_omap2_dflt,
1701         .recalc         = &followparent_recalc,
1702 };
1703
1704 static const struct clksel pruss_ocp_clk_mux_sel[] = {
1705         { .parent = &l3_gclk, .rates = div_1_0_rates },
1706         { .parent = &disp_pll_clk, .rates = div_1_1_rates },
1707         { .parent = NULL },
1708 };
1709
1710 static struct clk pruss_ocp_gclk = {
1711         .name           = "pruss_ocp_gclk",
1712         .parent         = &l3_gclk,
1713         .init           = &omap2_init_clksel_parent,
1714         .clksel         = pruss_ocp_clk_mux_sel,
1715         .clksel_reg     = AM33XX_CLKSEL_PRUSS_OCP_CLK,
1716         .clksel_mask    = AM33XX_CLKSEL_0_0_MASK,
1717         .ops            = &clkops_null,
1718         .recalc         = &followparent_recalc,
1719 };
1720
1721 static struct clk pruss_iep_gclk = {
1722         .name           = "pruss_iep_gclk",
1723         .clkdm_name     = "pruss_ocp_clkdm",
1724         .parent         = &l3_gclk,
1725         .ops            = &clkops_null,
1726         .recalc         = &followparent_recalc,
1727 };
1728
1729 static struct clk pruss_uart_gclk = {
1730         .name           = "pruss_uart_gclk",
1731         .clkdm_name     = "pruss_ocp_clkdm",
1732         .parent         = &per_192mhz_clk,
1733         .enable_reg     = AM33XX_CM_PER_PRUSS_CLKCTRL,
1734         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1735         .ops            = &clkops_omap2_dflt,
1736         .recalc         = &followparent_recalc,
1737 };
1738
1739 static struct clk lcdc_ick = {
1740         .name           = "lcdc_ick",
1741         .clkdm_name     = "l3_clkdm",
1742         .parent         = &sysclk1_ck,
1743         .ops            = &clkops_null,
1744         .recalc         = &followparent_recalc,
1745 };
1746
1747 static const struct clksel lcd_clk_mux_sel[] = {
1748         { .parent = &disp_pll_clk, .rates = div_1_0_rates },
1749         { .parent = &sysclk2_ck, .rates = div_1_1_rates },
1750         { .parent = &per_192mhz_clk, .rates = div_1_2_rates },
1751         { .parent = NULL },
1752 };
1753
1754 static struct clk lcd_gclk = {
1755         .name           = "lcd_gclk",
1756         .parent         = &disp_pll_clk,
1757         .init           = &omap2_init_clksel_parent,
1758         .clksel         = lcd_clk_mux_sel,
1759         .clksel_reg     = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
1760         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
1761         .ops            = &clkops_null,
1762         .recalc         = &followparent_recalc,
1763 };
1764
1765 static struct clk lcdc_fck = {
1766         .name           = "lcdc_fck",
1767         .clkdm_name     = "lcdc_clkdm",
1768         .parent         = &lcd_gclk,
1769         .enable_reg     = AM33XX_CM_PER_LCDC_CLKCTRL,
1770         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1771         .ops            = &clkops_omap2_dflt,
1772         .recalc         = &followparent_recalc,
1773 };
1774
1775 static struct clk mmc_clk = {
1776         .name           = "mmc_clk",
1777         .parent         = &per_192mhz_clk,
1778         .ops            = &clkops_null,
1779         .fixed_div      = 2,
1780         .recalc         = &omap_fixed_divisor_recalc,
1781 };
1782
1783 static struct clk mmc0_ick = {
1784         .name           = "mmc0_ick",
1785         .parent         = &l4ls_gclk,
1786         .ops            = &clkops_null,
1787         .recalc         = &followparent_recalc,
1788 };
1789
1790 static struct clk mmc0_fck = {
1791         .name           = "mmc0_fck",
1792         .clkdm_name     = "l4ls_clkdm",
1793         .parent         = &mmc_clk,
1794         .enable_reg     = AM33XX_CM_PER_MMC0_CLKCTRL,
1795         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1796         .ops            = &clkops_omap2_dflt,
1797         .recalc         = &followparent_recalc,
1798 };
1799
1800 static struct clk mmc1_ick = {
1801         .name           = "mmc1_ick",
1802         .parent         = &l4ls_gclk,
1803         .ops            = &clkops_null,
1804         .recalc         = &followparent_recalc,
1805 };
1806
1807 static struct clk mmc1_fck = {
1808         .name           = "mmc1_fck",
1809         .clkdm_name     = "l4ls_clkdm",
1810         .parent         = &mmc_clk,
1811         .enable_reg     = AM33XX_CM_PER_MMC1_CLKCTRL,
1812         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1813         .ops            = &clkops_omap2_dflt,
1814         .recalc         = &followparent_recalc,
1815 };
1816
1817 static struct clk mmc2_ick = {
1818         .name           = "mmc2_ick",
1819         .parent         = &l4ls_gclk,
1820         .ops            = &clkops_null,
1821         .recalc         = &followparent_recalc,
1822 };
1823
1824 static struct clk mmc2_fck = {
1825         .name           = "mmc2_fck",
1826         .clkdm_name     = "l3s_clkdm",
1827         .parent         = &mmc_clk,
1828         .enable_reg     = AM33XX_CM_PER_MMC2_CLKCTRL,
1829         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1830         .ops            = &clkops_omap2_dflt,
1831         .recalc         = &followparent_recalc,
1832 };
1833
1834 static const struct clksel gfx_clksel_sel[] = {
1835         { .parent = &sysclk1_ck, .rates = div_1_0_rates },
1836         { .parent = &per_192mhz_clk, .rates = div_1_1_rates },
1837         { .parent = NULL },
1838 };
1839
1840 static struct clk gfx_fclk_clksel_ck = {
1841         .name           = "gfx_fclk_clksel_ck",
1842         .parent         = &sysclk1_ck,
1843         .clksel         = gfx_clksel_sel,
1844         .ops            = &clkops_null,
1845         .clksel_reg     = AM33XX_CLKSEL_GFX_FCLK,
1846         .clksel_mask    = AM33XX_CLKSEL_GFX_FCLK_MASK,
1847         .recalc         = &omap2_clksel_recalc,
1848 };
1849
1850 static const struct clksel_rate div_1_0_2_1_rates[] = {
1851         { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
1852         { .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
1853         { .div = 0 },
1854 };
1855
1856 static const struct clksel gfx_div_sel[] = {
1857         { .parent = &gfx_fclk_clksel_ck, .rates = div_1_0_2_1_rates },
1858         { .parent = NULL },
1859 };
1860
1861 static struct clk gfx_ick = {
1862         .name           = "gfx_ick",
1863         .clkdm_name     = "gfx_l3_clkdm",
1864         .parent         = &gfx_l3_gclk,
1865         .ops            = &clkops_null,
1866         .recalc         = &followparent_recalc,
1867 };
1868
1869 static struct clk gfx_fclk = {
1870         .name           = "gfx_fclk",
1871         .clkdm_name     = "gfx_l3_clkdm",
1872         .parent         = &gfx_fclk_clksel_ck,
1873         .clksel         = gfx_div_sel,
1874         .enable_reg     = AM33XX_CM_GFX_GFX_CLKCTRL,
1875         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1876         .clksel_reg     = AM33XX_CLKSEL_GFX_FCLK,
1877         .clksel_mask    = AM33XX_CLKSEL_0_0_MASK,
1878         .recalc         = &omap2_clksel_recalc,
1879         .round_rate     = &omap2_clksel_round_rate,
1880         .set_rate       = &omap2_clksel_set_rate,
1881         .ops            = &clkops_omap2_dflt,
1882 };
1883
1884 static const struct clksel sysclkout_pre_sel[] = {
1885         { .parent = &clk_32768_ck, .rates = div_1_0_rates },
1886         { .parent = &l3_gclk, .rates = div_1_1_rates },
1887         { .parent = &ddr_pll_clk, .rates = div_1_2_rates },
1888         { .parent = &per_192mhz_clk, .rates = div_1_3_rates },
1889         { .parent = &lcd_gclk, .rates = div_1_4_rates },
1890         { .parent = NULL },
1891 };
1892
1893 static struct clk sysclkout_pre_ck = {
1894         .name           = "sysclkout_pre_ck",
1895         .parent         = &clk_32768_ck,
1896         .init           = &omap2_init_clksel_parent,
1897         .clksel         = sysclkout_pre_sel,
1898         .clksel_reg     = AM33XX_CM_CLKOUT_CTRL,
1899         .clksel_mask    = AM33XX_CLKOUT2SOURCE_MASK,
1900         .ops            = &clkops_null,
1901         .recalc         = &omap2_clksel_recalc,
1902 };
1903
1904 /* Divide by 8 clock rates with default clock is 1/1*/
1905 static const struct clksel_rate div8_rates[] = {
1906         { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
1907         { .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
1908         { .div = 3, .val = 2, .flags = RATE_IN_AM33XX },
1909         { .div = 4, .val = 3, .flags = RATE_IN_AM33XX },
1910         { .div = 5, .val = 4, .flags = RATE_IN_AM33XX },
1911         { .div = 6, .val = 5, .flags = RATE_IN_AM33XX },
1912         { .div = 7, .val = 6, .flags = RATE_IN_AM33XX },
1913         { .div = 8, .val = 7, .flags = RATE_IN_AM33XX },
1914         { .div = 0 },
1915 };
1916
1917 static const struct clksel clkout2_div[] = {
1918         { .parent = &sysclkout_pre_ck, .rates = div8_rates },
1919         { .parent = NULL },
1920 };
1921
1922 static struct clk clkout2_ck = {
1923         .name           = "clkout2_ck",
1924         .parent         = &sysclkout_pre_ck,
1925         .ops            = &clkops_omap2_dflt,
1926         .clksel         = clkout2_div,
1927         .clksel_reg     = AM33XX_CM_CLKOUT_CTRL,
1928         .clksel_mask    = AM33XX_CLKOUT2DIV_MASK,
1929         .enable_reg     = AM33XX_CM_CLKOUT_CTRL,
1930         .enable_bit     = AM33XX_CLKOUT2EN_SHIFT,
1931         .recalc         = &omap2_clksel_recalc,
1932         .round_rate     = &omap2_clksel_round_rate,
1933         .set_rate       = &omap2_clksel_set_rate,
1934 };
1935
1936 static struct clk vtp_clk = {
1937         .name           = "vtp_clk",
1938         .parent         = &sys_clkin_ck,
1939         .ops            = &clkops_null,
1940         .fixed_div      = 2,
1941         .recalc         = &omap_fixed_divisor_recalc,
1942 };
1943
1944 static const struct clksel wdt_clkmux_sel[] = {
1945         { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
1946         { .parent = &clk_32khz_ck, .rates = div_1_1_rates },
1947         { .parent = NULL },
1948 };
1949
1950 static struct clk wdt0_ick = {
1951         .name           = "wdt0_ick",
1952         .parent         = &l4_wkup_gclk,
1953         .ops            = &clkops_null,
1954         .recalc         = &followparent_recalc,
1955 };
1956
1957 static struct clk wdt0_fck = {
1958         .name           = "wdt0_fck",
1959         .clkdm_name     = "l4_wkup_clkdm",
1960         .parent         = &clk_rc32k_ck,
1961         .clksel         = wdt_clkmux_sel,
1962         .enable_reg     = AM33XX_CM_WKUP_WDT0_CLKCTRL,
1963         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1964         .ops            = &clkops_omap2_dflt,
1965         .recalc         = &followparent_recalc,
1966 };
1967
1968 static struct clk wdt1_ick = {
1969         .name           = "wdt1_ick",
1970         .parent         = &l4_wkup_gclk,
1971         .ops            = &clkops_null,
1972         .recalc         = &followparent_recalc,
1973 };
1974
1975 static struct clk wdt1_fck = {
1976         .name           = "wdt1_fck",
1977         .clkdm_name     = "l4_wkup_clkdm",
1978         .parent         = &clk_rc32k_ck,
1979         .init           = &omap2_init_clksel_parent,
1980         .clksel         = wdt_clkmux_sel,
1981         .enable_reg     = AM33XX_CM_WKUP_WDT1_CLKCTRL,
1982         .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
1983         .clksel_reg     = AM33XX_CLKSEL_WDT1_CLK,
1984         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
1985         .ops            = &clkops_omap2_dflt,
1986         .recalc         = &omap2_clksel_recalc,
1987 };
1988
1989 /*
1990  * Provides clock definitions for enabling bits for Time base module in
1991  * PWMSS ctrl register.
1992  */
1993
1994 static struct clk ehrpwm0_tbclk = {
1995         .name           = "ehrpwm0_tbclk",
1996         .enable_reg     = AM33XX_CONTROL_PWMSS_CTRL,
1997         .enable_bit     = AM33XX_PWMSS0_TBCLKEN,
1998         .ops            = &clkops_omap2_dflt,
1999         .flags          = ENABLE_ON_INIT,
2000 };
2001
2002 static struct clk ehrpwm1_tbclk = {
2003         .name           = "ehrpwm1_tbclk",
2004         .enable_reg     = AM33XX_CONTROL_PWMSS_CTRL,
2005         .enable_bit     = AM33XX_PWMSS1_TBCLKEN,
2006         .ops            = &clkops_omap2_dflt,
2007         .flags          = ENABLE_ON_INIT,
2008 };
2009
2010 static struct clk ehrpwm2_tbclk = {
2011         .name           = "ehrpwm2_tbclk",
2012         .enable_reg     = AM33XX_CONTROL_PWMSS_CTRL,
2013         .enable_bit     = AM33XX_PWMSS2_TBCLKEN,
2014         .ops            = &clkops_omap2_dflt,
2015         .flags          = ENABLE_ON_INIT,
2016 };
2017
2018
2019 /*
2020  * clkdev
2021  */
2022 static struct omap_clk am33xx_clks[] = {
2023         CLK(NULL,       "clk_32768_ck",         &clk_32768_ck,  CK_AM33XX),
2024         CLK(NULL,       "clk_32khz_ck",         &clk_32khz_ck,  CK_AM33XX),
2025         CLK(NULL,       "clk_rc32k_ck",         &clk_rc32k_ck,  CK_AM33XX),
2026         CLK(NULL,       "virt_19_2m_ck",        &virt_19_2m_ck, CK_AM33XX),
2027         CLK(NULL,       "virt_24m_ck",          &virt_24m_ck,   CK_AM33XX),
2028         CLK(NULL,       "virt_25m_ck",          &virt_25m_ck,   CK_AM33XX),
2029         CLK(NULL,       "virt_26m_ck",          &virt_26m_ck,   CK_AM33XX),
2030         CLK(NULL,       "sys_clkin_ck",         &sys_clkin_ck,  CK_AM33XX),
2031         CLK(NULL,       "tclkin_ck",            &tclkin_ck,     CK_AM33XX),
2032         CLK(NULL,       "dpll_core_ck",         &dpll_core_ck,          CK_AM33XX),
2033         CLK(NULL,       "dpll_core_x2_ck",      &dpll_core_x2_ck,       CK_AM33XX),
2034         CLK(NULL,       "dpll_core_m4_ck",      &dpll_core_m4_ck,       CK_AM33XX),
2035         CLK(NULL,       "dpll_core_m5_ck",      &dpll_core_m5_ck,       CK_AM33XX),
2036         CLK(NULL,       "dpll_core_m6_ck",      &dpll_core_m6_ck,       CK_AM33XX),
2037         CLK(NULL,       "sysclk1_ck",           &sysclk1_ck,    CK_AM33XX),
2038         CLK(NULL,       "sysclk2_ck",           &sysclk2_ck,    CK_AM33XX),
2039         CLK(NULL,       "core_clk_out",         &core_clk_out,  CK_AM33XX),
2040         CLK(NULL,       "clk_32khz_timer",      &clk_32khz_timer, CK_AM33XX),
2041         CLK(NULL,       "dpll_mpu_ck",          &dpll_mpu_ck,           CK_AM33XX),
2042         CLK(NULL,       "dpll_mpu_m2_ck",       &dpll_mpu_m2_ck,        CK_AM33XX),
2043         CLK(NULL,       "mpu_ck",               &mpu_fck,       CK_AM33XX),
2044         CLK(NULL,       "dpll_ddr_ck",          &dpll_ddr_ck,           CK_AM33XX),
2045         CLK(NULL,       "dpll_ddr_m2_ck",       &dpll_ddr_m2_ck,        CK_AM33XX),
2046         CLK(NULL,       "ddr_pll_clk",          &ddr_pll_clk,   CK_AM33XX),
2047         CLK(NULL,       "emif_fck",             &emif_fck,      CK_AM33XX),
2048         CLK(NULL,       "emif_fw_fck",          &emif_fw_fck,   CK_AM33XX),
2049         CLK(NULL,       "dpll_disp_ck",         &dpll_disp_ck,          CK_AM33XX),
2050         CLK(NULL,       "dpll_disp_m2_ck",      &dpll_disp_m2_ck,       CK_AM33XX),
2051         CLK(NULL,       "disp_pll_clk",         &disp_pll_clk,          CK_AM33XX),
2052         CLK(NULL,       "dpll_per_ck",          &dpll_per_ck,   CK_AM33XX),
2053         CLK(NULL,       "dpll_per_m2_ck",       &dpll_per_m2_ck,        CK_AM33XX),
2054         CLK(NULL,       "per_192mhz_clk",       &per_192mhz_clk,        CK_AM33XX),
2055         CLK(NULL,       "usb_pll_clk",          &usb_pll_clk,           CK_AM33XX),
2056         CLK(NULL,       "core_100mhz_ck",       &core_100mhz_ck,        CK_AM33XX),
2057         CLK(NULL,       "l3_ick",               &l3_ick,        CK_AM33XX),
2058         CLK(NULL,       "l3_instr_ick",         &l3_instr_ick,  CK_AM33XX),
2059         CLK(NULL,       "adc_tsc_fck",          &adc_tsc_fck,   CK_AM33XX),
2060         CLK(NULL,       "adc_tsc_ick",          &adc_tsc_ick,   CK_AM33XX),
2061         CLK(NULL,       "aes0_fck",             &aes0_fck,      CK_AM33XX),
2062         CLK(NULL,       "l4_cefuse_gclk",       &l4_cefuse_gclk, CK_AM33XX),
2063         CLK(NULL,       "cefuse_fck",           &cefuse_fck,    CK_AM33XX),
2064         CLK(NULL,       "cefuse_iclk",          &cefuse_iclk,   CK_AM33XX),
2065         CLK(NULL,       "clkdiv32k_ick",        &clkdiv32k_ick, CK_AM33XX),
2066         CLK(NULL,       "control_fck",          &control_fck,   CK_AM33XX),
2067         CLK("cpsw.0",   NULL,                   &cpgmac0_ick,   CK_AM33XX),
2068         CLK("d_can.0",  "fck",                  &dcan0_fck,     CK_AM33XX),
2069         CLK("d_can.1",  "fck",                  &dcan1_fck,     CK_AM33XX),
2070         CLK("d_can.0",  "ick",                  &dcan0_ick,     CK_AM33XX),
2071         CLK("d_can.1",  "ick",                  &dcan1_ick,     CK_AM33XX),
2072         CLK(NULL,       "debugss_ick",          &debugss_ick,   CK_AM33XX),
2073         CLK(NULL,       "elm_fck",              &elm_fck,       CK_AM33XX),
2074         CLK(NULL,       "epwmss0_fck",          &epwmss0_fck,   CK_AM33XX),
2075         CLK(NULL,       "epwmss1_fck",          &epwmss1_fck,   CK_AM33XX),
2076         CLK(NULL,       "epwmss2_fck",          &epwmss2_fck,   CK_AM33XX),
2077         CLK(NULL,       "gpio0_ick",            &gpio0_ick,     CK_AM33XX),
2078         CLK(NULL,       "gpio1_ick",            &gpio1_ick,     CK_AM33XX),
2079         CLK(NULL,       "gpio2_ick",            &gpio2_ick,     CK_AM33XX),
2080         CLK(NULL,       "gpio3_ick",            &gpio3_ick,     CK_AM33XX),
2081         CLK(NULL,       "gpmc_fck",             &gpmc_fck,      CK_AM33XX),
2082         CLK("omap_i2c.1",       "fck",          &i2c1_fck,      CK_AM33XX),
2083         CLK("omap_i2c.1",       "ick",          &i2c1_ick,      CK_AM33XX),
2084         CLK("omap_i2c.2",       "fck",          &i2c2_fck,      CK_AM33XX),
2085         CLK("omap_i2c.2",       "ick",          &i2c2_ick,      CK_AM33XX),
2086         CLK("omap_i2c.3",       "fck",          &i2c3_fck,      CK_AM33XX),
2087         CLK("omap_i2c.3",       "ick",          &i2c3_ick,      CK_AM33XX),
2088         CLK(NULL,       "pruss_ocp_gclk",       &pruss_ocp_gclk,        CK_AM33XX),
2089         CLK(NULL,       "pruss_uart_gclk",      &pruss_uart_gclk,       CK_AM33XX),
2090         CLK(NULL,       "pruss_iep_gclk",       &pruss_iep_gclk,        CK_AM33XX),
2091         CLK(NULL,       "ieee5000_fck",         &ieee5000_fck,  CK_AM33XX),
2092         CLK(NULL,       "l4hs_ick",             &l4hs_ick,      CK_AM33XX),
2093         CLK(NULL,       "l4wkup_ick",           &l4wkup_ick,    CK_AM33XX),
2094         CLK(NULL,       "l4fw_ick",             &l4fw_ick,      CK_AM33XX),
2095         CLK(NULL,       "l4ls_ick",             &l4ls_ick,      CK_AM33XX),
2096         CLK("da8xx_lcdc.0",     NULL,           &lcdc_fck,      CK_AM33XX),
2097         CLK(NULL,       "mailbox0_fck",         &mailbox0_fck,  CK_AM33XX),
2098         CLK(NULL,       "mcasp1_ick",           &mcasp0_ick,    CK_AM33XX),
2099         CLK("davinci-mcasp.0",  NULL,           &mcasp0_fck,    CK_AM33XX),
2100         CLK(NULL,       "mcasp2_ick",           &mcasp1_ick,    CK_AM33XX),
2101         CLK("davinci-mcasp.1",  NULL,           &mcasp1_fck,    CK_AM33XX),
2102         CLK(NULL,       "mlb_fck",              &mlb_fck,       CK_AM33XX),
2103         CLK("omap_hsmmc.0",     "ick",          &mmc0_ick,      CK_AM33XX),
2104         CLK("omap_hsmmc.1",     "ick",          &mmc1_ick,      CK_AM33XX),
2105         CLK("omap_hsmmc.2",     "ick",          &mmc2_ick,      CK_AM33XX),
2106         CLK("omap_hsmmc.0",     "fck",          &mmc0_fck,      CK_AM33XX),
2107         CLK("omap_hsmmc.1",     "fck",          &mmc1_fck,      CK_AM33XX),
2108         CLK("omap_hsmmc.2",     "fck",          &mmc2_fck,      CK_AM33XX),
2109         CLK(NULL,       "mmu_fck",              &mmu_fck,       CK_AM33XX),
2110         CLK(NULL,       "ocmcram_ick",          &ocmcram_ick,   CK_AM33XX),
2111         CLK(NULL,       "ocpwp_fck",            &ocpwp_fck,     CK_AM33XX),
2112         CLK(NULL,       "pka_fck",              &pka_fck,       CK_AM33XX),
2113         CLK(NULL,       "rng_fck",              &rng_fck,       CK_AM33XX),
2114         CLK(NULL,       "rtc_fck",              &rtc_fck,       CK_AM33XX),
2115         CLK(NULL,       "rtc_ick",              &rtc_ick,       CK_AM33XX),
2116         CLK(NULL,       "sha0_fck",             &sha0_fck,      CK_AM33XX),
2117         CLK(NULL,       "smartreflex0_fck",     &smartreflex0_fck,      CK_AM33XX),
2118         CLK(NULL,       "smartreflex0_ick",     &smartreflex0_ick,      CK_AM33XX),
2119         CLK(NULL,       "smartreflex1_fck",     &smartreflex1_fck,      CK_AM33XX),
2120         CLK(NULL,       "smartreflex1_ick",     &smartreflex1_ick,      CK_AM33XX),
2121         CLK("omap2_mcspi.1",    "fck",          &spi0_fck,      CK_AM33XX),
2122         CLK("omap2_mcspi.2",    "fck",          &spi1_fck,      CK_AM33XX),
2123         CLK("omap2_mcspi.1",    "ick",          &spi0_ick,      CK_AM33XX),
2124         CLK("omap2_mcspi.2",    "ick",          &spi1_ick,      CK_AM33XX),
2125         CLK(NULL,       "spinlock_fck",         &spinlock_fck,  CK_AM33XX),
2126         CLK(NULL,       "gpt0_fck",             &timer0_fck,    CK_AM33XX),
2127         CLK(NULL,       "gpt1_fck",             &timer1_fck,    CK_AM33XX),
2128         CLK(NULL,       "gpt2_fck",             &timer2_fck,    CK_AM33XX),
2129         CLK(NULL,       "gpt3_fck",             &timer3_fck,    CK_AM33XX),
2130         CLK(NULL,       "gpt4_fck",             &timer4_fck,    CK_AM33XX),
2131         CLK(NULL,       "gpt5_fck",             &timer5_fck,    CK_AM33XX),
2132         CLK(NULL,       "gpt6_fck",             &timer6_fck,    CK_AM33XX),
2133         CLK(NULL,       "gpt7_fck",             &timer7_fck,    CK_AM33XX),
2134         CLK("da8xx_lcdc.0",     "lcdc_ick",     &lcdc_ick,      CK_AM33XX),
2135         CLK(NULL,       "tpcc_ick",             &tpcc_ick,      CK_AM33XX),
2136         CLK(NULL,       "tptc0_ick",            &tptc0_ick,     CK_AM33XX),
2137         CLK(NULL,       "tptc1_ick",            &tptc1_ick,     CK_AM33XX),
2138         CLK(NULL,       "tptc2_ick",            &tptc2_ick,     CK_AM33XX),
2139         CLK(NULL,       "uart1_fck",            &uart1_fck,     CK_AM33XX),
2140         CLK(NULL,       "uart2_fck",            &uart2_fck,     CK_AM33XX),
2141         CLK(NULL,       "uart3_fck",            &uart3_fck,     CK_AM33XX),
2142         CLK(NULL,       "uart4_fck",            &uart4_fck,     CK_AM33XX),
2143         CLK(NULL,       "uart5_fck",            &uart5_fck,     CK_AM33XX),
2144         CLK(NULL,       "uart6_fck",            &uart6_fck,     CK_AM33XX),
2145         CLK(NULL,       "uart1_ick",            &uart1_ick,     CK_AM33XX),
2146         CLK(NULL,       "uart2_ick",            &uart2_ick,     CK_AM33XX),
2147         CLK(NULL,       "uart3_ick",            &uart3_ick,     CK_AM33XX),
2148         CLK(NULL,       "uart4_ick",            &uart4_ick,     CK_AM33XX),
2149         CLK(NULL,       "uart5_ick",            &uart5_ick,     CK_AM33XX),
2150         CLK(NULL,       "uart6_ick",            &uart6_ick,     CK_AM33XX),
2151         CLK(NULL,       "usbotg_ick",           &usbotg_ick,    CK_AM33XX),
2152         CLK(NULL,       "usbotg_fck",           &usbotg_fck,    CK_AM33XX),
2153         CLK(NULL,       "wdt0_ick",             &wdt0_ick,      CK_AM33XX),
2154         CLK(NULL,       "wdt0_fck",             &wdt0_fck,      CK_AM33XX),
2155         CLK(NULL,       "wdt1_ick",             &wdt1_ick,      CK_AM33XX),
2156         CLK(NULL,       "wdt1_fck",             &wdt1_fck,      CK_AM33XX),
2157         CLK(NULL,       "wkup_m3_fck",          &wkup_m3_fck,   CK_AM33XX),
2158         CLK(NULL,       "l3_aon_gclk",          &l3_aon_gclk,           CK_AM33XX),
2159         CLK(NULL,       "l4_wkup_aon_gclk",     &l4_wkup_aon_gclk,      CK_AM33XX),
2160         CLK(NULL,       "l4_rtc_gclk",          &l4_rtc_gclk,           CK_AM33XX),
2161         CLK(NULL,       "l3_gclk",              &l3_gclk,               CK_AM33XX),
2162         CLK(NULL,       "gfx_l3_gclk",          &gfx_l3_gclk,           CK_AM33XX),
2163         CLK(NULL,       "l4_wkup_gclk",         &l4_wkup_gclk,          CK_AM33XX),
2164         CLK(NULL,       "l4hs_gclk",            &l4hs_gclk,             CK_AM33XX),
2165         CLK(NULL,       "l3s_gclk",             &l3s_gclk,              CK_AM33XX),
2166         CLK(NULL,       "l4fw_gclk",            &l4fw_gclk,             CK_AM33XX),
2167         CLK(NULL,       "l4ls_gclk",            &l4ls_gclk,             CK_AM33XX),
2168         CLK(NULL,       "debug_clka_gclk",      &debug_clka_gclk,       CK_AM33XX),
2169         CLK(NULL,       "clk_24mhz",            &clk_24mhz,             CK_AM33XX),
2170         CLK(NULL,       "sysclk_div_ck",        &sysclk_div_ck,         CK_AM33XX),
2171         CLK(NULL,       "cpsw_250mhz_clk",      &cpsw_250mhz_clk,       CK_AM33XX),
2172         CLK(NULL,       "cpsw_125mhz_gclk",     &cpsw_125mhz_gclk,      CK_AM33XX),
2173         CLK(NULL,       "cpsw_50mhz_clk",       &cpsw_50mhz_clk,        CK_AM33XX),
2174         CLK(NULL,       "cpsw_5mhz_clk",        &cpsw_5mhz_clk,         CK_AM33XX),
2175         CLK(NULL,       "cpsw_cpts_rft_clk",    &cpsw_cpts_rft_clk,     CK_AM33XX),
2176         CLK(NULL,       "gpio0_dbclk_mux_ck",   &gpio0_dbclk_mux_ck,    CK_AM33XX),
2177         CLK(NULL,       "gpio0_dbclk",          &gpio0_dbclk,           CK_AM33XX),
2178         CLK(NULL,       "gpio1_dbclk",          &gpio1_dbclk,           CK_AM33XX),
2179         CLK(NULL,       "gpio2_dbclk",          &gpio2_dbclk,           CK_AM33XX),
2180         CLK(NULL,       "gpio3_dbclk",          &gpio3_dbclk,           CK_AM33XX),
2181         CLK(NULL,       "lcd_gclk",             &lcd_gclk,              CK_AM33XX),
2182         CLK(NULL,       "mmc_clk",              &mmc_clk,               CK_AM33XX),
2183         CLK(NULL,       "gfx_fclk_clksel_ck",   &gfx_fclk_clksel_ck,    CK_AM33XX),
2184         CLK(NULL,       "gfx_fclk",             &gfx_fclk,              CK_AM33XX),
2185         CLK(NULL,       "gfx_ick",              &gfx_ick,               CK_AM33XX),
2186         CLK(NULL,       "sysclkout_pre_ck",     &sysclkout_pre_ck,      CK_AM33XX),
2187         CLK(NULL,       "clkout2_ck",           &clkout2_ck,            CK_AM33XX),
2188         CLK(NULL,       "gpt0_ick",             &timer0_ick,            CK_AM33XX),
2189         CLK(NULL,       "gpt1_ick",             &timer1_ick,            CK_AM33XX),
2190         CLK(NULL,       "gpt2_ick",             &timer2_ick,            CK_AM33XX),
2191         CLK(NULL,       "gpt3_ick",             &timer3_ick,            CK_AM33XX),
2192         CLK(NULL,       "gpt4_ick",             &timer4_ick,            CK_AM33XX),
2193         CLK(NULL,       "gpt5_ick",             &timer5_ick,            CK_AM33XX),
2194         CLK(NULL,       "gpt6_ick",             &timer6_ick,            CK_AM33XX),
2195         CLK(NULL,       "gpt7_ick",             &timer7_ick,            CK_AM33XX),
2196         CLK(NULL,       "vtp_clk",              &vtp_clk,               CK_AM33XX),
2197         CLK(NULL,       "ehrpwm0_tbclk",        &ehrpwm0_tbclk, CK_AM33XX),
2198         CLK(NULL,       "ehrpwm1_tbclk",        &ehrpwm1_tbclk, CK_AM33XX),
2199         CLK(NULL,       "ehrpwm2_tbclk",        &ehrpwm2_tbclk, CK_AM33XX),
2200 };
2201
2202 int __init am33xx_clk_init(void)
2203 {
2204         struct omap_clk *c;
2205         u32 cpu_clkflg;
2206
2207         if (cpu_is_am33xx()) {
2208                 cpu_mask = RATE_IN_AM33XX;
2209                 cpu_clkflg = CK_AM33XX;
2210         }
2211
2212         clk_init(&omap2_clk_functions);
2213
2214         for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
2215                 clk_preinit(c->lk.clk);
2216
2217         for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
2218                 if (c->cpu & cpu_clkflg) {
2219                         clkdev_add(&c->lk);
2220                         clk_register(c->lk.clk);
2221                         omap2_init_clk_clkdm(c->lk.clk);
2222                 }
2223
2224         recalculate_root_clocks();
2225
2226         /*
2227          * Only enable those clocks we will need, let the drivers
2228          * enable other clocks as necessary
2229          */
2230         clk_enable_init_clocks();
2231
2232         return 0;
2233 }